1.1 --- a/src/cpu/x86/vm/assembler_x86.cpp Wed Aug 15 16:49:38 2012 -0700
1.2 +++ b/src/cpu/x86/vm/assembler_x86.cpp Mon Aug 20 09:07:21 2012 -0700
1.3 @@ -999,32 +999,22 @@
1.4
1.5 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1.6 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.7 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1.8 - emit_byte(0x58);
1.9 - emit_byte(0xC0 | encode);
1.10 + emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1.11 }
1.12
1.13 void Assembler::addsd(XMMRegister dst, Address src) {
1.14 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.15 - InstructionMark im(this);
1.16 - simd_prefix(dst, dst, src, VEX_SIMD_F2);
1.17 - emit_byte(0x58);
1.18 - emit_operand(dst, src);
1.19 + emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1.20 }
1.21
1.22 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1.23 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.24 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1.25 - emit_byte(0x58);
1.26 - emit_byte(0xC0 | encode);
1.27 + emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1.28 }
1.29
1.30 void Assembler::addss(XMMRegister dst, Address src) {
1.31 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.32 - InstructionMark im(this);
1.33 - simd_prefix(dst, dst, src, VEX_SIMD_F3);
1.34 - emit_byte(0x58);
1.35 - emit_operand(dst, src);
1.36 + emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1.37 }
1.38
1.39 void Assembler::andl(Address dst, int32_t imm32) {
1.40 @@ -1052,36 +1042,6 @@
1.41 emit_arith(0x23, 0xC0, dst, src);
1.42 }
1.43
1.44 -void Assembler::andpd(XMMRegister dst, Address src) {
1.45 - NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.46 - InstructionMark im(this);
1.47 - simd_prefix(dst, dst, src, VEX_SIMD_66);
1.48 - emit_byte(0x54);
1.49 - emit_operand(dst, src);
1.50 -}
1.51 -
1.52 -void Assembler::andpd(XMMRegister dst, XMMRegister src) {
1.53 - NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.54 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1.55 - emit_byte(0x54);
1.56 - emit_byte(0xC0 | encode);
1.57 -}
1.58 -
1.59 -void Assembler::andps(XMMRegister dst, Address src) {
1.60 - NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.61 - InstructionMark im(this);
1.62 - simd_prefix(dst, dst, src, VEX_SIMD_NONE);
1.63 - emit_byte(0x54);
1.64 - emit_operand(dst, src);
1.65 -}
1.66 -
1.67 -void Assembler::andps(XMMRegister dst, XMMRegister src) {
1.68 - NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.69 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
1.70 - emit_byte(0x54);
1.71 - emit_byte(0xC0 | encode);
1.72 -}
1.73 -
1.74 void Assembler::bsfl(Register dst, Register src) {
1.75 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1.76 emit_byte(0x0F);
1.77 @@ -1246,61 +1206,42 @@
1.78 // NOTE: dbx seems to decode this as comiss even though the
1.79 // 0x66 is there. Strangly ucomisd comes out correct
1.80 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.81 - InstructionMark im(this);
1.82 - simd_prefix(dst, src, VEX_SIMD_66);
1.83 - emit_byte(0x2F);
1.84 - emit_operand(dst, src);
1.85 + emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1.86 }
1.87
1.88 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1.89 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.90 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1.91 - emit_byte(0x2F);
1.92 - emit_byte(0xC0 | encode);
1.93 + emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1.94 }
1.95
1.96 void Assembler::comiss(XMMRegister dst, Address src) {
1.97 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.98 - InstructionMark im(this);
1.99 - simd_prefix(dst, src, VEX_SIMD_NONE);
1.100 - emit_byte(0x2F);
1.101 - emit_operand(dst, src);
1.102 + emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1.103 }
1.104
1.105 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1.106 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.107 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1.108 - emit_byte(0x2F);
1.109 - emit_byte(0xC0 | encode);
1.110 + emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1.111 }
1.112
1.113 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1.114 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.115 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1.116 - emit_byte(0xE6);
1.117 - emit_byte(0xC0 | encode);
1.118 + emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1.119 }
1.120
1.121 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1.122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.123 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1.124 - emit_byte(0x5B);
1.125 - emit_byte(0xC0 | encode);
1.126 + emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1.127 }
1.128
1.129 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1.130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.131 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1.132 - emit_byte(0x5A);
1.133 - emit_byte(0xC0 | encode);
1.134 + emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1.135 }
1.136
1.137 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1.138 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.139 - InstructionMark im(this);
1.140 - simd_prefix(dst, dst, src, VEX_SIMD_F2);
1.141 - emit_byte(0x5A);
1.142 - emit_operand(dst, src);
1.143 + emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1.144 }
1.145
1.146 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1.147 @@ -1312,10 +1253,7 @@
1.148
1.149 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1.150 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.151 - InstructionMark im(this);
1.152 - simd_prefix(dst, dst, src, VEX_SIMD_F2);
1.153 - emit_byte(0x2A);
1.154 - emit_operand(dst, src);
1.155 + emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1.156 }
1.157
1.158 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1.159 @@ -1327,25 +1265,17 @@
1.160
1.161 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1.162 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.163 - InstructionMark im(this);
1.164 - simd_prefix(dst, dst, src, VEX_SIMD_F3);
1.165 - emit_byte(0x2A);
1.166 - emit_operand(dst, src);
1.167 + emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1.168 }
1.169
1.170 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1.171 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.172 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1.173 - emit_byte(0x5A);
1.174 - emit_byte(0xC0 | encode);
1.175 + emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1.176 }
1.177
1.178 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1.179 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.180 - InstructionMark im(this);
1.181 - simd_prefix(dst, dst, src, VEX_SIMD_F3);
1.182 - emit_byte(0x5A);
1.183 - emit_operand(dst, src);
1.184 + emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1.185 }
1.186
1.187
1.188 @@ -1373,32 +1303,22 @@
1.189
1.190 void Assembler::divsd(XMMRegister dst, Address src) {
1.191 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.192 - InstructionMark im(this);
1.193 - simd_prefix(dst, dst, src, VEX_SIMD_F2);
1.194 - emit_byte(0x5E);
1.195 - emit_operand(dst, src);
1.196 + emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1.197 }
1.198
1.199 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1.200 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.201 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1.202 - emit_byte(0x5E);
1.203 - emit_byte(0xC0 | encode);
1.204 + emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1.205 }
1.206
1.207 void Assembler::divss(XMMRegister dst, Address src) {
1.208 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.209 - InstructionMark im(this);
1.210 - simd_prefix(dst, dst, src, VEX_SIMD_F3);
1.211 - emit_byte(0x5E);
1.212 - emit_operand(dst, src);
1.213 + emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1.214 }
1.215
1.216 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1.217 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.218 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1.219 - emit_byte(0x5E);
1.220 - emit_byte(0xC0 | encode);
1.221 + emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1.222 }
1.223
1.224 void Assembler::emms() {
1.225 @@ -1634,16 +1554,12 @@
1.226
1.227 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1.228 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.229 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1.230 - emit_byte(0x28);
1.231 - emit_byte(0xC0 | encode);
1.232 + emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1.233 }
1.234
1.235 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1.236 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.237 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1.238 - emit_byte(0x28);
1.239 - emit_byte(0xC0 | encode);
1.240 + emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1.241 }
1.242
1.243 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1.244 @@ -1712,24 +1628,17 @@
1.245
1.246 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1.247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.248 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1.249 - emit_byte(0x6F);
1.250 - emit_byte(0xC0 | encode);
1.251 + emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1.252 }
1.253
1.254 void Assembler::movdqu(XMMRegister dst, Address src) {
1.255 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.256 - InstructionMark im(this);
1.257 - simd_prefix(dst, src, VEX_SIMD_F3);
1.258 - emit_byte(0x6F);
1.259 - emit_operand(dst, src);
1.260 + emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1.261 }
1.262
1.263 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1.264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.265 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1.266 - emit_byte(0x6F);
1.267 - emit_byte(0xC0 | encode);
1.268 + emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1.269 }
1.270
1.271 void Assembler::movdqu(Address dst, XMMRegister src) {
1.272 @@ -1810,10 +1719,7 @@
1.273 // The selection is done in MacroAssembler::movdbl() and movflt().
1.274 void Assembler::movlpd(XMMRegister dst, Address src) {
1.275 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.276 - InstructionMark im(this);
1.277 - simd_prefix(dst, dst, src, VEX_SIMD_66);
1.278 - emit_byte(0x12);
1.279 - emit_operand(dst, src);
1.280 + emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1.281 }
1.282
1.283 void Assembler::movq( MMXRegister dst, Address src ) {
1.284 @@ -1870,17 +1776,12 @@
1.285
1.286 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1.287 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.288 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1.289 - emit_byte(0x10);
1.290 - emit_byte(0xC0 | encode);
1.291 + emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1.292 }
1.293
1.294 void Assembler::movsd(XMMRegister dst, Address src) {
1.295 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.296 - InstructionMark im(this);
1.297 - simd_prefix(dst, src, VEX_SIMD_F2);
1.298 - emit_byte(0x10);
1.299 - emit_operand(dst, src);
1.300 + emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1.301 }
1.302
1.303 void Assembler::movsd(Address dst, XMMRegister src) {
1.304 @@ -1893,17 +1794,12 @@
1.305
1.306 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1.307 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.308 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1.309 - emit_byte(0x10);
1.310 - emit_byte(0xC0 | encode);
1.311 + emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1.312 }
1.313
1.314 void Assembler::movss(XMMRegister dst, Address src) {
1.315 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.316 - InstructionMark im(this);
1.317 - simd_prefix(dst, src, VEX_SIMD_F3);
1.318 - emit_byte(0x10);
1.319 - emit_operand(dst, src);
1.320 + emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1.321 }
1.322
1.323 void Assembler::movss(Address dst, XMMRegister src) {
1.324 @@ -2001,32 +1897,22 @@
1.325
1.326 void Assembler::mulsd(XMMRegister dst, Address src) {
1.327 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.328 - InstructionMark im(this);
1.329 - simd_prefix(dst, dst, src, VEX_SIMD_F2);
1.330 - emit_byte(0x59);
1.331 - emit_operand(dst, src);
1.332 + emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
1.333 }
1.334
1.335 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1.336 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.337 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1.338 - emit_byte(0x59);
1.339 - emit_byte(0xC0 | encode);
1.340 + emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
1.341 }
1.342
1.343 void Assembler::mulss(XMMRegister dst, Address src) {
1.344 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.345 - InstructionMark im(this);
1.346 - simd_prefix(dst, dst, src, VEX_SIMD_F3);
1.347 - emit_byte(0x59);
1.348 - emit_operand(dst, src);
1.349 + emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
1.350 }
1.351
1.352 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1.353 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.354 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1.355 - emit_byte(0x59);
1.356 - emit_byte(0xC0 | encode);
1.357 + emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
1.358 }
1.359
1.360 void Assembler::negl(Register dst) {
1.361 @@ -2315,17 +2201,12 @@
1.362 void Assembler::packuswb(XMMRegister dst, Address src) {
1.363 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.364 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
1.365 - InstructionMark im(this);
1.366 - simd_prefix(dst, dst, src, VEX_SIMD_66);
1.367 - emit_byte(0x67);
1.368 - emit_operand(dst, src);
1.369 + emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
1.370 }
1.371
1.372 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
1.373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.374 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1.375 - emit_byte(0x67);
1.376 - emit_byte(0xC0 | encode);
1.377 + emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
1.378 }
1.379
1.380 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
1.381 @@ -2339,7 +2220,7 @@
1.382
1.383 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
1.384 assert(VM_Version::supports_sse4_2(), "");
1.385 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
1.386 + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
1.387 emit_byte(0x61);
1.388 emit_byte(0xC0 | encode);
1.389 emit_byte(imm8);
1.390 @@ -2355,7 +2236,7 @@
1.391
1.392 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
1.393 assert(VM_Version::supports_sse4_1(), "");
1.394 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.395 + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.396 emit_byte(0x30);
1.397 emit_byte(0xC0 | encode);
1.398 }
1.399 @@ -2456,28 +2337,10 @@
1.400 a_byte(p);
1.401 }
1.402
1.403 -void Assembler::por(XMMRegister dst, XMMRegister src) {
1.404 - NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.405 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1.406 - emit_byte(0xEB);
1.407 - emit_byte(0xC0 | encode);
1.408 -}
1.409 -
1.410 -void Assembler::por(XMMRegister dst, Address src) {
1.411 - NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.412 - assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
1.413 - InstructionMark im(this);
1.414 - simd_prefix(dst, dst, src, VEX_SIMD_66);
1.415 - emit_byte(0xEB);
1.416 - emit_operand(dst, src);
1.417 -}
1.418 -
1.419 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
1.420 assert(isByte(mode), "invalid value");
1.421 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.422 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1.423 - emit_byte(0x70);
1.424 - emit_byte(0xC0 | encode);
1.425 + emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
1.426 emit_byte(mode & 0xFF);
1.427
1.428 }
1.429 @@ -2496,9 +2359,7 @@
1.430 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
1.431 assert(isByte(mode), "invalid value");
1.432 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.433 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1.434 - emit_byte(0x70);
1.435 - emit_byte(0xC0 | encode);
1.436 + emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
1.437 emit_byte(mode & 0xFF);
1.438 }
1.439
1.440 @@ -2513,18 +2374,6 @@
1.441 emit_byte(mode & 0xFF);
1.442 }
1.443
1.444 -void Assembler::psrlq(XMMRegister dst, int shift) {
1.445 - // Shift 64 bit value logically right by specified number of bits.
1.446 - // HMM Table D-1 says sse2 or mmx.
1.447 - // Do not confuse it with psrldq SSE2 instruction which
1.448 - // shifts 128 bit value in xmm register by number of bytes.
1.449 - NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.450 - int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
1.451 - emit_byte(0x73);
1.452 - emit_byte(0xC0 | encode);
1.453 - emit_byte(shift);
1.454 -}
1.455 -
1.456 void Assembler::psrldq(XMMRegister dst, int shift) {
1.457 // Shift 128 bit value in xmm register by number of bytes.
1.458 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.459 @@ -2545,7 +2394,7 @@
1.460
1.461 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
1.462 assert(VM_Version::supports_sse4_1(), "");
1.463 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.464 + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.465 emit_byte(0x17);
1.466 emit_byte(0xC0 | encode);
1.467 }
1.468 @@ -2553,40 +2402,28 @@
1.469 void Assembler::punpcklbw(XMMRegister dst, Address src) {
1.470 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.471 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
1.472 - InstructionMark im(this);
1.473 - simd_prefix(dst, dst, src, VEX_SIMD_66);
1.474 - emit_byte(0x60);
1.475 - emit_operand(dst, src);
1.476 + emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
1.477 }
1.478
1.479 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
1.480 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.481 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1.482 - emit_byte(0x60);
1.483 - emit_byte(0xC0 | encode);
1.484 + emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
1.485 }
1.486
1.487 void Assembler::punpckldq(XMMRegister dst, Address src) {
1.488 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.489 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
1.490 - InstructionMark im(this);
1.491 - simd_prefix(dst, dst, src, VEX_SIMD_66);
1.492 - emit_byte(0x62);
1.493 - emit_operand(dst, src);
1.494 + emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
1.495 }
1.496
1.497 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
1.498 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.499 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1.500 - emit_byte(0x62);
1.501 - emit_byte(0xC0 | encode);
1.502 + emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
1.503 }
1.504
1.505 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
1.506 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.507 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1.508 - emit_byte(0x6C);
1.509 - emit_byte(0xC0 | encode);
1.510 + emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
1.511 }
1.512
1.513 void Assembler::push(int32_t imm32) {
1.514 @@ -2616,22 +2453,6 @@
1.515 }
1.516 #endif
1.517
1.518 -void Assembler::pxor(XMMRegister dst, Address src) {
1.519 - NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.520 - assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
1.521 - InstructionMark im(this);
1.522 - simd_prefix(dst, dst, src, VEX_SIMD_66);
1.523 - emit_byte(0xEF);
1.524 - emit_operand(dst, src);
1.525 -}
1.526 -
1.527 -void Assembler::pxor(XMMRegister dst, XMMRegister src) {
1.528 - NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.529 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1.530 - emit_byte(0xEF);
1.531 - emit_byte(0xC0 | encode);
1.532 -}
1.533 -
1.534 void Assembler::rcll(Register dst, int imm8) {
1.535 assert(isShiftCount(imm8), "illegal shift count");
1.536 int encode = prefix_and_encode(dst->encoding());
1.537 @@ -2790,32 +2611,22 @@
1.538
1.539 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
1.540 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.541 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1.542 - emit_byte(0x51);
1.543 - emit_byte(0xC0 | encode);
1.544 + emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
1.545 }
1.546
1.547 void Assembler::sqrtsd(XMMRegister dst, Address src) {
1.548 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.549 - InstructionMark im(this);
1.550 - simd_prefix(dst, dst, src, VEX_SIMD_F2);
1.551 - emit_byte(0x51);
1.552 - emit_operand(dst, src);
1.553 + emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
1.554 }
1.555
1.556 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
1.557 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.558 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1.559 - emit_byte(0x51);
1.560 - emit_byte(0xC0 | encode);
1.561 + emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
1.562 }
1.563
1.564 void Assembler::sqrtss(XMMRegister dst, Address src) {
1.565 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.566 - InstructionMark im(this);
1.567 - simd_prefix(dst, dst, src, VEX_SIMD_F3);
1.568 - emit_byte(0x51);
1.569 - emit_operand(dst, src);
1.570 + emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
1.571 }
1.572
1.573 void Assembler::stmxcsr( Address dst) {
1.574 @@ -2865,32 +2676,22 @@
1.575
1.576 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
1.577 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.578 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1.579 - emit_byte(0x5C);
1.580 - emit_byte(0xC0 | encode);
1.581 + emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
1.582 }
1.583
1.584 void Assembler::subsd(XMMRegister dst, Address src) {
1.585 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.586 - InstructionMark im(this);
1.587 - simd_prefix(dst, dst, src, VEX_SIMD_F2);
1.588 - emit_byte(0x5C);
1.589 - emit_operand(dst, src);
1.590 + emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
1.591 }
1.592
1.593 void Assembler::subss(XMMRegister dst, XMMRegister src) {
1.594 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.595 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1.596 - emit_byte(0x5C);
1.597 - emit_byte(0xC0 | encode);
1.598 + emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
1.599 }
1.600
1.601 void Assembler::subss(XMMRegister dst, Address src) {
1.602 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.603 - InstructionMark im(this);
1.604 - simd_prefix(dst, dst, src, VEX_SIMD_F3);
1.605 - emit_byte(0x5C);
1.606 - emit_operand(dst, src);
1.607 + emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
1.608 }
1.609
1.610 void Assembler::testb(Register dst, int imm8) {
1.611 @@ -2928,32 +2729,22 @@
1.612
1.613 void Assembler::ucomisd(XMMRegister dst, Address src) {
1.614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.615 - InstructionMark im(this);
1.616 - simd_prefix(dst, src, VEX_SIMD_66);
1.617 - emit_byte(0x2E);
1.618 - emit_operand(dst, src);
1.619 + emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
1.620 }
1.621
1.622 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
1.623 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.624 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1.625 - emit_byte(0x2E);
1.626 - emit_byte(0xC0 | encode);
1.627 + emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
1.628 }
1.629
1.630 void Assembler::ucomiss(XMMRegister dst, Address src) {
1.631 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.632 - InstructionMark im(this);
1.633 - simd_prefix(dst, src, VEX_SIMD_NONE);
1.634 - emit_byte(0x2E);
1.635 - emit_operand(dst, src);
1.636 + emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
1.637 }
1.638
1.639 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
1.640 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.641 - int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1.642 - emit_byte(0x2E);
1.643 - emit_byte(0xC0 | encode);
1.644 + emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
1.645 }
1.646
1.647
1.648 @@ -2995,211 +2786,714 @@
1.649 emit_arith(0x33, 0xC0, dst, src);
1.650 }
1.651
1.652 +
1.653 +// AVX 3-operands scalar float-point arithmetic instructions
1.654 +
1.655 +void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
1.656 + assert(VM_Version::supports_avx(), "");
1.657 + emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
1.658 +}
1.659 +
1.660 +void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.661 + assert(VM_Version::supports_avx(), "");
1.662 + emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
1.663 +}
1.664 +
1.665 +void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
1.666 + assert(VM_Version::supports_avx(), "");
1.667 + emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
1.668 +}
1.669 +
1.670 +void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.671 + assert(VM_Version::supports_avx(), "");
1.672 + emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
1.673 +}
1.674 +
1.675 +void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
1.676 + assert(VM_Version::supports_avx(), "");
1.677 + emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
1.678 +}
1.679 +
1.680 +void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.681 + assert(VM_Version::supports_avx(), "");
1.682 + emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
1.683 +}
1.684 +
1.685 +void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
1.686 + assert(VM_Version::supports_avx(), "");
1.687 + emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
1.688 +}
1.689 +
1.690 +void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.691 + assert(VM_Version::supports_avx(), "");
1.692 + emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
1.693 +}
1.694 +
1.695 +void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
1.696 + assert(VM_Version::supports_avx(), "");
1.697 + emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
1.698 +}
1.699 +
1.700 +void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.701 + assert(VM_Version::supports_avx(), "");
1.702 + emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
1.703 +}
1.704 +
1.705 +void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
1.706 + assert(VM_Version::supports_avx(), "");
1.707 + emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
1.708 +}
1.709 +
1.710 +void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.711 + assert(VM_Version::supports_avx(), "");
1.712 + emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
1.713 +}
1.714 +
1.715 +void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
1.716 + assert(VM_Version::supports_avx(), "");
1.717 + emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
1.718 +}
1.719 +
1.720 +void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.721 + assert(VM_Version::supports_avx(), "");
1.722 + emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
1.723 +}
1.724 +
1.725 +void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
1.726 + assert(VM_Version::supports_avx(), "");
1.727 + emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
1.728 +}
1.729 +
1.730 +void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.731 + assert(VM_Version::supports_avx(), "");
1.732 + emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
1.733 +}
1.734 +
1.735 +//====================VECTOR ARITHMETIC=====================================
1.736 +
1.737 +// Float-point vector arithmetic
1.738 +
1.739 +void Assembler::addpd(XMMRegister dst, XMMRegister src) {
1.740 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.741 + emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
1.742 +}
1.743 +
1.744 +void Assembler::addps(XMMRegister dst, XMMRegister src) {
1.745 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.746 + emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
1.747 +}
1.748 +
1.749 +void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.750 + assert(VM_Version::supports_avx(), "");
1.751 + emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
1.752 +}
1.753 +
1.754 +void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.755 + assert(VM_Version::supports_avx(), "");
1.756 + emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
1.757 +}
1.758 +
1.759 +void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.760 + assert(VM_Version::supports_avx(), "");
1.761 + emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
1.762 +}
1.763 +
1.764 +void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.765 + assert(VM_Version::supports_avx(), "");
1.766 + emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
1.767 +}
1.768 +
1.769 +void Assembler::subpd(XMMRegister dst, XMMRegister src) {
1.770 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.771 + emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
1.772 +}
1.773 +
1.774 +void Assembler::subps(XMMRegister dst, XMMRegister src) {
1.775 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.776 + emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
1.777 +}
1.778 +
1.779 +void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.780 + assert(VM_Version::supports_avx(), "");
1.781 + emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
1.782 +}
1.783 +
1.784 +void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.785 + assert(VM_Version::supports_avx(), "");
1.786 + emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
1.787 +}
1.788 +
1.789 +void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.790 + assert(VM_Version::supports_avx(), "");
1.791 + emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
1.792 +}
1.793 +
1.794 +void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.795 + assert(VM_Version::supports_avx(), "");
1.796 + emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
1.797 +}
1.798 +
1.799 +void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
1.800 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.801 + emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
1.802 +}
1.803 +
1.804 +void Assembler::mulps(XMMRegister dst, XMMRegister src) {
1.805 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.806 + emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
1.807 +}
1.808 +
1.809 +void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.810 + assert(VM_Version::supports_avx(), "");
1.811 + emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
1.812 +}
1.813 +
1.814 +void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.815 + assert(VM_Version::supports_avx(), "");
1.816 + emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
1.817 +}
1.818 +
1.819 +void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.820 + assert(VM_Version::supports_avx(), "");
1.821 + emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
1.822 +}
1.823 +
1.824 +void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.825 + assert(VM_Version::supports_avx(), "");
1.826 + emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
1.827 +}
1.828 +
1.829 +void Assembler::divpd(XMMRegister dst, XMMRegister src) {
1.830 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.831 + emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
1.832 +}
1.833 +
1.834 +void Assembler::divps(XMMRegister dst, XMMRegister src) {
1.835 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.836 + emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
1.837 +}
1.838 +
1.839 +void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.840 + assert(VM_Version::supports_avx(), "");
1.841 + emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
1.842 +}
1.843 +
1.844 +void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.845 + assert(VM_Version::supports_avx(), "");
1.846 + emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
1.847 +}
1.848 +
1.849 +void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.850 + assert(VM_Version::supports_avx(), "");
1.851 + emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
1.852 +}
1.853 +
1.854 +void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.855 + assert(VM_Version::supports_avx(), "");
1.856 + emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
1.857 +}
1.858 +
1.859 +void Assembler::andpd(XMMRegister dst, XMMRegister src) {
1.860 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.861 + emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
1.862 +}
1.863 +
1.864 +void Assembler::andps(XMMRegister dst, XMMRegister src) {
1.865 + NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.866 + emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
1.867 +}
1.868 +
1.869 +void Assembler::andps(XMMRegister dst, Address src) {
1.870 + NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.871 + emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
1.872 +}
1.873 +
1.874 +void Assembler::andpd(XMMRegister dst, Address src) {
1.875 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.876 + emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
1.877 +}
1.878 +
1.879 +void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.880 + assert(VM_Version::supports_avx(), "");
1.881 + emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
1.882 +}
1.883 +
1.884 +void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.885 + assert(VM_Version::supports_avx(), "");
1.886 + emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
1.887 +}
1.888 +
1.889 +void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.890 + assert(VM_Version::supports_avx(), "");
1.891 + emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
1.892 +}
1.893 +
1.894 +void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.895 + assert(VM_Version::supports_avx(), "");
1.896 + emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
1.897 +}
1.898 +
1.899 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
1.900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.901 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1.902 - emit_byte(0x57);
1.903 - emit_byte(0xC0 | encode);
1.904 -}
1.905 -
1.906 -void Assembler::xorpd(XMMRegister dst, Address src) {
1.907 - NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.908 - InstructionMark im(this);
1.909 - simd_prefix(dst, dst, src, VEX_SIMD_66);
1.910 - emit_byte(0x57);
1.911 - emit_operand(dst, src);
1.912 -}
1.913 -
1.914 + emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
1.915 +}
1.916
1.917 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
1.918 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.919 - int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
1.920 - emit_byte(0x57);
1.921 - emit_byte(0xC0 | encode);
1.922 + emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
1.923 +}
1.924 +
1.925 +void Assembler::xorpd(XMMRegister dst, Address src) {
1.926 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.927 + emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
1.928 }
1.929
1.930 void Assembler::xorps(XMMRegister dst, Address src) {
1.931 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1.932 - InstructionMark im(this);
1.933 - simd_prefix(dst, dst, src, VEX_SIMD_NONE);
1.934 - emit_byte(0x57);
1.935 - emit_operand(dst, src);
1.936 -}
1.937 -
1.938 -// AVX 3-operands non destructive source instructions (encoded with VEX prefix)
1.939 -
1.940 -void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
1.941 - assert(VM_Version::supports_avx(), "");
1.942 - InstructionMark im(this);
1.943 - vex_prefix(dst, nds, src, VEX_SIMD_F2);
1.944 - emit_byte(0x58);
1.945 - emit_operand(dst, src);
1.946 -}
1.947 -
1.948 -void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.949 - assert(VM_Version::supports_avx(), "");
1.950 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
1.951 - emit_byte(0x58);
1.952 - emit_byte(0xC0 | encode);
1.953 -}
1.954 -
1.955 -void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
1.956 - assert(VM_Version::supports_avx(), "");
1.957 - InstructionMark im(this);
1.958 - vex_prefix(dst, nds, src, VEX_SIMD_F3);
1.959 - emit_byte(0x58);
1.960 - emit_operand(dst, src);
1.961 -}
1.962 -
1.963 -void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.964 - assert(VM_Version::supports_avx(), "");
1.965 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
1.966 - emit_byte(0x58);
1.967 - emit_byte(0xC0 | encode);
1.968 -}
1.969 -
1.970 -void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) {
1.971 - assert(VM_Version::supports_avx(), "");
1.972 - InstructionMark im(this);
1.973 - vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
1.974 - emit_byte(0x54);
1.975 - emit_operand(dst, src);
1.976 -}
1.977 -
1.978 -void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) {
1.979 - assert(VM_Version::supports_avx(), "");
1.980 - InstructionMark im(this);
1.981 - vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
1.982 - emit_byte(0x54);
1.983 - emit_operand(dst, src);
1.984 -}
1.985 -
1.986 -void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
1.987 - assert(VM_Version::supports_avx(), "");
1.988 - InstructionMark im(this);
1.989 - vex_prefix(dst, nds, src, VEX_SIMD_F2);
1.990 - emit_byte(0x5E);
1.991 - emit_operand(dst, src);
1.992 -}
1.993 -
1.994 -void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.995 - assert(VM_Version::supports_avx(), "");
1.996 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
1.997 - emit_byte(0x5E);
1.998 - emit_byte(0xC0 | encode);
1.999 -}
1.1000 -
1.1001 -void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
1.1002 - assert(VM_Version::supports_avx(), "");
1.1003 - InstructionMark im(this);
1.1004 - vex_prefix(dst, nds, src, VEX_SIMD_F3);
1.1005 - emit_byte(0x5E);
1.1006 - emit_operand(dst, src);
1.1007 -}
1.1008 -
1.1009 -void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.1010 - assert(VM_Version::supports_avx(), "");
1.1011 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
1.1012 - emit_byte(0x5E);
1.1013 - emit_byte(0xC0 | encode);
1.1014 -}
1.1015 -
1.1016 -void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
1.1017 - assert(VM_Version::supports_avx(), "");
1.1018 - InstructionMark im(this);
1.1019 - vex_prefix(dst, nds, src, VEX_SIMD_F2);
1.1020 - emit_byte(0x59);
1.1021 - emit_operand(dst, src);
1.1022 -}
1.1023 -
1.1024 -void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.1025 - assert(VM_Version::supports_avx(), "");
1.1026 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
1.1027 - emit_byte(0x59);
1.1028 - emit_byte(0xC0 | encode);
1.1029 -}
1.1030 -
1.1031 -void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
1.1032 - InstructionMark im(this);
1.1033 - vex_prefix(dst, nds, src, VEX_SIMD_F3);
1.1034 - emit_byte(0x59);
1.1035 - emit_operand(dst, src);
1.1036 -}
1.1037 -
1.1038 -void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.1039 - assert(VM_Version::supports_avx(), "");
1.1040 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
1.1041 - emit_byte(0x59);
1.1042 - emit_byte(0xC0 | encode);
1.1043 -}
1.1044 -
1.1045 -
1.1046 -void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
1.1047 - assert(VM_Version::supports_avx(), "");
1.1048 - InstructionMark im(this);
1.1049 - vex_prefix(dst, nds, src, VEX_SIMD_F2);
1.1050 - emit_byte(0x5C);
1.1051 - emit_operand(dst, src);
1.1052 -}
1.1053 -
1.1054 -void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.1055 - assert(VM_Version::supports_avx(), "");
1.1056 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
1.1057 - emit_byte(0x5C);
1.1058 - emit_byte(0xC0 | encode);
1.1059 -}
1.1060 -
1.1061 -void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
1.1062 - assert(VM_Version::supports_avx(), "");
1.1063 - InstructionMark im(this);
1.1064 - vex_prefix(dst, nds, src, VEX_SIMD_F3);
1.1065 - emit_byte(0x5C);
1.1066 - emit_operand(dst, src);
1.1067 -}
1.1068 -
1.1069 -void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.1070 - assert(VM_Version::supports_avx(), "");
1.1071 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
1.1072 - emit_byte(0x5C);
1.1073 - emit_byte(0xC0 | encode);
1.1074 -}
1.1075 -
1.1076 -void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) {
1.1077 - assert(VM_Version::supports_avx(), "");
1.1078 - InstructionMark im(this);
1.1079 - vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
1.1080 - emit_byte(0x57);
1.1081 - emit_operand(dst, src);
1.1082 + emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
1.1083 }
1.1084
1.1085 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1086 assert(VM_Version::supports_avx(), "");
1.1087 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256);
1.1088 - emit_byte(0x57);
1.1089 - emit_byte(0xC0 | encode);
1.1090 -}
1.1091 -
1.1092 -void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) {
1.1093 - assert(VM_Version::supports_avx(), "");
1.1094 - InstructionMark im(this);
1.1095 - vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
1.1096 - emit_byte(0x57);
1.1097 - emit_operand(dst, src);
1.1098 + emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
1.1099 }
1.1100
1.1101 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1102 assert(VM_Version::supports_avx(), "");
1.1103 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, vector256);
1.1104 - emit_byte(0x57);
1.1105 + emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
1.1106 +}
1.1107 +
1.1108 +void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1109 + assert(VM_Version::supports_avx(), "");
1.1110 + emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
1.1111 +}
1.1112 +
1.1113 +void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1114 + assert(VM_Version::supports_avx(), "");
1.1115 + emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
1.1116 +}
1.1117 +
1.1118 +
1.1119 +// Integer vector arithmetic
1.1120 +void Assembler::paddb(XMMRegister dst, XMMRegister src) {
1.1121 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1122 + emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
1.1123 +}
1.1124 +
1.1125 +void Assembler::paddw(XMMRegister dst, XMMRegister src) {
1.1126 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1127 + emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
1.1128 +}
1.1129 +
1.1130 +void Assembler::paddd(XMMRegister dst, XMMRegister src) {
1.1131 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1132 + emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
1.1133 +}
1.1134 +
1.1135 +void Assembler::paddq(XMMRegister dst, XMMRegister src) {
1.1136 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1137 + emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
1.1138 +}
1.1139 +
1.1140 +void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1141 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1142 + emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
1.1143 +}
1.1144 +
1.1145 +void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1146 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1147 + emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
1.1148 +}
1.1149 +
1.1150 +void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1151 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1152 + emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
1.1153 +}
1.1154 +
1.1155 +void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1156 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1157 + emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
1.1158 +}
1.1159 +
1.1160 +void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1161 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1162 + emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
1.1163 +}
1.1164 +
1.1165 +void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1166 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1167 + emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
1.1168 +}
1.1169 +
1.1170 +void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1171 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1172 + emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
1.1173 +}
1.1174 +
1.1175 +void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1176 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1177 + emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
1.1178 +}
1.1179 +
1.1180 +void Assembler::psubb(XMMRegister dst, XMMRegister src) {
1.1181 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1182 + emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
1.1183 +}
1.1184 +
1.1185 +void Assembler::psubw(XMMRegister dst, XMMRegister src) {
1.1186 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1187 + emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
1.1188 +}
1.1189 +
1.1190 +void Assembler::psubd(XMMRegister dst, XMMRegister src) {
1.1191 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1192 + emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
1.1193 +}
1.1194 +
1.1195 +void Assembler::psubq(XMMRegister dst, XMMRegister src) {
1.1196 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1197 + emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
1.1198 +}
1.1199 +
1.1200 +void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1201 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1202 + emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
1.1203 +}
1.1204 +
1.1205 +void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1206 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1207 + emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
1.1208 +}
1.1209 +
1.1210 +void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1211 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1212 + emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
1.1213 +}
1.1214 +
1.1215 +void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1216 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1217 + emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
1.1218 +}
1.1219 +
1.1220 +void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1221 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1222 + emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
1.1223 +}
1.1224 +
1.1225 +void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1226 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1227 + emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
1.1228 +}
1.1229 +
1.1230 +void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1231 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1232 + emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
1.1233 +}
1.1234 +
1.1235 +void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1236 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1237 + emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
1.1238 +}
1.1239 +
1.1240 +void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
1.1241 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1242 + emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
1.1243 +}
1.1244 +
1.1245 +void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
1.1246 + assert(VM_Version::supports_sse4_1(), "");
1.1247 + int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1.1248 + emit_byte(0x40);
1.1249 emit_byte(0xC0 | encode);
1.1250 }
1.1251
1.1252 +void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1253 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1254 + emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
1.1255 +}
1.1256 +
1.1257 +void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1258 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1259 + int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
1.1260 + emit_byte(0x40);
1.1261 + emit_byte(0xC0 | encode);
1.1262 +}
1.1263 +
1.1264 +void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1265 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1266 + emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
1.1267 +}
1.1268 +
1.1269 +void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1270 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1271 + InstructionMark im(this);
1.1272 + int dst_enc = dst->encoding();
1.1273 + int nds_enc = nds->is_valid() ? nds->encoding() : 0;
1.1274 + vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
1.1275 + emit_byte(0x40);
1.1276 + emit_operand(dst, src);
1.1277 +}
1.1278 +
1.1279 +// Shift packed integers left by specified number of bits.
1.1280 +void Assembler::psllw(XMMRegister dst, int shift) {
1.1281 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1282 + // XMM6 is for /6 encoding: 66 0F 71 /6 ib
1.1283 + int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
1.1284 + emit_byte(0x71);
1.1285 + emit_byte(0xC0 | encode);
1.1286 + emit_byte(shift & 0xFF);
1.1287 +}
1.1288 +
1.1289 +void Assembler::pslld(XMMRegister dst, int shift) {
1.1290 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1291 + // XMM6 is for /6 encoding: 66 0F 72 /6 ib
1.1292 + int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
1.1293 + emit_byte(0x72);
1.1294 + emit_byte(0xC0 | encode);
1.1295 + emit_byte(shift & 0xFF);
1.1296 +}
1.1297 +
1.1298 +void Assembler::psllq(XMMRegister dst, int shift) {
1.1299 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1300 + // XMM6 is for /6 encoding: 66 0F 73 /6 ib
1.1301 + int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
1.1302 + emit_byte(0x73);
1.1303 + emit_byte(0xC0 | encode);
1.1304 + emit_byte(shift & 0xFF);
1.1305 +}
1.1306 +
1.1307 +void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
1.1308 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1309 + emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
1.1310 +}
1.1311 +
1.1312 +void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
1.1313 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1314 + emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
1.1315 +}
1.1316 +
1.1317 +void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
1.1318 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1319 + emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
1.1320 +}
1.1321 +
1.1322 +void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.1323 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1324 + // XMM6 is for /6 encoding: 66 0F 71 /6 ib
1.1325 + emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
1.1326 + emit_byte(shift & 0xFF);
1.1327 +}
1.1328 +
1.1329 +void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.1330 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1331 + // XMM6 is for /6 encoding: 66 0F 72 /6 ib
1.1332 + emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
1.1333 + emit_byte(shift & 0xFF);
1.1334 +}
1.1335 +
1.1336 +void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.1337 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1338 + // XMM6 is for /6 encoding: 66 0F 73 /6 ib
1.1339 + emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
1.1340 + emit_byte(shift & 0xFF);
1.1341 +}
1.1342 +
1.1343 +void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.1344 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1345 + emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
1.1346 +}
1.1347 +
1.1348 +void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.1349 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1350 + emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
1.1351 +}
1.1352 +
1.1353 +void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.1354 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1355 + emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
1.1356 +}
1.1357 +
1.1358 +// Shift packed integers logically right by specified number of bits.
1.1359 +void Assembler::psrlw(XMMRegister dst, int shift) {
1.1360 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1361 + // XMM2 is for /2 encoding: 66 0F 71 /2 ib
1.1362 + int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
1.1363 + emit_byte(0x71);
1.1364 + emit_byte(0xC0 | encode);
1.1365 + emit_byte(shift & 0xFF);
1.1366 +}
1.1367 +
1.1368 +void Assembler::psrld(XMMRegister dst, int shift) {
1.1369 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1370 + // XMM2 is for /2 encoding: 66 0F 72 /2 ib
1.1371 + int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
1.1372 + emit_byte(0x72);
1.1373 + emit_byte(0xC0 | encode);
1.1374 + emit_byte(shift & 0xFF);
1.1375 +}
1.1376 +
1.1377 +void Assembler::psrlq(XMMRegister dst, int shift) {
1.1378 + // Do not confuse it with psrldq SSE2 instruction which
1.1379 + // shifts 128 bit value in xmm register by number of bytes.
1.1380 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1381 + // XMM2 is for /2 encoding: 66 0F 73 /2 ib
1.1382 + int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
1.1383 + emit_byte(0x73);
1.1384 + emit_byte(0xC0 | encode);
1.1385 + emit_byte(shift & 0xFF);
1.1386 +}
1.1387 +
1.1388 +void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
1.1389 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1390 + emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
1.1391 +}
1.1392 +
1.1393 +void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
1.1394 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1395 + emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
1.1396 +}
1.1397 +
1.1398 +void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
1.1399 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1400 + emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
1.1401 +}
1.1402 +
1.1403 +void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.1404 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1405 + // XMM2 is for /2 encoding: 66 0F 73 /2 ib
1.1406 + emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
1.1407 + emit_byte(shift & 0xFF);
1.1408 +}
1.1409 +
1.1410 +void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.1411 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1412 + // XMM2 is for /2 encoding: 66 0F 73 /2 ib
1.1413 + emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
1.1414 + emit_byte(shift & 0xFF);
1.1415 +}
1.1416 +
1.1417 +void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.1418 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1419 + // XMM2 is for /2 encoding: 66 0F 73 /2 ib
1.1420 + emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
1.1421 + emit_byte(shift & 0xFF);
1.1422 +}
1.1423 +
1.1424 +void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.1425 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1426 + emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
1.1427 +}
1.1428 +
1.1429 +void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.1430 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1431 + emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
1.1432 +}
1.1433 +
1.1434 +void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.1435 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1436 + emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
1.1437 +}
1.1438 +
1.1439 +// Shift packed integers arithmetically right by specified number of bits.
1.1440 +void Assembler::psraw(XMMRegister dst, int shift) {
1.1441 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1442 + // XMM4 is for /4 encoding: 66 0F 71 /4 ib
1.1443 + int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
1.1444 + emit_byte(0x71);
1.1445 + emit_byte(0xC0 | encode);
1.1446 + emit_byte(shift & 0xFF);
1.1447 +}
1.1448 +
1.1449 +void Assembler::psrad(XMMRegister dst, int shift) {
1.1450 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1451 + // XMM4 is for /4 encoding: 66 0F 72 /4 ib
1.1452 + int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
1.1453 + emit_byte(0x72);
1.1454 + emit_byte(0xC0 | encode);
1.1455 + emit_byte(shift & 0xFF);
1.1456 +}
1.1457 +
1.1458 +void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
1.1459 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1460 + emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
1.1461 +}
1.1462 +
1.1463 +void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
1.1464 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1465 + emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
1.1466 +}
1.1467 +
1.1468 +void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.1469 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1470 + // XMM4 is for /4 encoding: 66 0F 71 /4 ib
1.1471 + emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
1.1472 + emit_byte(shift & 0xFF);
1.1473 +}
1.1474 +
1.1475 +void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
1.1476 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1477 + // XMM4 is for /4 encoding: 66 0F 71 /4 ib
1.1478 + emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
1.1479 + emit_byte(shift & 0xFF);
1.1480 +}
1.1481 +
1.1482 +void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.1483 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1484 + emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
1.1485 +}
1.1486 +
1.1487 +void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
1.1488 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1489 + emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
1.1490 +}
1.1491 +
1.1492 +
1.1493 +// AND packed integers
1.1494 +void Assembler::pand(XMMRegister dst, XMMRegister src) {
1.1495 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1496 + emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
1.1497 +}
1.1498 +
1.1499 +void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1500 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1501 + emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
1.1502 +}
1.1503 +
1.1504 +void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1505 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1506 + emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
1.1507 +}
1.1508 +
1.1509 +void Assembler::por(XMMRegister dst, XMMRegister src) {
1.1510 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1511 + emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
1.1512 +}
1.1513 +
1.1514 +void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1515 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1516 + emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
1.1517 +}
1.1518 +
1.1519 +void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1520 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1521 + emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
1.1522 +}
1.1523 +
1.1524 +void Assembler::pxor(XMMRegister dst, XMMRegister src) {
1.1525 + NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1.1526 + emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
1.1527 +}
1.1528 +
1.1529 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1.1530 - assert(VM_Version::supports_avx2() || (!vector256) && VM_Version::supports_avx(), "");
1.1531 - int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256);
1.1532 - emit_byte(0xEF);
1.1533 - emit_byte(0xC0 | encode);
1.1534 -}
1.1535 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1536 + emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
1.1537 +}
1.1538 +
1.1539 +void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1.1540 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
1.1541 + emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
1.1542 +}
1.1543 +
1.1544
1.1545 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1.1546 assert(VM_Version::supports_avx(), "");
1.1547 @@ -3805,6 +4099,49 @@
1.1548 }
1.1549 }
1.1550
1.1551 +void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
1.1552 + InstructionMark im(this);
1.1553 + simd_prefix(dst, dst, src, pre);
1.1554 + emit_byte(opcode);
1.1555 + emit_operand(dst, src);
1.1556 +}
1.1557 +
1.1558 +void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
1.1559 + int encode = simd_prefix_and_encode(dst, dst, src, pre);
1.1560 + emit_byte(opcode);
1.1561 + emit_byte(0xC0 | encode);
1.1562 +}
1.1563 +
1.1564 +// Versions with no second source register (non-destructive source).
1.1565 +void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
1.1566 + InstructionMark im(this);
1.1567 + simd_prefix(dst, xnoreg, src, pre);
1.1568 + emit_byte(opcode);
1.1569 + emit_operand(dst, src);
1.1570 +}
1.1571 +
1.1572 +void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
1.1573 + int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
1.1574 + emit_byte(opcode);
1.1575 + emit_byte(0xC0 | encode);
1.1576 +}
1.1577 +
1.1578 +// 3-operands AVX instructions
1.1579 +void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
1.1580 + Address src, VexSimdPrefix pre, bool vector256) {
1.1581 + InstructionMark im(this);
1.1582 + vex_prefix(dst, nds, src, pre, vector256);
1.1583 + emit_byte(opcode);
1.1584 + emit_operand(dst, src);
1.1585 +}
1.1586 +
1.1587 +void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
1.1588 + XMMRegister src, VexSimdPrefix pre, bool vector256) {
1.1589 + int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
1.1590 + emit_byte(opcode);
1.1591 + emit_byte(0xC0 | encode);
1.1592 +}
1.1593 +
1.1594 #ifndef _LP64
1.1595
1.1596 void Assembler::incl(Register dst) {
1.1597 @@ -7968,21 +8305,21 @@
1.1598 }
1.1599 }
1.1600
1.1601 -void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.1602 +void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
1.1603 if (reachable(src)) {
1.1604 - vandpd(dst, nds, as_Address(src));
1.1605 + vandpd(dst, nds, as_Address(src), vector256);
1.1606 } else {
1.1607 lea(rscratch1, src);
1.1608 - vandpd(dst, nds, Address(rscratch1, 0));
1.1609 - }
1.1610 -}
1.1611 -
1.1612 -void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.1613 + vandpd(dst, nds, Address(rscratch1, 0), vector256);
1.1614 + }
1.1615 +}
1.1616 +
1.1617 +void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
1.1618 if (reachable(src)) {
1.1619 - vandps(dst, nds, as_Address(src));
1.1620 + vandps(dst, nds, as_Address(src), vector256);
1.1621 } else {
1.1622 lea(rscratch1, src);
1.1623 - vandps(dst, nds, Address(rscratch1, 0));
1.1624 + vandps(dst, nds, Address(rscratch1, 0), vector256);
1.1625 }
1.1626 }
1.1627
1.1628 @@ -8040,21 +8377,21 @@
1.1629 }
1.1630 }
1.1631
1.1632 -void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.1633 +void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
1.1634 if (reachable(src)) {
1.1635 - vxorpd(dst, nds, as_Address(src));
1.1636 + vxorpd(dst, nds, as_Address(src), vector256);
1.1637 } else {
1.1638 lea(rscratch1, src);
1.1639 - vxorpd(dst, nds, Address(rscratch1, 0));
1.1640 - }
1.1641 -}
1.1642 -
1.1643 -void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
1.1644 + vxorpd(dst, nds, Address(rscratch1, 0), vector256);
1.1645 + }
1.1646 +}
1.1647 +
1.1648 +void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
1.1649 if (reachable(src)) {
1.1650 - vxorps(dst, nds, as_Address(src));
1.1651 + vxorps(dst, nds, as_Address(src), vector256);
1.1652 } else {
1.1653 lea(rscratch1, src);
1.1654 - vxorps(dst, nds, Address(rscratch1, 0));
1.1655 + vxorps(dst, nds, Address(rscratch1, 0), vector256);
1.1656 }
1.1657 }
1.1658
