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1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP |
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26 #define CPU_X86_VM_VM_VERSION_X86_HPP |
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27 |
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28 #include "runtime/globals_extension.hpp" |
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29 #include "runtime/vm_version.hpp" |
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30 |
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31 class VM_Version : public Abstract_VM_Version { |
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32 public: |
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33 // cpuid result register layouts. These are all unions of a uint32_t |
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34 // (in case anyone wants access to the register as a whole) and a bitfield. |
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35 |
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36 union StdCpuid1Eax { |
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37 uint32_t value; |
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38 struct { |
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39 uint32_t stepping : 4, |
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40 model : 4, |
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41 family : 4, |
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42 proc_type : 2, |
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43 : 2, |
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44 ext_model : 4, |
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45 ext_family : 8, |
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46 : 4; |
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47 } bits; |
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48 }; |
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49 |
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50 union StdCpuid1Ebx { // example, unused |
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51 uint32_t value; |
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52 struct { |
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53 uint32_t brand_id : 8, |
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54 clflush_size : 8, |
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55 threads_per_cpu : 8, |
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56 apic_id : 8; |
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57 } bits; |
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58 }; |
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59 |
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60 union StdCpuid1Ecx { |
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61 uint32_t value; |
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62 struct { |
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63 uint32_t sse3 : 1, |
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64 clmul : 1, |
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65 : 1, |
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66 monitor : 1, |
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67 : 1, |
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68 vmx : 1, |
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69 : 1, |
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70 est : 1, |
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71 : 1, |
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72 ssse3 : 1, |
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73 cid : 1, |
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74 : 2, |
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75 cmpxchg16: 1, |
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76 : 4, |
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77 dca : 1, |
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78 sse4_1 : 1, |
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79 sse4_2 : 1, |
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80 : 2, |
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81 popcnt : 1, |
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82 : 1, |
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83 aes : 1, |
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84 : 1, |
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85 osxsave : 1, |
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86 avx : 1, |
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87 : 3; |
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88 } bits; |
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89 }; |
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90 |
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91 union StdCpuid1Edx { |
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92 uint32_t value; |
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93 struct { |
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94 uint32_t : 4, |
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95 tsc : 1, |
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96 : 3, |
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97 cmpxchg8 : 1, |
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98 : 6, |
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99 cmov : 1, |
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100 : 3, |
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101 clflush : 1, |
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102 : 3, |
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103 mmx : 1, |
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104 fxsr : 1, |
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105 sse : 1, |
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106 sse2 : 1, |
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107 : 1, |
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108 ht : 1, |
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109 : 3; |
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110 } bits; |
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111 }; |
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112 |
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113 union DcpCpuid4Eax { |
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114 uint32_t value; |
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115 struct { |
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116 uint32_t cache_type : 5, |
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117 : 21, |
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118 cores_per_cpu : 6; |
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119 } bits; |
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120 }; |
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121 |
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122 union DcpCpuid4Ebx { |
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123 uint32_t value; |
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124 struct { |
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125 uint32_t L1_line_size : 12, |
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126 partitions : 10, |
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127 associativity : 10; |
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128 } bits; |
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129 }; |
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130 |
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131 union TplCpuidBEbx { |
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132 uint32_t value; |
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133 struct { |
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134 uint32_t logical_cpus : 16, |
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135 : 16; |
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136 } bits; |
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137 }; |
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138 |
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139 union ExtCpuid1Ecx { |
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140 uint32_t value; |
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141 struct { |
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142 uint32_t LahfSahf : 1, |
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143 CmpLegacy : 1, |
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144 : 3, |
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145 lzcnt_intel : 1, |
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146 lzcnt : 1, |
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147 sse4a : 1, |
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148 misalignsse : 1, |
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149 prefetchw : 1, |
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150 : 22; |
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151 } bits; |
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152 }; |
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153 |
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154 union ExtCpuid1Edx { |
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155 uint32_t value; |
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156 struct { |
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157 uint32_t : 22, |
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158 mmx_amd : 1, |
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159 mmx : 1, |
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160 fxsr : 1, |
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161 : 4, |
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162 long_mode : 1, |
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163 tdnow2 : 1, |
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164 tdnow : 1; |
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165 } bits; |
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166 }; |
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167 |
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168 union ExtCpuid5Ex { |
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169 uint32_t value; |
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170 struct { |
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171 uint32_t L1_line_size : 8, |
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172 L1_tag_lines : 8, |
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173 L1_assoc : 8, |
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174 L1_size : 8; |
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175 } bits; |
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176 }; |
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177 |
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178 union ExtCpuid7Edx { |
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179 uint32_t value; |
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180 struct { |
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181 uint32_t : 8, |
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182 tsc_invariance : 1, |
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183 : 23; |
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184 } bits; |
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185 }; |
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186 |
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187 union ExtCpuid8Ecx { |
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188 uint32_t value; |
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189 struct { |
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190 uint32_t cores_per_cpu : 8, |
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191 : 24; |
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192 } bits; |
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193 }; |
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194 |
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195 union SefCpuid7Eax { |
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196 uint32_t value; |
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197 }; |
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198 |
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199 union SefCpuid7Ebx { |
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200 uint32_t value; |
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201 struct { |
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202 uint32_t fsgsbase : 1, |
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203 : 2, |
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204 bmi1 : 1, |
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205 : 1, |
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206 avx2 : 1, |
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207 : 2, |
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208 bmi2 : 1, |
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209 erms : 1, |
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210 : 1, |
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211 rtm : 1, |
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212 : 20; |
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213 } bits; |
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214 }; |
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215 |
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216 union XemXcr0Eax { |
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217 uint32_t value; |
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218 struct { |
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219 uint32_t x87 : 1, |
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220 sse : 1, |
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221 ymm : 1, |
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222 : 29; |
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223 } bits; |
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224 }; |
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225 |
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226 protected: |
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227 static int _cpu; |
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228 static int _model; |
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229 static int _stepping; |
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230 static int _cpuFeatures; // features returned by the "cpuid" instruction |
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231 // 0 if this instruction is not available |
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232 static const char* _features_str; |
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233 |
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234 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV |
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235 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV |
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236 |
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237 enum { |
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238 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) |
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239 CPU_CMOV = (1 << 1), |
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240 CPU_FXSR = (1 << 2), |
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241 CPU_HT = (1 << 3), |
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242 CPU_MMX = (1 << 4), |
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243 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions |
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244 // may not necessarily support other 3dnow instructions |
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245 CPU_SSE = (1 << 6), |
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246 CPU_SSE2 = (1 << 7), |
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247 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) |
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248 CPU_SSSE3 = (1 << 9), |
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249 CPU_SSE4A = (1 << 10), |
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250 CPU_SSE4_1 = (1 << 11), |
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251 CPU_SSE4_2 = (1 << 12), |
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252 CPU_POPCNT = (1 << 13), |
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253 CPU_LZCNT = (1 << 14), |
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254 CPU_TSC = (1 << 15), |
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255 CPU_TSCINV = (1 << 16), |
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256 CPU_AVX = (1 << 17), |
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257 CPU_AVX2 = (1 << 18), |
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258 CPU_AES = (1 << 19), |
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259 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions |
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260 CPU_CLMUL = (1 << 21), // carryless multiply for CRC |
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261 CPU_BMI1 = (1 << 22), |
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262 CPU_BMI2 = (1 << 23), |
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263 CPU_RTM = (1 << 24) // Restricted Transactional Memory instructions |
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264 } cpuFeatureFlags; |
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265 |
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266 enum { |
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267 // AMD |
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268 CPU_FAMILY_AMD_11H = 0x11, |
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269 // Intel |
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270 CPU_FAMILY_INTEL_CORE = 6, |
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271 CPU_MODEL_NEHALEM = 0x1e, |
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272 CPU_MODEL_NEHALEM_EP = 0x1a, |
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273 CPU_MODEL_NEHALEM_EX = 0x2e, |
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274 CPU_MODEL_WESTMERE = 0x25, |
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275 CPU_MODEL_WESTMERE_EP = 0x2c, |
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276 CPU_MODEL_WESTMERE_EX = 0x2f, |
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277 CPU_MODEL_SANDYBRIDGE = 0x2a, |
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278 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, |
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279 CPU_MODEL_IVYBRIDGE_EP = 0x3a |
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280 } cpuExtendedFamily; |
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281 |
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282 // cpuid information block. All info derived from executing cpuid with |
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283 // various function numbers is stored here. Intel and AMD info is |
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284 // merged in this block: accessor methods disentangle it. |
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285 // |
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286 // The info block is laid out in subblocks of 4 dwords corresponding to |
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287 // eax, ebx, ecx and edx, whether or not they contain anything useful. |
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288 struct CpuidInfo { |
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289 // cpuid function 0 |
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290 uint32_t std_max_function; |
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291 uint32_t std_vendor_name_0; |
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292 uint32_t std_vendor_name_1; |
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293 uint32_t std_vendor_name_2; |
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294 |
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295 // cpuid function 1 |
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296 StdCpuid1Eax std_cpuid1_eax; |
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297 StdCpuid1Ebx std_cpuid1_ebx; |
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298 StdCpuid1Ecx std_cpuid1_ecx; |
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299 StdCpuid1Edx std_cpuid1_edx; |
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300 |
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301 // cpuid function 4 (deterministic cache parameters) |
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302 DcpCpuid4Eax dcp_cpuid4_eax; |
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303 DcpCpuid4Ebx dcp_cpuid4_ebx; |
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304 uint32_t dcp_cpuid4_ecx; // unused currently |
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305 uint32_t dcp_cpuid4_edx; // unused currently |
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306 |
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307 // cpuid function 7 (structured extended features) |
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308 SefCpuid7Eax sef_cpuid7_eax; |
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309 SefCpuid7Ebx sef_cpuid7_ebx; |
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310 uint32_t sef_cpuid7_ecx; // unused currently |
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311 uint32_t sef_cpuid7_edx; // unused currently |
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312 |
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313 // cpuid function 0xB (processor topology) |
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314 // ecx = 0 |
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315 uint32_t tpl_cpuidB0_eax; |
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316 TplCpuidBEbx tpl_cpuidB0_ebx; |
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317 uint32_t tpl_cpuidB0_ecx; // unused currently |
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318 uint32_t tpl_cpuidB0_edx; // unused currently |
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319 |
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320 // ecx = 1 |
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321 uint32_t tpl_cpuidB1_eax; |
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322 TplCpuidBEbx tpl_cpuidB1_ebx; |
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323 uint32_t tpl_cpuidB1_ecx; // unused currently |
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324 uint32_t tpl_cpuidB1_edx; // unused currently |
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325 |
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326 // ecx = 2 |
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327 uint32_t tpl_cpuidB2_eax; |
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328 TplCpuidBEbx tpl_cpuidB2_ebx; |
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329 uint32_t tpl_cpuidB2_ecx; // unused currently |
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330 uint32_t tpl_cpuidB2_edx; // unused currently |
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331 |
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332 // cpuid function 0x80000000 // example, unused |
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333 uint32_t ext_max_function; |
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334 uint32_t ext_vendor_name_0; |
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335 uint32_t ext_vendor_name_1; |
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336 uint32_t ext_vendor_name_2; |
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337 |
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338 // cpuid function 0x80000001 |
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339 uint32_t ext_cpuid1_eax; // reserved |
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340 uint32_t ext_cpuid1_ebx; // reserved |
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341 ExtCpuid1Ecx ext_cpuid1_ecx; |
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342 ExtCpuid1Edx ext_cpuid1_edx; |
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343 |
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344 // cpuid functions 0x80000002 thru 0x80000004: example, unused |
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345 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; |
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346 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; |
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347 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; |
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348 |
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349 // cpuid function 0x80000005 // AMD L1, Intel reserved |
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350 uint32_t ext_cpuid5_eax; // unused currently |
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351 uint32_t ext_cpuid5_ebx; // reserved |
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352 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) |
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353 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) |
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354 |
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355 // cpuid function 0x80000007 |
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356 uint32_t ext_cpuid7_eax; // reserved |
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357 uint32_t ext_cpuid7_ebx; // reserved |
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358 uint32_t ext_cpuid7_ecx; // reserved |
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359 ExtCpuid7Edx ext_cpuid7_edx; // tscinv |
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360 |
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361 // cpuid function 0x80000008 |
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362 uint32_t ext_cpuid8_eax; // unused currently |
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363 uint32_t ext_cpuid8_ebx; // reserved |
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364 ExtCpuid8Ecx ext_cpuid8_ecx; |
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365 uint32_t ext_cpuid8_edx; // reserved |
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366 |
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367 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) |
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368 XemXcr0Eax xem_xcr0_eax; |
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369 uint32_t xem_xcr0_edx; // reserved |
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370 |
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371 // Space to save ymm registers after signal handle |
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372 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 |
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373 }; |
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374 |
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375 // The actual cpuid info block |
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376 static CpuidInfo _cpuid_info; |
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377 |
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378 // Extractors and predicates |
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379 static uint32_t extended_cpu_family() { |
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380 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; |
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381 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; |
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382 return result; |
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383 } |
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384 |
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385 static uint32_t extended_cpu_model() { |
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386 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; |
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387 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; |
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388 return result; |
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389 } |
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390 |
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391 static uint32_t cpu_stepping() { |
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392 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; |
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393 return result; |
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394 } |
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395 |
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396 static uint logical_processor_count() { |
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397 uint result = threads_per_core(); |
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398 return result; |
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399 } |
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400 |
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401 static uint32_t feature_flags() { |
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402 uint32_t result = 0; |
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403 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) |
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404 result |= CPU_CX8; |
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405 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) |
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406 result |= CPU_CMOV; |
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407 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && |
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408 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) |
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409 result |= CPU_FXSR; |
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410 // HT flag is set for multi-core processors also. |
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411 if (threads_per_core() > 1) |
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412 result |= CPU_HT; |
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413 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && |
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414 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) |
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415 result |= CPU_MMX; |
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416 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) |
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417 result |= CPU_SSE; |
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418 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) |
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419 result |= CPU_SSE2; |
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420 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) |
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421 result |= CPU_SSE3; |
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422 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) |
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423 result |= CPU_SSSE3; |
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424 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) |
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425 result |= CPU_SSE4_1; |
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426 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) |
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427 result |= CPU_SSE4_2; |
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428 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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429 result |= CPU_POPCNT; |
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430 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && |
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431 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && |
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432 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && |
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433 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { |
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434 result |= CPU_AVX; |
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435 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) |
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436 result |= CPU_AVX2; |
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437 } |
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438 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) |
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439 result |= CPU_BMI1; |
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440 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) |
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441 result |= CPU_TSC; |
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442 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) |
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443 result |= CPU_TSCINV; |
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444 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) |
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445 result |= CPU_AES; |
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446 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) |
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447 result |= CPU_ERMS; |
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448 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) |
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449 result |= CPU_CLMUL; |
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450 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) |
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451 result |= CPU_RTM; |
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452 |
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453 // AMD features. |
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454 if (is_amd()) { |
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455 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || |
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456 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) |
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457 result |= CPU_3DNOW_PREFETCH; |
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458 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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459 result |= CPU_LZCNT; |
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460 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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461 result |= CPU_SSE4A; |
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462 } |
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463 // Intel features. |
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464 if(is_intel()) { |
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465 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) |
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466 result |= CPU_BMI2; |
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467 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) |
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468 result |= CPU_LZCNT; |
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469 } |
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470 |
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471 return result; |
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472 } |
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473 |
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474 static bool os_supports_avx_vectors() { |
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475 if (!supports_avx()) { |
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476 return false; |
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477 } |
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478 // Verify that OS save/restore all bits of AVX registers |
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479 // during signal processing. |
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480 int nreg = 2 LP64_ONLY(+2); |
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481 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register |
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482 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { |
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483 return false; |
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484 } |
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485 } |
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486 return true; |
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487 } |
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488 |
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489 static void get_processor_features(); |
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490 |
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491 public: |
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492 // Offsets for cpuid asm stub |
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493 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } |
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494 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } |
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495 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } |
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496 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } |
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497 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
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498 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } |
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499 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } |
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500 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
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501 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
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502 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } |
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503 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } |
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504 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } |
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505 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } |
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506 |
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507 // The value used to check ymm register after signal handle |
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508 static int ymm_test_value() { return 0xCAFEBABE; } |
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509 |
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510 static void get_cpu_info_wrapper(); |
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511 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } |
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512 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } |
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513 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } |
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514 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } |
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515 |
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516 static void clean_cpuFeatures() { _cpuFeatures = 0; } |
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517 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); } |
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518 |
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519 |
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520 // Initialization |
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521 static void initialize(); |
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522 |
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523 // Override Abstract_VM_Version implementation |
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524 static bool use_biased_locking(); |
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525 |
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526 // Asserts |
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527 static void assert_is_initialized() { |
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528 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); |
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529 } |
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530 |
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531 // |
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532 // Processor family: |
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533 // 3 - 386 |
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534 // 4 - 486 |
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535 // 5 - Pentium |
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536 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, |
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537 // Pentium M, Core Solo, Core Duo, Core2 Duo |
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538 // family 6 model: 9, 13, 14, 15 |
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539 // 0x0f - Pentium 4, Opteron |
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540 // |
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541 // Note: The cpu family should be used to select between |
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542 // instruction sequences which are valid on all Intel |
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543 // processors. Use the feature test functions below to |
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544 // determine whether a particular instruction is supported. |
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545 // |
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546 static int cpu_family() { return _cpu;} |
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547 static bool is_P6() { return cpu_family() >= 6; } |
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548 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' |
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549 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' |
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550 |
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551 static bool supports_processor_topology() { |
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552 return (_cpuid_info.std_max_function >= 0xB) && |
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553 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. |
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554 // Some cpus have max cpuid >= 0xB but do not support processor topology. |
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555 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); |
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556 } |
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557 |
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558 static uint cores_per_cpu() { |
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559 uint result = 1; |
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560 if (is_intel()) { |
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561 if (supports_processor_topology()) { |
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562 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
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563 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
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564 } else { |
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565 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); |
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566 } |
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567 } else if (is_amd()) { |
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568 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); |
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569 } |
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570 return result; |
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571 } |
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572 |
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573 static uint threads_per_core() { |
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574 uint result = 1; |
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575 if (is_intel() && supports_processor_topology()) { |
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576 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
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577 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { |
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578 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
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579 cores_per_cpu(); |
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580 } |
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581 return result; |
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582 } |
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583 |
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584 static intx prefetch_data_size() { |
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585 intx result = 0; |
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586 if (is_intel()) { |
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587 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); |
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588 } else if (is_amd()) { |
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589 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; |
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590 } |
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591 if (result < 32) // not defined ? |
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592 result = 32; // 32 bytes by default on x86 and other x64 |
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593 return result; |
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594 } |
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595 |
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596 // |
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597 // Feature identification |
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598 // |
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599 static bool supports_cpuid() { return _cpuFeatures != 0; } |
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600 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } |
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601 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } |
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602 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } |
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603 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } |
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604 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } |
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605 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } |
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606 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } |
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607 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } |
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608 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } |
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609 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } |
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610 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } |
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611 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
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612 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } |
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613 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } |
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614 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } |
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615 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } |
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616 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } |
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617 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } |
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618 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; } |
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619 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } |
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620 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } |
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621 // Intel features |
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622 static bool is_intel_family_core() { return is_intel() && |
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623 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } |
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624 |
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625 static bool is_intel_tsc_synched_at_init() { |
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626 if (is_intel_family_core()) { |
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627 uint32_t ext_model = extended_cpu_model(); |
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628 if (ext_model == CPU_MODEL_NEHALEM_EP || |
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629 ext_model == CPU_MODEL_WESTMERE_EP || |
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630 ext_model == CPU_MODEL_SANDYBRIDGE_EP || |
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631 ext_model == CPU_MODEL_IVYBRIDGE_EP) { |
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632 // <= 2-socket invariant tsc support. EX versions are usually used |
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633 // in > 2-socket systems and likely don't synchronize tscs at |
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634 // initialization. |
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635 // Code that uses tsc values must be prepared for them to arbitrarily |
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636 // jump forward or backward. |
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637 return true; |
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638 } |
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639 } |
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640 return false; |
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641 } |
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642 |
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643 // AMD features |
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644 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } |
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645 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
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646 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
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647 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
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648 |
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649 static bool is_amd_Barcelona() { return is_amd() && |
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650 extended_cpu_family() == CPU_FAMILY_AMD_11H; } |
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651 |
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652 // Intel and AMD newer cores support fast timestamps well |
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653 static bool supports_tscinv_bit() { |
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654 return (_cpuFeatures & CPU_TSCINV) != 0; |
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655 } |
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656 static bool supports_tscinv() { |
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657 return supports_tscinv_bit() && |
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658 ( (is_amd() && !is_amd_Barcelona()) || |
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659 is_intel_tsc_synched_at_init() ); |
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660 } |
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661 |
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662 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
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663 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
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664 supports_sse3() && _model != 0x1C; } |
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665 |
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666 static bool supports_compare_and_exchange() { return true; } |
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667 |
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668 static const char* cpu_features() { return _features_str; } |
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669 |
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670 static intx allocate_prefetch_distance() { |
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671 // This method should be called before allocate_prefetch_style(). |
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672 // |
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673 // Hardware prefetching (distance/size in bytes): |
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674 // Pentium 3 - 64 / 32 |
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675 // Pentium 4 - 256 / 128 |
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676 // Athlon - 64 / 32 ???? |
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677 // Opteron - 128 / 64 only when 2 sequential cache lines accessed |
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678 // Core - 128 / 64 |
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679 // |
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680 // Software prefetching (distance in bytes / instruction with best score): |
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681 // Pentium 3 - 128 / prefetchnta |
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682 // Pentium 4 - 512 / prefetchnta |
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683 // Athlon - 128 / prefetchnta |
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684 // Opteron - 256 / prefetchnta |
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685 // Core - 256 / prefetchnta |
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686 // It will be used only when AllocatePrefetchStyle > 0 |
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687 |
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688 intx count = AllocatePrefetchDistance; |
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689 if (count < 0) { // default ? |
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690 if (is_amd()) { // AMD |
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691 if (supports_sse2()) |
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692 count = 256; // Opteron |
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693 else |
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694 count = 128; // Athlon |
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695 } else { // Intel |
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696 if (supports_sse2()) |
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697 if (cpu_family() == 6) { |
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698 count = 256; // Pentium M, Core, Core2 |
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699 } else { |
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700 count = 512; // Pentium 4 |
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701 } |
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702 else |
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703 count = 128; // Pentium 3 (and all other old CPUs) |
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704 } |
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705 } |
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706 return count; |
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707 } |
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708 static intx allocate_prefetch_style() { |
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709 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); |
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710 // Return 0 if AllocatePrefetchDistance was not defined. |
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711 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; |
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712 } |
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713 |
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714 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from |
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715 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. |
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716 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. |
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717 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. |
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718 |
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719 // gc copy/scan is disabled if prefetchw isn't supported, because |
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720 // Prefetch::write emits an inlined prefetchw on Linux. |
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721 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. |
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722 // The used prefetcht0 instruction works for both amd64 and em64t. |
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723 static intx prefetch_copy_interval_in_bytes() { |
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724 intx interval = PrefetchCopyIntervalInBytes; |
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725 return interval >= 0 ? interval : 576; |
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726 } |
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727 static intx prefetch_scan_interval_in_bytes() { |
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728 intx interval = PrefetchScanIntervalInBytes; |
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729 return interval >= 0 ? interval : 576; |
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730 } |
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731 static intx prefetch_fields_ahead() { |
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732 intx count = PrefetchFieldsAhead; |
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733 return count >= 0 ? count : 1; |
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734 } |
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735 }; |
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736 |
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737 #endif // CPU_X86_VM_VM_VERSION_X86_HPP |