34 }; |
34 }; |
35 |
35 |
36 |
36 |
37 // registers |
37 // registers |
38 enum { |
38 enum { |
39 pd_nof_cpu_regs_frame_map = 8, // number of registers used during code emission |
39 pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission |
40 pd_nof_fpu_regs_frame_map = 8, // number of registers used during code emission |
40 pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission |
41 pd_nof_xmm_regs_frame_map = 8, // number of registers used during code emission |
41 pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission |
42 pd_nof_caller_save_cpu_regs_frame_map = 6, // number of registers killed by calls |
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43 pd_nof_caller_save_fpu_regs_frame_map = 8, // number of registers killed by calls |
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44 pd_nof_caller_save_xmm_regs_frame_map = 8, // number of registers killed by calls |
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45 |
42 |
46 pd_nof_cpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator |
43 #ifdef _LP64 |
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44 #define UNALLOCATED 4 // rsp, rbp, r15, r10 |
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45 #else |
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46 #define UNALLOCATED 2 // rsp, rbp |
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47 #endif // LP64 |
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48 |
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49 pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls |
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50 pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls |
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51 pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls |
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52 |
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53 pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator |
47 pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator |
54 pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator |
48 |
55 |
49 pd_nof_cpu_regs_linearscan = 8, // number of registers visible to linear scan |
56 pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan |
50 pd_nof_fpu_regs_linearscan = 8, // number of registers visible to linear scan |
57 pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan |
51 pd_nof_xmm_regs_linearscan = 8, // number of registers visible to linear scan |
58 pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan |
52 pd_first_cpu_reg = 0, |
59 pd_first_cpu_reg = 0, |
53 pd_last_cpu_reg = 5, |
60 pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11), |
54 pd_first_byte_reg = 2, |
61 pd_first_byte_reg = 2, |
55 pd_last_byte_reg = 5, |
62 pd_last_byte_reg = 5, |
56 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, |
63 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, |
57 pd_last_fpu_reg = pd_first_fpu_reg + 7, |
64 pd_last_fpu_reg = pd_first_fpu_reg + 7, |
58 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map, |
65 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map, |
59 pd_last_xmm_reg = pd_first_xmm_reg + 7 |
66 pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1 |
60 }; |
67 }; |
61 |
68 |
62 |
69 |
63 // encoding of float value in debug info: |
70 // encoding of float value in debug info: |
64 enum { |
71 enum { |