499 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); |
499 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); |
500 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); |
500 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); |
501 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); |
501 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); |
502 #else |
502 #else |
503 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); |
503 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); |
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504 #ifdef ARM |
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505 // ARM has support for moving 64bit values between a pair of |
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506 // integer registers and a double register |
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507 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); |
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508 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); |
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509 #endif |
504 #endif |
510 #endif |
505 } |
511 } |
506 |
512 |
507 // Make up debug masks. Any spill slot plus callee-save registers. |
513 // Make up debug masks. Any spill slot plus callee-save registers. |
508 // Caller-save registers are assumed to be trashable by the various |
514 // Caller-save registers are assumed to be trashable by the various |