Mercurial > jdk8-mips64-public > hotspot / file comparison
comparison: src/share/vm/c1/c1_LIRAssembler.cpp
src/share/vm/c1/c1_LIRAssembler.cpp
- changeset 6876
- 710a3c8b516e
- parent 6723
- 0bf37f737702
- parent 1
- 2d8a650513c2
- child 8604
- 04d83ba48607
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| 6875:28b50d07f6f8 | 6876:710a3c8b516e |
|---|---|
| 20 * or visit www.oracle.com if you need additional information or have any | 20 * or visit www.oracle.com if you need additional information or have any |
| 21 * questions. | 21 * questions. |
| 22 * | 22 * |
| 23 */ | 23 */ |
| 24 | 24 |
| 25 /* | |
| 26 * This file has been modified by Loongson Technology in 2015. These | |
| 27 * modifications are Copyright (c) 2015 Loongson Technology, and are made | |
| 28 * available on the same license terms set forth above. | |
| 29 */ | |
| 30 | |
| 25 #include "precompiled.hpp" | 31 #include "precompiled.hpp" |
| 26 #include "c1/c1_Compilation.hpp" | 32 #include "c1/c1_Compilation.hpp" |
| 27 #include "c1/c1_Instruction.hpp" | 33 #include "c1/c1_Instruction.hpp" |
| 28 #include "c1/c1_InstructionPrinter.hpp" | 34 #include "c1/c1_InstructionPrinter.hpp" |
| 29 #include "c1/c1_LIRAssembler.hpp" | 35 #include "c1/c1_LIRAssembler.hpp" |
| 31 #include "c1/c1_ValueStack.hpp" | 37 #include "c1/c1_ValueStack.hpp" |
| 32 #include "ci/ciInstance.hpp" | 38 #include "ci/ciInstance.hpp" |
| 33 #ifdef TARGET_ARCH_x86 | 39 #ifdef TARGET_ARCH_x86 |
| 34 # include "nativeInst_x86.hpp" | 40 # include "nativeInst_x86.hpp" |
| 35 # include "vmreg_x86.inline.hpp" | 41 # include "vmreg_x86.inline.hpp" |
| 42 #endif | |
| 43 #ifdef TARGET_ARCH_mips | |
| 44 # include "nativeInst_mips.hpp" | |
| 45 # include "vmreg_mips.inline.hpp" | |
| 36 #endif | 46 #endif |
| 37 #ifdef TARGET_ARCH_sparc | 47 #ifdef TARGET_ARCH_sparc |
| 38 # include "nativeInst_sparc.hpp" | 48 # include "nativeInst_sparc.hpp" |
| 39 # include "vmreg_sparc.inline.hpp" | 49 # include "vmreg_sparc.inline.hpp" |
| 40 #endif | 50 #endif |
| 712 } | 722 } |
| 713 | 723 |
| 714 | 724 |
| 715 void LIR_Assembler::emit_op2(LIR_Op2* op) { | 725 void LIR_Assembler::emit_op2(LIR_Op2* op) { |
| 716 switch (op->code()) { | 726 switch (op->code()) { |
| 727 #ifndef MIPS64 | |
| 717 case lir_cmp: | 728 case lir_cmp: |
| 718 if (op->info() != NULL) { | 729 if (op->info() != NULL) { |
| 719 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(), | 730 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(), |
| 720 "shouldn't be codeemitinfo for non-address operands"); | 731 "shouldn't be codeemitinfo for non-address operands"); |
| 721 add_debug_info_for_null_check_here(op->info()); // exception possible | 732 add_debug_info_for_null_check_here(op->info()); // exception possible |
| 722 } | 733 } |
| 723 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); | 734 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); |
| 724 break; | 735 break; |
| 736 #else | |
| 737 case lir_null_check_for_branch: | |
| 738 if (op->info() != NULL) { | |
| 739 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(), | |
| 740 "shouldn't be codeemitinfo for non-address operands"); | |
| 741 add_debug_info_for_null_check_here(op->info()); // exception possible | |
| 742 } | |
| 743 break; | |
| 744 #endif | |
| 725 | 745 |
| 726 case lir_cmp_l2i: | 746 case lir_cmp_l2i: |
| 727 case lir_cmp_fd2i: | 747 case lir_cmp_fd2i: |
| 728 case lir_ucmp_fd2i: | 748 case lir_ucmp_fd2i: |
| 729 comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op); | 749 comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op); |
| 730 break; | 750 break; |
| 731 | 751 |
| 732 case lir_cmove: | 752 case lir_cmove: |
| 753 #ifndef MIPS64 | |
| 733 cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type()); | 754 cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type()); |
| 755 #endif | |
| 734 break; | 756 break; |
| 735 | 757 |
| 736 case lir_shl: | 758 case lir_shl: |
| 737 case lir_shr: | 759 case lir_shr: |
| 738 case lir_ushr: | 760 case lir_ushr: |
