319 } |
319 } |
320 // in 64 bit the use of SSE2 is the minimum |
320 // in 64 bit the use of SSE2 is the minimum |
321 if (UseSSE < 2) UseSSE = 2; |
321 if (UseSSE < 2) UseSSE = 2; |
322 #endif |
322 #endif |
323 |
323 |
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324 #ifdef AMD64 |
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325 // flush_icache_stub have to be generated first. |
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326 // That is why Icache line size is hard coded in ICache class, |
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327 // see icache_x86.hpp. It is also the reason why we can't use |
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328 // clflush instruction in 32-bit VM since it could be running |
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329 // on CPU which does not support it. |
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330 // |
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331 // The only thing we can do is to verify that flushed |
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332 // ICache::line_size has correct value. |
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333 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
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334 // clflush_size is size in quadwords (8 bytes). |
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335 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
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336 #endif |
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337 |
324 // If the OS doesn't support SSE, we can't use this feature even if the HW does |
338 // If the OS doesn't support SSE, we can't use this feature even if the HW does |
325 if (!os::supports_sse()) |
339 if (!os::supports_sse()) |
326 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
340 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
327 |
341 |
328 if (UseSSE < 4) { |
342 if (UseSSE < 4) { |