src/cpu/ppc/vm/ppc.ad

changeset 8906
584eac5794ff
parent 8905
7c3dc80542b6
child 9041
95a08233f46c
child 9333
2fccf735a116
equal deleted inserted replaced
8905:7c3dc80542b6 8906:584eac5794ff
1 // 1 //
2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved. 2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2014 SAP AG. All rights reserved. 3 // Copyright (c) 2012, 2017 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 // 5 //
6 // This code is free software; you can redistribute it and/or modify it 6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as 7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation. 8 // published by the Free Software Foundation.
8604 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} 8604 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8605 size(4); 8605 size(4);
8606 ins_encode %{ 8606 ins_encode %{
8607 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8607 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8608 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8608 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8609 %}
8610 ins_pipe(pipe_class_default);
8611 %}
8612
8613 // Bitfield Extract: URShiftI + AndI
8614 instruct andI_urShiftI_regI_immI_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immI src2, immIpow2minus1 src3) %{
8615 match(Set dst (AndI (URShiftI src1 src2) src3));
8616
8617 format %{ "EXTRDI $dst, $src1, shift=$src2, mask=$src3 \t// int bitfield extract" %}
8618 size(4);
8619 ins_encode %{
8620 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8621 int rshift = ($src2$$constant) & 0x1f;
8622 int length = log2_long(((jlong) $src3$$constant) + 1);
8623 if (rshift + length > 32) {
8624 // if necessary, adjust mask to omit rotated bits.
8625 length = 32 - rshift;
8626 }
8627 __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
8628 %}
8629 ins_pipe(pipe_class_default);
8630 %}
8631
8632 // Bitfield Extract: URShiftL + AndL
8633 instruct andL_urShiftL_regL_immI_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immI src2, immLpow2minus1 src3) %{
8634 match(Set dst (AndL (URShiftL src1 src2) src3));
8635
8636 format %{ "EXTRDI $dst, $src1, shift=$src2, mask=$src3 \t// long bitfield extract" %}
8637 size(4);
8638 ins_encode %{
8639 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8640 int rshift = ($src2$$constant) & 0x3f;
8641 int length = log2_long(((jlong) $src3$$constant) + 1);
8642 if (rshift + length > 64) {
8643 // if necessary, adjust mask to omit rotated bits.
8644 length = 64 - rshift;
8645 }
8646 __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
8609 %} 8647 %}
8610 ins_pipe(pipe_class_default); 8648 ins_pipe(pipe_class_default);
8611 %} 8649 %}
8612 8650
8613 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ 8651 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{

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