jdk8-mips64-public/hotspot: comparison src/cpu/sparc/vm/sparc.ad

-:6a991dcb52bb
+:3d42f82cd811
 }
 #endif
 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 MacroAssembler _masm(&cbuf);
-Label L;
 Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
 Register temp_reg   = G3;
 assert( G5_ic_reg != temp_reg, "conflicting registers" );
 // Load klass from receiver
 MacroAssembler _masm(&cbuf);
 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
 __ delayed()->nop();
 %}
-enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
+enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
 MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
+Label* L = $labl$$label;
 Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
-__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
+__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
 __ delayed()->nop();
 %}
-enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
+enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
 MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
+Label* L = $labl$$label;
 Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
-__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
+__ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
-__ delayed()->nop();
-%}
-enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
-MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
-Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
-__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
-__ delayed()->nop();
-%}
-enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
-MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
-Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
-__ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
-__ delayed()->nop();
-%}
-enc_class enc_ba( Label labl ) %{
-MacroAssembler _masm(&cbuf);
-Label &L = *($labl$$label);
-__ ba(false, L);
-__ delayed()->nop();
-%}
-enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
-MacroAssembler _masm(&cbuf);
-Label &L = *$labl$$label;
-Assembler::Predict predict_taken =
-cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
-__ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
 __ delayed()->nop();
 %}
 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
 int op = (Assembler::arith_op << 30) |
 __ cmp(str1_reg, str2_reg); //same char[] ?
 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
 __ delayed()->add(G0, 1, result_reg);
-__ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
+__ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
 __ delayed()->add(G0, 1, result_reg); // count == 0
 //rename registers
 Register limit_reg =    cnt_reg;
 Register  chr1_reg = result_reg;
 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
 // Compare char[] arrays aligned to 4 bytes.
 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
 chr1_reg, chr2_reg, Ldone);
-__ ba(false,Ldone);
+__ ba(Ldone);
 __ delayed()->add(G0, 1, result_reg);
 // char by char compare
 __ bind(Lchar);
 __ add(str1_reg, limit_reg, str1_reg);
 // return false if the two arrays are not equal length
 __ cmp(tmp1_reg, tmp2_reg);
 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
 __ delayed()->mov(G0, result_reg);     // not equal
-__ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
+__ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
 // load array addresses
 __ add(ary1_reg, base_offset, ary1_reg);
 __ add(ary2_reg, base_offset, ary2_reg);
 effect(USE labl);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BA     $labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
+ins_encode %{
-opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
+Label* L = $labl$$label;
-ins_encode( enc_ba( labl ) );
+__ ba(*L);
+__ delayed()->nop();
+%}
 ins_pc_relative(1);
 ins_pipe(br);
 %}
 // Conditional Direct Branch
 effect(USE labl);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BP$cmp  $pcc,$labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30
+ins_encode %{
-ins_encode( enc_bpx( labl, cmp, pcc ) );
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
+__ delayed()->nop();
+%}
 ins_pc_relative(1);
 ins_pipe(br_cc);
 %}
 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
 effect(USE labl);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "FBP$cmp $fcc,$labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30
+ins_encode %{
-ins_encode( enc_fbp( labl, cmp, fcc ) );
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
+__ delayed()->nop();
+%}
 ins_pc_relative(1);
 ins_pipe(br_fcc);
 %}
 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
 effect(USE labl);
 size(8);
 ins_cost(BRANCH_COST);
 format %{ "BP$cmp   $xcc,$labl" %}
-// Prim = bits 24-22, Secnd = bits 31-30
+ins_encode %{
-ins_encode( enc_bpl( labl, cmp, xcc ) );
+Label* L = $labl$$label;
+Assembler::Predict predict_taken =
+cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
+__ delayed()->nop();
+%}
 ins_pc_relative(1);
 ins_pipe(br_cc);
 %}
 // Manifest a CmpL3 result in an integer register.  Very painful.
 match(Set pcc (FastLock object box));
 effect(KILL scratch, TEMP scratch2);
 ins_cost(100);
-size(4*112);       // conservative overestimation ...
 format %{ "FASTLOCK  $object, $box; KILL $scratch, $scratch2, $box" %}
 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
 ins_pipe(long_memory_op);
 %}
 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
 match(Set pcc (FastUnlock object box));
 effect(KILL scratch, TEMP scratch2);
 ins_cost(100);
-size(4*120);       // conservative overestimation ...
 format %{ "FASTUNLOCK  $object, $box; KILL $scratch, $scratch2, $box" %}
 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
 ins_pipe(long_memory_op);
 %}

Mercurial > jdk8-mips64-public > hotspot / file comparison

comparison: src/cpu/sparc/vm/sparc.ad

src/cpu/sparc/vm/sparc.ad