2405 |
2405 |
2406 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
2406 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
2407 return RegMask(); |
2407 return RegMask(); |
2408 } |
2408 } |
2409 |
2409 |
2410 const RegMask Matcher::mathExactI_result_proj_mask() { |
|
2411 return RARG4_BITS64_REG_mask(); |
|
2412 } |
|
2413 |
|
2414 const RegMask Matcher::mathExactL_result_proj_mask() { |
|
2415 return RARG4_BITS64_REG_mask(); |
|
2416 } |
|
2417 |
|
2418 const RegMask Matcher::mathExactI_flags_proj_mask() { |
|
2419 return INT_FLAGS_mask(); |
|
2420 } |
|
2421 |
|
2422 %} |
2410 %} |
2423 |
2411 |
2424 //----------ENCODING BLOCK----------------------------------------------------- |
2412 //----------ENCODING BLOCK----------------------------------------------------- |
2425 // This block specifies the encoding classes used by the compiler to output |
2413 // This block specifies the encoding classes used by the compiler to output |
2426 // byte streams. Encoding classes are parameterized macros used by |
2414 // byte streams. Encoding classes are parameterized macros used by |
7631 ins_pipe(pipe_class_default); |
7619 ins_pipe(pipe_class_default); |
7632 %} |
7620 %} |
7633 |
7621 |
7634 //----------Arithmetic Instructions-------------------------------------------- |
7622 //----------Arithmetic Instructions-------------------------------------------- |
7635 // Addition Instructions |
7623 // Addition Instructions |
7636 |
|
7637 // PPC has no instruction setting overflow of 32-bit integer. |
|
7638 //instruct addExactI_rReg(rarg4RegI dst, rRegI src, flagsReg cr) %{ |
|
7639 // match(AddExactI dst src); |
|
7640 // effect(DEF cr); |
|
7641 // |
|
7642 // format %{ "ADD $dst, $dst, $src \t// addExact int, sets $cr" %} |
|
7643 // ins_encode( enc_add(dst, dst, src) ); |
|
7644 // ins_pipe(pipe_class_default); |
|
7645 //%} |
|
7646 |
7624 |
7647 // Register Addition |
7625 // Register Addition |
7648 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ |
7626 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ |
7649 match(Set dst (AddI src1 src2)); |
7627 match(Set dst (AddI src1 src2)); |
7650 format %{ "ADD $dst, $src1, $src2" %} |
7628 format %{ "ADD $dst, $src1, $src2" %} |