src/cpu/sparc/vm/sparc.ad

changeset 6067
208ebea980f8
parent 6030
b4aa8fc5d0d5
child 6184
9ecf408d4568
child 6485
da862781b584
equal deleted inserted replaced
6058:5b84039ca739 6067:208ebea980f8
2914 2914
2915 // Strings might not be equal 2915 // Strings might not be equal
2916 __ bind(LSkip2); 2916 __ bind(LSkip2);
2917 } 2917 }
2918 2918
2919 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2920 __ signx(limit_reg);
2921
2919 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2922 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2920 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2923 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2921 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2924 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2922 2925
2923 // Shift str1_reg and str2_reg to the end of the arrays, negate limit 2926 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2970 2973
2971 //rename registers 2974 //rename registers
2972 Register limit_reg = cnt_reg; 2975 Register limit_reg = cnt_reg;
2973 Register chr1_reg = result_reg; 2976 Register chr1_reg = result_reg;
2974 Register chr2_reg = tmp1_reg; 2977 Register chr2_reg = tmp1_reg;
2978
2979 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2980 __ signx(limit_reg);
2975 2981
2976 //check for alignment and position the pointers to the ends 2982 //check for alignment and position the pointers to the ends
2977 __ or3(str1_reg, str2_reg, chr1_reg); 2983 __ or3(str1_reg, str2_reg, chr1_reg);
2978 __ andcc(chr1_reg, 0x3, chr1_reg); 2984 __ andcc(chr1_reg, 0x3, chr1_reg);
2979 // notZero means at least one not 4-byte aligned. 2985 // notZero means at least one not 4-byte aligned.

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