4239 load_for_type_by_register(dst_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type); |
4239 load_for_type_by_register(dst_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type); |
4240 } |
4240 } |
4241 |
4241 |
4242 return code_offset; |
4242 return code_offset; |
4243 } |
4243 } |
|
4244 |
|
4245 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) { |
|
4246 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask); |
|
4247 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code |
|
4248 // The inverted mask is sign-extended |
|
4249 move(AT, inverted_jweak_mask); |
|
4250 andr(possibly_jweak, AT, possibly_jweak); |
|
4251 } |
|
4252 |
|
4253 void MacroAssembler::resolve_jobject(Register value, |
|
4254 Register thread, |
|
4255 Register tmp) { |
|
4256 assert_different_registers(value, thread, tmp); |
|
4257 Label done, not_weak; |
|
4258 beq(value, R0, done); // Use NULL as-is. |
|
4259 delayed()->nop(); |
|
4260 move(AT, JNIHandles::weak_tag_mask); // Test for jweak tag. |
|
4261 andr(AT, value, AT); |
|
4262 beq(AT, R0, not_weak); |
|
4263 delayed()->nop(); |
|
4264 // Resolve jweak. |
|
4265 ld(value, value, -JNIHandles::weak_tag_value); |
|
4266 verify_oop(value); |
|
4267 #if INCLUDE_ALL_GCS |
|
4268 if (UseG1GC) { |
|
4269 g1_write_barrier_pre(noreg /* obj */, |
|
4270 value /* pre_val */, |
|
4271 thread /* thread */, |
|
4272 tmp /* tmp */, |
|
4273 true /* tosca_live */, |
|
4274 true /* expand_call */); |
|
4275 } |
|
4276 #endif // INCLUDE_ALL_GCS |
|
4277 b(done); |
|
4278 delayed()->nop(); |
|
4279 bind(not_weak); |
|
4280 // Resolve (untagged) jobject. |
|
4281 ld(value, value, 0); |
|
4282 verify_oop(value); |
|
4283 bind(done); |
|
4284 } |