Wed, 27 Apr 2016 01:25:04 +0800
Initial load
http://hg.openjdk.java.net/jdk8u/jdk8u/hotspot/
changeset: 6782:28b50d07f6f8
tag: jdk8u25-b17
aoqi@0 | 1 | /* |
aoqi@0 | 2 | * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
aoqi@0 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@0 | 4 | * |
aoqi@0 | 5 | * This code is free software; you can redistribute it and/or modify it |
aoqi@0 | 6 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@0 | 7 | * published by the Free Software Foundation. |
aoqi@0 | 8 | * |
aoqi@0 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@0 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@0 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@0 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@0 | 13 | * accompanied this code). |
aoqi@0 | 14 | * |
aoqi@0 | 15 | * You should have received a copy of the GNU General Public License version |
aoqi@0 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@0 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@0 | 18 | * |
aoqi@0 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@0 | 20 | * or visit www.oracle.com if you need additional information or have any |
aoqi@0 | 21 | * questions. |
aoqi@0 | 22 | * |
aoqi@0 | 23 | */ |
aoqi@0 | 24 | |
aoqi@0 | 25 | #ifndef CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP |
aoqi@0 | 26 | #define CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP |
aoqi@0 | 27 | |
aoqi@0 | 28 | #include "asm/assembler.hpp" |
aoqi@0 | 29 | #include "utilities/macros.hpp" |
aoqi@0 | 30 | |
aoqi@0 | 31 | // <sys/trap.h> promises that the system will not use traps 16-31 |
aoqi@0 | 32 | #define ST_RESERVED_FOR_USER_0 0x10 |
aoqi@0 | 33 | |
aoqi@0 | 34 | class BiasedLockingCounters; |
aoqi@0 | 35 | |
aoqi@0 | 36 | |
aoqi@0 | 37 | // Register aliases for parts of the system: |
aoqi@0 | 38 | |
aoqi@0 | 39 | // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe |
aoqi@0 | 40 | // across context switches in V8+ ABI. Of course, there are no 64 bit regs |
aoqi@0 | 41 | // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers. |
aoqi@0 | 42 | |
aoqi@0 | 43 | // g2-g4 are scratch registers called "application globals". Their |
aoqi@0 | 44 | // meaning is reserved to the "compilation system"--which means us! |
aoqi@0 | 45 | // They are are not supposed to be touched by ordinary C code, although |
aoqi@0 | 46 | // highly-optimized C code might steal them for temps. They are safe |
aoqi@0 | 47 | // across thread switches, and the ABI requires that they be safe |
aoqi@0 | 48 | // across function calls. |
aoqi@0 | 49 | // |
aoqi@0 | 50 | // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered |
aoqi@0 | 51 | // across func calls, and V8+ also allows g5 to be clobbered across |
aoqi@0 | 52 | // func calls. Also, g1 and g5 can get touched while doing shared |
aoqi@0 | 53 | // library loading. |
aoqi@0 | 54 | // |
aoqi@0 | 55 | // We must not touch g7 (it is the thread-self register) and g6 is |
aoqi@0 | 56 | // reserved for certain tools. g0, of course, is always zero. |
aoqi@0 | 57 | // |
aoqi@0 | 58 | // (Sources: SunSoft Compilers Group, thread library engineers.) |
aoqi@0 | 59 | |
aoqi@0 | 60 | // %%%% The interpreter should be revisited to reduce global scratch regs. |
aoqi@0 | 61 | |
aoqi@0 | 62 | // This global always holds the current JavaThread pointer: |
aoqi@0 | 63 | |
aoqi@0 | 64 | REGISTER_DECLARATION(Register, G2_thread , G2); |
aoqi@0 | 65 | REGISTER_DECLARATION(Register, G6_heapbase , G6); |
aoqi@0 | 66 | |
aoqi@0 | 67 | // The following globals are part of the Java calling convention: |
aoqi@0 | 68 | |
aoqi@0 | 69 | REGISTER_DECLARATION(Register, G5_method , G5); |
aoqi@0 | 70 | REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method); |
aoqi@0 | 71 | REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method); |
aoqi@0 | 72 | |
aoqi@0 | 73 | // The following globals are used for the new C1 & interpreter calling convention: |
aoqi@0 | 74 | REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument |
aoqi@0 | 75 | |
aoqi@0 | 76 | // This local is used to preserve G2_thread in the interpreter and in stubs: |
aoqi@0 | 77 | REGISTER_DECLARATION(Register, L7_thread_cache , L7); |
aoqi@0 | 78 | |
aoqi@0 | 79 | // These globals are used as scratch registers in the interpreter: |
aoqi@0 | 80 | |
aoqi@0 | 81 | REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch |
aoqi@0 | 82 | REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME |
aoqi@0 | 83 | REGISTER_DECLARATION(Register, G3_scratch , G3); |
aoqi@0 | 84 | REGISTER_DECLARATION(Register, G4_scratch , G4); |
aoqi@0 | 85 | |
aoqi@0 | 86 | // These globals are used as short-lived scratch registers in the compiler: |
aoqi@0 | 87 | |
aoqi@0 | 88 | REGISTER_DECLARATION(Register, Gtemp , G5); |
aoqi@0 | 89 | |
aoqi@0 | 90 | // JSR 292 fixed register usages: |
aoqi@0 | 91 | REGISTER_DECLARATION(Register, G5_method_type , G5); |
aoqi@0 | 92 | REGISTER_DECLARATION(Register, G3_method_handle , G3); |
aoqi@0 | 93 | REGISTER_DECLARATION(Register, L7_mh_SP_save , L7); |
aoqi@0 | 94 | |
aoqi@0 | 95 | // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass, |
aoqi@0 | 96 | // because a single patchable "set" instruction (NativeMovConstReg, |
aoqi@0 | 97 | // or NativeMovConstPatching for compiler1) instruction |
aoqi@0 | 98 | // serves to set up either quantity, depending on whether the compiled |
aoqi@0 | 99 | // call site is an inline cache or is megamorphic. See the function |
aoqi@0 | 100 | // CompiledIC::set_to_megamorphic. |
aoqi@0 | 101 | // |
aoqi@0 | 102 | // If a inline cache targets an interpreted method, then the |
aoqi@0 | 103 | // G5 register will be used twice during the call. First, |
aoqi@0 | 104 | // the call site will be patched to load a compiledICHolder |
aoqi@0 | 105 | // into G5. (This is an ordered pair of ic_klass, method.) |
aoqi@0 | 106 | // The c2i adapter will first check the ic_klass, then load |
aoqi@0 | 107 | // G5_method with the method part of the pair just before |
aoqi@0 | 108 | // jumping into the interpreter. |
aoqi@0 | 109 | // |
aoqi@0 | 110 | // Note that G5_method is only the method-self for the interpreter, |
aoqi@0 | 111 | // and is logically unrelated to G5_megamorphic_method. |
aoqi@0 | 112 | // |
aoqi@0 | 113 | // Invariants on G2_thread (the JavaThread pointer): |
aoqi@0 | 114 | // - it should not be used for any other purpose anywhere |
aoqi@0 | 115 | // - it must be re-initialized by StubRoutines::call_stub() |
aoqi@0 | 116 | // - it must be preserved around every use of call_VM |
aoqi@0 | 117 | |
aoqi@0 | 118 | // We can consider using g2/g3/g4 to cache more values than the |
aoqi@0 | 119 | // JavaThread, such as the card-marking base or perhaps pointers into |
aoqi@0 | 120 | // Eden. It's something of a waste to use them as scratch temporaries, |
aoqi@0 | 121 | // since they are not supposed to be volatile. (Of course, if we find |
aoqi@0 | 122 | // that Java doesn't benefit from application globals, then we can just |
aoqi@0 | 123 | // use them as ordinary temporaries.) |
aoqi@0 | 124 | // |
aoqi@0 | 125 | // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers, |
aoqi@0 | 126 | // it makes sense to use them routinely for procedure linkage, |
aoqi@0 | 127 | // whenever the On registers are not applicable. Examples: G5_method, |
aoqi@0 | 128 | // G5_inline_cache_klass, and a double handful of miscellaneous compiler |
aoqi@0 | 129 | // stubs. This means that compiler stubs, etc., should be kept to a |
aoqi@0 | 130 | // maximum of two or three G-register arguments. |
aoqi@0 | 131 | |
aoqi@0 | 132 | |
aoqi@0 | 133 | // stub frames |
aoqi@0 | 134 | |
aoqi@0 | 135 | REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself |
aoqi@0 | 136 | |
aoqi@0 | 137 | // Interpreter frames |
aoqi@0 | 138 | |
aoqi@0 | 139 | #ifdef CC_INTERP |
aoqi@0 | 140 | REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer |
aoqi@0 | 141 | REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch |
aoqi@0 | 142 | REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only) |
aoqi@0 | 143 | REGISTER_DECLARATION(Register, L2_scratch , L2); |
aoqi@0 | 144 | REGISTER_DECLARATION(Register, L3_scratch , L3); |
aoqi@0 | 145 | REGISTER_DECLARATION(Register, L4_scratch , L4); |
aoqi@0 | 146 | REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses |
aoqi@0 | 147 | REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses |
aoqi@0 | 148 | REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache |
aoqi@0 | 149 | REGISTER_DECLARATION(Register, O5_savedSP , O5); |
aoqi@0 | 150 | REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply |
aoqi@0 | 151 | // a copy SP, so in 64-bit it's a biased value. The bias |
aoqi@0 | 152 | // is added and removed as needed in the frame code. |
aoqi@0 | 153 | // Interface to signature handler |
aoqi@0 | 154 | REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler |
aoqi@0 | 155 | REGISTER_DECLARATION(Register, Lmethod , L6); // Method* when calling signature handler |
aoqi@0 | 156 | |
aoqi@0 | 157 | #else |
aoqi@0 | 158 | REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer |
aoqi@0 | 159 | REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode |
aoqi@0 | 160 | REGISTER_DECLARATION(Register, Lmethod , L2); |
aoqi@0 | 161 | REGISTER_DECLARATION(Register, Llocals , L3); |
aoqi@0 | 162 | REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler |
aoqi@0 | 163 | // must match Llocals in asm interpreter |
aoqi@0 | 164 | REGISTER_DECLARATION(Register, Lmonitors , L4); |
aoqi@0 | 165 | REGISTER_DECLARATION(Register, Lbyte_code , L5); |
aoqi@0 | 166 | // When calling out from the interpreter we record SP so that we can remove any extra stack |
aoqi@0 | 167 | // space allocated during adapter transitions. This register is only live from the point |
aoqi@0 | 168 | // of the call until we return. |
aoqi@0 | 169 | REGISTER_DECLARATION(Register, Llast_SP , L5); |
aoqi@0 | 170 | REGISTER_DECLARATION(Register, Lscratch , L5); |
aoqi@0 | 171 | REGISTER_DECLARATION(Register, Lscratch2 , L6); |
aoqi@0 | 172 | REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache |
aoqi@0 | 173 | |
aoqi@0 | 174 | REGISTER_DECLARATION(Register, O5_savedSP , O5); |
aoqi@0 | 175 | REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply |
aoqi@0 | 176 | // a copy SP, so in 64-bit it's a biased value. The bias |
aoqi@0 | 177 | // is added and removed as needed in the frame code. |
aoqi@0 | 178 | REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables |
aoqi@0 | 179 | REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode |
aoqi@0 | 180 | REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data |
aoqi@0 | 181 | #endif /* CC_INTERP */ |
aoqi@0 | 182 | |
aoqi@0 | 183 | // NOTE: Lscratch2 and LcpoolCache point to the same registers in |
aoqi@0 | 184 | // the interpreter code. If Lscratch2 needs to be used for some |
aoqi@0 | 185 | // purpose than LcpoolCache should be restore after that for |
aoqi@0 | 186 | // the interpreter to work right |
aoqi@0 | 187 | // (These assignments must be compatible with L7_thread_cache; see above.) |
aoqi@0 | 188 | |
aoqi@0 | 189 | // Since Lbcp points into the middle of the method object, |
aoqi@0 | 190 | // it is temporarily converted into a "bcx" during GC. |
aoqi@0 | 191 | |
aoqi@0 | 192 | // Exception processing |
aoqi@0 | 193 | // These registers are passed into exception handlers. |
aoqi@0 | 194 | // All exception handlers require the exception object being thrown. |
aoqi@0 | 195 | // In addition, an nmethod's exception handler must be passed |
aoqi@0 | 196 | // the address of the call site within the nmethod, to allow |
aoqi@0 | 197 | // proper selection of the applicable catch block. |
aoqi@0 | 198 | // (Interpreter frames use their own bcp() for this purpose.) |
aoqi@0 | 199 | // |
aoqi@0 | 200 | // The Oissuing_pc value is not always needed. When jumping to a |
aoqi@0 | 201 | // handler that is known to be interpreted, the Oissuing_pc value can be |
aoqi@0 | 202 | // omitted. An actual catch block in compiled code receives (from its |
aoqi@0 | 203 | // nmethod's exception handler) the thrown exception in the Oexception, |
aoqi@0 | 204 | // but it doesn't need the Oissuing_pc. |
aoqi@0 | 205 | // |
aoqi@0 | 206 | // If an exception handler (either interpreted or compiled) |
aoqi@0 | 207 | // discovers there is no applicable catch block, it updates |
aoqi@0 | 208 | // the Oissuing_pc to the continuation PC of its own caller, |
aoqi@0 | 209 | // pops back to that caller's stack frame, and executes that |
aoqi@0 | 210 | // caller's exception handler. Obviously, this process will |
aoqi@0 | 211 | // iterate until the control stack is popped back to a method |
aoqi@0 | 212 | // containing an applicable catch block. A key invariant is |
aoqi@0 | 213 | // that the Oissuing_pc value is always a value local to |
aoqi@0 | 214 | // the method whose exception handler is currently executing. |
aoqi@0 | 215 | // |
aoqi@0 | 216 | // Note: The issuing PC value is __not__ a raw return address (I7 value). |
aoqi@0 | 217 | // It is a "return pc", the address __following__ the call. |
aoqi@0 | 218 | // Raw return addresses are converted to issuing PCs by frame::pc(), |
aoqi@0 | 219 | // or by stubs. Issuing PCs can be used directly with PC range tables. |
aoqi@0 | 220 | // |
aoqi@0 | 221 | REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown |
aoqi@0 | 222 | REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from |
aoqi@0 | 223 | |
aoqi@0 | 224 | |
aoqi@0 | 225 | // These must occur after the declarations above |
aoqi@0 | 226 | #ifndef DONT_USE_REGISTER_DEFINES |
aoqi@0 | 227 | |
aoqi@0 | 228 | #define Gthread AS_REGISTER(Register, Gthread) |
aoqi@0 | 229 | #define Gmethod AS_REGISTER(Register, Gmethod) |
aoqi@0 | 230 | #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method) |
aoqi@0 | 231 | #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg) |
aoqi@0 | 232 | #define Gargs AS_REGISTER(Register, Gargs) |
aoqi@0 | 233 | #define Lthread_cache AS_REGISTER(Register, Lthread_cache) |
aoqi@0 | 234 | #define Gframe_size AS_REGISTER(Register, Gframe_size) |
aoqi@0 | 235 | #define Gtemp AS_REGISTER(Register, Gtemp) |
aoqi@0 | 236 | |
aoqi@0 | 237 | #ifdef CC_INTERP |
aoqi@0 | 238 | #define Lstate AS_REGISTER(Register, Lstate) |
aoqi@0 | 239 | #define Lesp AS_REGISTER(Register, Lesp) |
aoqi@0 | 240 | #define L1_scratch AS_REGISTER(Register, L1_scratch) |
aoqi@0 | 241 | #define Lmirror AS_REGISTER(Register, Lmirror) |
aoqi@0 | 242 | #define L2_scratch AS_REGISTER(Register, L2_scratch) |
aoqi@0 | 243 | #define L3_scratch AS_REGISTER(Register, L3_scratch) |
aoqi@0 | 244 | #define L4_scratch AS_REGISTER(Register, L4_scratch) |
aoqi@0 | 245 | #define Lscratch AS_REGISTER(Register, Lscratch) |
aoqi@0 | 246 | #define Lscratch2 AS_REGISTER(Register, Lscratch2) |
aoqi@0 | 247 | #define L7_scratch AS_REGISTER(Register, L7_scratch) |
aoqi@0 | 248 | #define Ostate AS_REGISTER(Register, Ostate) |
aoqi@0 | 249 | #else |
aoqi@0 | 250 | #define Lesp AS_REGISTER(Register, Lesp) |
aoqi@0 | 251 | #define Lbcp AS_REGISTER(Register, Lbcp) |
aoqi@0 | 252 | #define Lmethod AS_REGISTER(Register, Lmethod) |
aoqi@0 | 253 | #define Llocals AS_REGISTER(Register, Llocals) |
aoqi@0 | 254 | #define Lmonitors AS_REGISTER(Register, Lmonitors) |
aoqi@0 | 255 | #define Lbyte_code AS_REGISTER(Register, Lbyte_code) |
aoqi@0 | 256 | #define Lscratch AS_REGISTER(Register, Lscratch) |
aoqi@0 | 257 | #define Lscratch2 AS_REGISTER(Register, Lscratch2) |
aoqi@0 | 258 | #define LcpoolCache AS_REGISTER(Register, LcpoolCache) |
aoqi@0 | 259 | #endif /* ! CC_INTERP */ |
aoqi@0 | 260 | |
aoqi@0 | 261 | #define Lentry_args AS_REGISTER(Register, Lentry_args) |
aoqi@0 | 262 | #define I5_savedSP AS_REGISTER(Register, I5_savedSP) |
aoqi@0 | 263 | #define O5_savedSP AS_REGISTER(Register, O5_savedSP) |
aoqi@0 | 264 | #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress) |
aoqi@0 | 265 | #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr) |
aoqi@0 | 266 | #define IdispatchTables AS_REGISTER(Register, IdispatchTables) |
aoqi@0 | 267 | |
aoqi@0 | 268 | #define Oexception AS_REGISTER(Register, Oexception) |
aoqi@0 | 269 | #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc) |
aoqi@0 | 270 | |
aoqi@0 | 271 | #endif |
aoqi@0 | 272 | |
aoqi@0 | 273 | |
aoqi@0 | 274 | // Address is an abstraction used to represent a memory location. |
aoqi@0 | 275 | // |
aoqi@0 | 276 | // Note: A register location is represented via a Register, not |
aoqi@0 | 277 | // via an address for efficiency & simplicity reasons. |
aoqi@0 | 278 | |
aoqi@0 | 279 | class Address VALUE_OBJ_CLASS_SPEC { |
aoqi@0 | 280 | private: |
aoqi@0 | 281 | Register _base; // Base register. |
aoqi@0 | 282 | RegisterOrConstant _index_or_disp; // Index register or constant displacement. |
aoqi@0 | 283 | RelocationHolder _rspec; |
aoqi@0 | 284 | |
aoqi@0 | 285 | public: |
aoqi@0 | 286 | Address() : _base(noreg), _index_or_disp(noreg) {} |
aoqi@0 | 287 | |
aoqi@0 | 288 | Address(Register base, RegisterOrConstant index_or_disp) |
aoqi@0 | 289 | : _base(base), |
aoqi@0 | 290 | _index_or_disp(index_or_disp) { |
aoqi@0 | 291 | } |
aoqi@0 | 292 | |
aoqi@0 | 293 | Address(Register base, Register index) |
aoqi@0 | 294 | : _base(base), |
aoqi@0 | 295 | _index_or_disp(index) { |
aoqi@0 | 296 | } |
aoqi@0 | 297 | |
aoqi@0 | 298 | Address(Register base, int disp) |
aoqi@0 | 299 | : _base(base), |
aoqi@0 | 300 | _index_or_disp(disp) { |
aoqi@0 | 301 | } |
aoqi@0 | 302 | |
aoqi@0 | 303 | #ifdef ASSERT |
aoqi@0 | 304 | // ByteSize is only a class when ASSERT is defined, otherwise it's an int. |
aoqi@0 | 305 | Address(Register base, ByteSize disp) |
aoqi@0 | 306 | : _base(base), |
aoqi@0 | 307 | _index_or_disp(in_bytes(disp)) { |
aoqi@0 | 308 | } |
aoqi@0 | 309 | #endif |
aoqi@0 | 310 | |
aoqi@0 | 311 | // accessors |
aoqi@0 | 312 | Register base() const { return _base; } |
aoqi@0 | 313 | Register index() const { return _index_or_disp.as_register(); } |
aoqi@0 | 314 | int disp() const { return _index_or_disp.as_constant(); } |
aoqi@0 | 315 | |
aoqi@0 | 316 | bool has_index() const { return _index_or_disp.is_register(); } |
aoqi@0 | 317 | bool has_disp() const { return _index_or_disp.is_constant(); } |
aoqi@0 | 318 | |
aoqi@0 | 319 | bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); } |
aoqi@0 | 320 | |
aoqi@0 | 321 | const relocInfo::relocType rtype() { return _rspec.type(); } |
aoqi@0 | 322 | const RelocationHolder& rspec() { return _rspec; } |
aoqi@0 | 323 | |
aoqi@0 | 324 | RelocationHolder rspec(int offset) const { |
aoqi@0 | 325 | return offset == 0 ? _rspec : _rspec.plus(offset); |
aoqi@0 | 326 | } |
aoqi@0 | 327 | |
aoqi@0 | 328 | inline bool is_simm13(int offset = 0); // check disp+offset for overflow |
aoqi@0 | 329 | |
aoqi@0 | 330 | Address plus_disp(int plusdisp) const { // bump disp by a small amount |
aoqi@0 | 331 | assert(_index_or_disp.is_constant(), "must have a displacement"); |
aoqi@0 | 332 | Address a(base(), disp() + plusdisp); |
aoqi@0 | 333 | return a; |
aoqi@0 | 334 | } |
aoqi@0 | 335 | bool is_same_address(Address a) const { |
aoqi@0 | 336 | // disregard _rspec |
aoqi@0 | 337 | return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp()); |
aoqi@0 | 338 | } |
aoqi@0 | 339 | |
aoqi@0 | 340 | Address after_save() const { |
aoqi@0 | 341 | Address a = (*this); |
aoqi@0 | 342 | a._base = a._base->after_save(); |
aoqi@0 | 343 | return a; |
aoqi@0 | 344 | } |
aoqi@0 | 345 | |
aoqi@0 | 346 | Address after_restore() const { |
aoqi@0 | 347 | Address a = (*this); |
aoqi@0 | 348 | a._base = a._base->after_restore(); |
aoqi@0 | 349 | return a; |
aoqi@0 | 350 | } |
aoqi@0 | 351 | |
aoqi@0 | 352 | // Convert the raw encoding form into the form expected by the |
aoqi@0 | 353 | // constructor for Address. |
aoqi@0 | 354 | static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); |
aoqi@0 | 355 | |
aoqi@0 | 356 | friend class Assembler; |
aoqi@0 | 357 | }; |
aoqi@0 | 358 | |
aoqi@0 | 359 | |
aoqi@0 | 360 | class AddressLiteral VALUE_OBJ_CLASS_SPEC { |
aoqi@0 | 361 | private: |
aoqi@0 | 362 | address _address; |
aoqi@0 | 363 | RelocationHolder _rspec; |
aoqi@0 | 364 | |
aoqi@0 | 365 | RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { |
aoqi@0 | 366 | switch (rtype) { |
aoqi@0 | 367 | case relocInfo::external_word_type: |
aoqi@0 | 368 | return external_word_Relocation::spec(addr); |
aoqi@0 | 369 | case relocInfo::internal_word_type: |
aoqi@0 | 370 | return internal_word_Relocation::spec(addr); |
aoqi@0 | 371 | #ifdef _LP64 |
aoqi@0 | 372 | case relocInfo::opt_virtual_call_type: |
aoqi@0 | 373 | return opt_virtual_call_Relocation::spec(); |
aoqi@0 | 374 | case relocInfo::static_call_type: |
aoqi@0 | 375 | return static_call_Relocation::spec(); |
aoqi@0 | 376 | case relocInfo::runtime_call_type: |
aoqi@0 | 377 | return runtime_call_Relocation::spec(); |
aoqi@0 | 378 | #endif |
aoqi@0 | 379 | case relocInfo::none: |
aoqi@0 | 380 | return RelocationHolder(); |
aoqi@0 | 381 | default: |
aoqi@0 | 382 | ShouldNotReachHere(); |
aoqi@0 | 383 | return RelocationHolder(); |
aoqi@0 | 384 | } |
aoqi@0 | 385 | } |
aoqi@0 | 386 | |
aoqi@0 | 387 | protected: |
aoqi@0 | 388 | // creation |
aoqi@0 | 389 | AddressLiteral() : _address(NULL), _rspec(NULL) {} |
aoqi@0 | 390 | |
aoqi@0 | 391 | public: |
aoqi@0 | 392 | AddressLiteral(address addr, RelocationHolder const& rspec) |
aoqi@0 | 393 | : _address(addr), |
aoqi@0 | 394 | _rspec(rspec) {} |
aoqi@0 | 395 | |
aoqi@0 | 396 | // Some constructors to avoid casting at the call site. |
aoqi@0 | 397 | AddressLiteral(jobject obj, RelocationHolder const& rspec) |
aoqi@0 | 398 | : _address((address) obj), |
aoqi@0 | 399 | _rspec(rspec) {} |
aoqi@0 | 400 | |
aoqi@0 | 401 | AddressLiteral(intptr_t value, RelocationHolder const& rspec) |
aoqi@0 | 402 | : _address((address) value), |
aoqi@0 | 403 | _rspec(rspec) {} |
aoqi@0 | 404 | |
aoqi@0 | 405 | AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 406 | : _address((address) addr), |
aoqi@0 | 407 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 408 | |
aoqi@0 | 409 | // Some constructors to avoid casting at the call site. |
aoqi@0 | 410 | AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 411 | : _address((address) addr), |
aoqi@0 | 412 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 413 | |
aoqi@0 | 414 | AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 415 | : _address((address) addr), |
aoqi@0 | 416 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 417 | |
aoqi@0 | 418 | AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 419 | : _address((address) addr), |
aoqi@0 | 420 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 421 | |
aoqi@0 | 422 | AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 423 | : _address((address) addr), |
aoqi@0 | 424 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 425 | |
aoqi@0 | 426 | AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 427 | : _address((address) addr), |
aoqi@0 | 428 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 429 | |
aoqi@0 | 430 | AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 431 | : _address((address) addr), |
aoqi@0 | 432 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 433 | |
aoqi@0 | 434 | #ifdef _LP64 |
aoqi@0 | 435 | // 32-bit complains about a multiple declaration for int*. |
aoqi@0 | 436 | AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 437 | : _address((address) addr), |
aoqi@0 | 438 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 439 | #endif |
aoqi@0 | 440 | |
aoqi@0 | 441 | AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 442 | : _address((address) addr), |
aoqi@0 | 443 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 444 | |
aoqi@0 | 445 | AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 446 | : _address((address) addr), |
aoqi@0 | 447 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 448 | |
aoqi@0 | 449 | AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 450 | : _address((address) addr), |
aoqi@0 | 451 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 452 | |
aoqi@0 | 453 | AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) |
aoqi@0 | 454 | : _address((address) addr), |
aoqi@0 | 455 | _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
aoqi@0 | 456 | |
aoqi@0 | 457 | intptr_t value() const { return (intptr_t) _address; } |
aoqi@0 | 458 | int low10() const; |
aoqi@0 | 459 | |
aoqi@0 | 460 | const relocInfo::relocType rtype() const { return _rspec.type(); } |
aoqi@0 | 461 | const RelocationHolder& rspec() const { return _rspec; } |
aoqi@0 | 462 | |
aoqi@0 | 463 | RelocationHolder rspec(int offset) const { |
aoqi@0 | 464 | return offset == 0 ? _rspec : _rspec.plus(offset); |
aoqi@0 | 465 | } |
aoqi@0 | 466 | }; |
aoqi@0 | 467 | |
aoqi@0 | 468 | // Convenience classes |
aoqi@0 | 469 | class ExternalAddress: public AddressLiteral { |
aoqi@0 | 470 | private: |
aoqi@0 | 471 | static relocInfo::relocType reloc_for_target(address target) { |
aoqi@0 | 472 | // Sometimes ExternalAddress is used for values which aren't |
aoqi@0 | 473 | // exactly addresses, like the card table base. |
aoqi@0 | 474 | // external_word_type can't be used for values in the first page |
aoqi@0 | 475 | // so just skip the reloc in that case. |
aoqi@0 | 476 | return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
aoqi@0 | 477 | } |
aoqi@0 | 478 | |
aoqi@0 | 479 | public: |
aoqi@0 | 480 | ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {} |
aoqi@0 | 481 | ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {} |
aoqi@0 | 482 | }; |
aoqi@0 | 483 | |
aoqi@0 | 484 | inline Address RegisterImpl::address_in_saved_window() const { |
aoqi@0 | 485 | return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS)); |
aoqi@0 | 486 | } |
aoqi@0 | 487 | |
aoqi@0 | 488 | |
aoqi@0 | 489 | |
aoqi@0 | 490 | // Argument is an abstraction used to represent an outgoing |
aoqi@0 | 491 | // actual argument or an incoming formal parameter, whether |
aoqi@0 | 492 | // it resides in memory or in a register, in a manner consistent |
aoqi@0 | 493 | // with the SPARC Application Binary Interface, or ABI. This is |
aoqi@0 | 494 | // often referred to as the native or C calling convention. |
aoqi@0 | 495 | |
aoqi@0 | 496 | class Argument VALUE_OBJ_CLASS_SPEC { |
aoqi@0 | 497 | private: |
aoqi@0 | 498 | int _number; |
aoqi@0 | 499 | bool _is_in; |
aoqi@0 | 500 | |
aoqi@0 | 501 | public: |
aoqi@0 | 502 | #ifdef _LP64 |
aoqi@0 | 503 | enum { |
aoqi@0 | 504 | n_register_parameters = 6, // only 6 registers may contain integer parameters |
aoqi@0 | 505 | n_float_register_parameters = 16 // Can have up to 16 floating registers |
aoqi@0 | 506 | }; |
aoqi@0 | 507 | #else |
aoqi@0 | 508 | enum { |
aoqi@0 | 509 | n_register_parameters = 6 // only 6 registers may contain integer parameters |
aoqi@0 | 510 | }; |
aoqi@0 | 511 | #endif |
aoqi@0 | 512 | |
aoqi@0 | 513 | // creation |
aoqi@0 | 514 | Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} |
aoqi@0 | 515 | |
aoqi@0 | 516 | int number() const { return _number; } |
aoqi@0 | 517 | bool is_in() const { return _is_in; } |
aoqi@0 | 518 | bool is_out() const { return !is_in(); } |
aoqi@0 | 519 | |
aoqi@0 | 520 | Argument successor() const { return Argument(number() + 1, is_in()); } |
aoqi@0 | 521 | Argument as_in() const { return Argument(number(), true ); } |
aoqi@0 | 522 | Argument as_out() const { return Argument(number(), false); } |
aoqi@0 | 523 | |
aoqi@0 | 524 | // locating register-based arguments: |
aoqi@0 | 525 | bool is_register() const { return _number < n_register_parameters; } |
aoqi@0 | 526 | |
aoqi@0 | 527 | #ifdef _LP64 |
aoqi@0 | 528 | // locating Floating Point register-based arguments: |
aoqi@0 | 529 | bool is_float_register() const { return _number < n_float_register_parameters; } |
aoqi@0 | 530 | |
aoqi@0 | 531 | FloatRegister as_float_register() const { |
aoqi@0 | 532 | assert(is_float_register(), "must be a register argument"); |
aoqi@0 | 533 | return as_FloatRegister(( number() *2 ) + 1); |
aoqi@0 | 534 | } |
aoqi@0 | 535 | FloatRegister as_double_register() const { |
aoqi@0 | 536 | assert(is_float_register(), "must be a register argument"); |
aoqi@0 | 537 | return as_FloatRegister(( number() *2 )); |
aoqi@0 | 538 | } |
aoqi@0 | 539 | #endif |
aoqi@0 | 540 | |
aoqi@0 | 541 | Register as_register() const { |
aoqi@0 | 542 | assert(is_register(), "must be a register argument"); |
aoqi@0 | 543 | return is_in() ? as_iRegister(number()) : as_oRegister(number()); |
aoqi@0 | 544 | } |
aoqi@0 | 545 | |
aoqi@0 | 546 | // locating memory-based arguments |
aoqi@0 | 547 | Address as_address() const { |
aoqi@0 | 548 | assert(!is_register(), "must be a memory argument"); |
aoqi@0 | 549 | return address_in_frame(); |
aoqi@0 | 550 | } |
aoqi@0 | 551 | |
aoqi@0 | 552 | // When applied to a register-based argument, give the corresponding address |
aoqi@0 | 553 | // into the 6-word area "into which callee may store register arguments" |
aoqi@0 | 554 | // (This is a different place than the corresponding register-save area location.) |
aoqi@0 | 555 | Address address_in_frame() const; |
aoqi@0 | 556 | |
aoqi@0 | 557 | // debugging |
aoqi@0 | 558 | const char* name() const; |
aoqi@0 | 559 | |
aoqi@0 | 560 | friend class Assembler; |
aoqi@0 | 561 | }; |
aoqi@0 | 562 | |
aoqi@0 | 563 | |
aoqi@0 | 564 | class RegistersForDebugging : public StackObj { |
aoqi@0 | 565 | public: |
aoqi@0 | 566 | intptr_t i[8], l[8], o[8], g[8]; |
aoqi@0 | 567 | float f[32]; |
aoqi@0 | 568 | double d[32]; |
aoqi@0 | 569 | |
aoqi@0 | 570 | void print(outputStream* s); |
aoqi@0 | 571 | |
aoqi@0 | 572 | static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); } |
aoqi@0 | 573 | static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); } |
aoqi@0 | 574 | static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); } |
aoqi@0 | 575 | static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); } |
aoqi@0 | 576 | static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); } |
aoqi@0 | 577 | static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); } |
aoqi@0 | 578 | |
aoqi@0 | 579 | // gen asm code to save regs |
aoqi@0 | 580 | static void save_registers(MacroAssembler* a); |
aoqi@0 | 581 | |
aoqi@0 | 582 | // restore global registers in case C code disturbed them |
aoqi@0 | 583 | static void restore_registers(MacroAssembler* a, Register r); |
aoqi@0 | 584 | }; |
aoqi@0 | 585 | |
aoqi@0 | 586 | |
aoqi@0 | 587 | // MacroAssembler extends Assembler by a few frequently used macros. |
aoqi@0 | 588 | // |
aoqi@0 | 589 | // Most of the standard SPARC synthetic ops are defined here. |
aoqi@0 | 590 | // Instructions for which a 'better' code sequence exists depending |
aoqi@0 | 591 | // on arguments should also go in here. |
aoqi@0 | 592 | |
aoqi@0 | 593 | #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__) |
aoqi@0 | 594 | #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__) |
aoqi@0 | 595 | #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__) |
aoqi@0 | 596 | #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__) |
aoqi@0 | 597 | |
aoqi@0 | 598 | |
aoqi@0 | 599 | class MacroAssembler : public Assembler { |
aoqi@0 | 600 | // code patchers need various routines like inv_wdisp() |
aoqi@0 | 601 | friend class NativeInstruction; |
aoqi@0 | 602 | friend class NativeGeneralJump; |
aoqi@0 | 603 | friend class Relocation; |
aoqi@0 | 604 | friend class Label; |
aoqi@0 | 605 | |
aoqi@0 | 606 | protected: |
aoqi@0 | 607 | static int patched_branch(int dest_pos, int inst, int inst_pos); |
aoqi@0 | 608 | static int branch_destination(int inst, int pos); |
aoqi@0 | 609 | |
aoqi@0 | 610 | // Support for VM calls |
aoqi@0 | 611 | // This is the base routine called by the different versions of call_VM_leaf. The interpreter |
aoqi@0 | 612 | // may customize this version by overriding it for its purposes (e.g., to save/restore |
aoqi@0 | 613 | // additional registers when doing a VM call). |
aoqi@0 | 614 | #ifdef CC_INTERP |
aoqi@0 | 615 | #define VIRTUAL |
aoqi@0 | 616 | #else |
aoqi@0 | 617 | #define VIRTUAL virtual |
aoqi@0 | 618 | #endif |
aoqi@0 | 619 | |
aoqi@0 | 620 | VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments); |
aoqi@0 | 621 | |
aoqi@0 | 622 | // |
aoqi@0 | 623 | // It is imperative that all calls into the VM are handled via the call_VM macros. |
aoqi@0 | 624 | // They make sure that the stack linkage is setup correctly. call_VM's correspond |
aoqi@0 | 625 | // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. |
aoqi@0 | 626 | // |
aoqi@0 | 627 | // This is the base routine called by the different versions of call_VM. The interpreter |
aoqi@0 | 628 | // may customize this version by overriding it for its purposes (e.g., to save/restore |
aoqi@0 | 629 | // additional registers when doing a VM call). |
aoqi@0 | 630 | // |
aoqi@0 | 631 | // A non-volatile java_thread_cache register should be specified so |
aoqi@0 | 632 | // that the G2_thread value can be preserved across the call. |
aoqi@0 | 633 | // (If java_thread_cache is noreg, then a slow get_thread call |
aoqi@0 | 634 | // will re-initialize the G2_thread.) call_VM_base returns the register that contains the |
aoqi@0 | 635 | // thread. |
aoqi@0 | 636 | // |
aoqi@0 | 637 | // If no last_java_sp is specified (noreg) than SP will be used instead. |
aoqi@0 | 638 | |
aoqi@0 | 639 | virtual void call_VM_base( |
aoqi@0 | 640 | Register oop_result, // where an oop-result ends up if any; use noreg otherwise |
aoqi@0 | 641 | Register java_thread_cache, // the thread if computed before ; use noreg otherwise |
aoqi@0 | 642 | Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise |
aoqi@0 | 643 | address entry_point, // the entry point |
aoqi@0 | 644 | int number_of_arguments, // the number of arguments (w/o thread) to pop after call |
aoqi@0 | 645 | bool check_exception=true // flag which indicates if exception should be checked |
aoqi@0 | 646 | ); |
aoqi@0 | 647 | |
aoqi@0 | 648 | // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code. |
aoqi@0 | 649 | // The implementation is only non-empty for the InterpreterMacroAssembler, |
aoqi@0 | 650 | // as only the interpreter handles and ForceEarlyReturn PopFrame requests. |
aoqi@0 | 651 | virtual void check_and_handle_popframe(Register scratch_reg); |
aoqi@0 | 652 | virtual void check_and_handle_earlyret(Register scratch_reg); |
aoqi@0 | 653 | |
aoqi@0 | 654 | public: |
aoqi@0 | 655 | MacroAssembler(CodeBuffer* code) : Assembler(code) {} |
aoqi@0 | 656 | |
aoqi@0 | 657 | // Support for NULL-checks |
aoqi@0 | 658 | // |
aoqi@0 | 659 | // Generates code that causes a NULL OS exception if the content of reg is NULL. |
aoqi@0 | 660 | // If the accessed location is M[reg + offset] and the offset is known, provide the |
aoqi@0 | 661 | // offset. No explicit code generation is needed if the offset is within a certain |
aoqi@0 | 662 | // range (0 <= offset <= page_size). |
aoqi@0 | 663 | // |
aoqi@0 | 664 | // %%%%%% Currently not done for SPARC |
aoqi@0 | 665 | |
aoqi@0 | 666 | void null_check(Register reg, int offset = -1); |
aoqi@0 | 667 | static bool needs_explicit_null_check(intptr_t offset); |
aoqi@0 | 668 | |
aoqi@0 | 669 | // support for delayed instructions |
aoqi@0 | 670 | MacroAssembler* delayed() { Assembler::delayed(); return this; } |
aoqi@0 | 671 | |
aoqi@0 | 672 | // branches that use right instruction for v8 vs. v9 |
aoqi@0 | 673 | inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
aoqi@0 | 674 | inline void br( Condition c, bool a, Predict p, Label& L ); |
aoqi@0 | 675 | |
aoqi@0 | 676 | inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
aoqi@0 | 677 | inline void fb( Condition c, bool a, Predict p, Label& L ); |
aoqi@0 | 678 | |
aoqi@0 | 679 | // compares register with zero (32 bit) and branches (V9 and V8 instructions) |
aoqi@0 | 680 | void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn ); |
aoqi@0 | 681 | // Compares a pointer register with zero and branches on (not)null. |
aoqi@0 | 682 | // Does a test & branch on 32-bit systems and a register-branch on 64-bit. |
aoqi@0 | 683 | void br_null ( Register s1, bool a, Predict p, Label& L ); |
aoqi@0 | 684 | void br_notnull( Register s1, bool a, Predict p, Label& L ); |
aoqi@0 | 685 | |
aoqi@0 | 686 | // |
aoqi@0 | 687 | // Compare registers and branch with nop in delay slot or cbcond without delay slot. |
aoqi@0 | 688 | // |
aoqi@0 | 689 | // ATTENTION: use these instructions with caution because cbcond instruction |
aoqi@0 | 690 | // has very short distance: 512 instructions (2Kbyte). |
aoqi@0 | 691 | |
aoqi@0 | 692 | // Compare integer (32 bit) values (icc only). |
aoqi@0 | 693 | void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L); |
aoqi@0 | 694 | void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L); |
aoqi@0 | 695 | // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64). |
aoqi@0 | 696 | void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L); |
aoqi@0 | 697 | void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L); |
aoqi@0 | 698 | |
aoqi@0 | 699 | // Short branch version for compares a pointer pwith zero. |
aoqi@0 | 700 | void br_null_short ( Register s1, Predict p, Label& L ); |
aoqi@0 | 701 | void br_notnull_short( Register s1, Predict p, Label& L ); |
aoqi@0 | 702 | |
aoqi@0 | 703 | // unconditional short branch |
aoqi@0 | 704 | void ba_short(Label& L); |
aoqi@0 | 705 | |
aoqi@0 | 706 | inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
aoqi@0 | 707 | inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); |
aoqi@0 | 708 | |
aoqi@0 | 709 | // Branch that tests xcc in LP64 and icc in !LP64 |
aoqi@0 | 710 | inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
aoqi@0 | 711 | inline void brx( Condition c, bool a, Predict p, Label& L ); |
aoqi@0 | 712 | |
aoqi@0 | 713 | // unconditional branch |
aoqi@0 | 714 | inline void ba( Label& L ); |
aoqi@0 | 715 | |
aoqi@0 | 716 | // Branch that tests fp condition codes |
aoqi@0 | 717 | inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
aoqi@0 | 718 | inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); |
aoqi@0 | 719 | |
aoqi@0 | 720 | // get PC the best way |
aoqi@0 | 721 | inline int get_pc( Register d ); |
aoqi@0 | 722 | |
aoqi@0 | 723 | // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual) |
aoqi@0 | 724 | inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); } |
aoqi@0 | 725 | inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); } |
aoqi@0 | 726 | |
aoqi@0 | 727 | inline void jmp( Register s1, Register s2 ); |
aoqi@0 | 728 | inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); |
aoqi@0 | 729 | |
aoqi@0 | 730 | // Check if the call target is out of wdisp30 range (relative to the code cache) |
aoqi@0 | 731 | static inline bool is_far_target(address d); |
aoqi@0 | 732 | inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); |
aoqi@0 | 733 | inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); |
aoqi@0 | 734 | inline void callr( Register s1, Register s2 ); |
aoqi@0 | 735 | inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); |
aoqi@0 | 736 | |
aoqi@0 | 737 | // Emits nothing on V8 |
aoqi@0 | 738 | inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none ); |
aoqi@0 | 739 | inline void iprefetch( Label& L); |
aoqi@0 | 740 | |
aoqi@0 | 741 | inline void tst( Register s ) { orcc( G0, s, G0 ); } |
aoqi@0 | 742 | |
aoqi@0 | 743 | #ifdef PRODUCT |
aoqi@0 | 744 | inline void ret( bool trace = TraceJumps ) { if (trace) { |
aoqi@0 | 745 | mov(I7, O7); // traceable register |
aoqi@0 | 746 | JMP(O7, 2 * BytesPerInstWord); |
aoqi@0 | 747 | } else { |
aoqi@0 | 748 | jmpl( I7, 2 * BytesPerInstWord, G0 ); |
aoqi@0 | 749 | } |
aoqi@0 | 750 | } |
aoqi@0 | 751 | |
aoqi@0 | 752 | inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord); |
aoqi@0 | 753 | else jmpl( O7, 2 * BytesPerInstWord, G0 ); } |
aoqi@0 | 754 | #else |
aoqi@0 | 755 | void ret( bool trace = TraceJumps ); |
aoqi@0 | 756 | void retl( bool trace = TraceJumps ); |
aoqi@0 | 757 | #endif /* PRODUCT */ |
aoqi@0 | 758 | |
aoqi@0 | 759 | // Required platform-specific helpers for Label::patch_instructions. |
aoqi@0 | 760 | // They _shadow_ the declarations in AbstractAssembler, which are undefined. |
aoqi@0 | 761 | void pd_patch_instruction(address branch, address target); |
aoqi@0 | 762 | |
aoqi@0 | 763 | // sethi Macro handles optimizations and relocations |
aoqi@0 | 764 | private: |
aoqi@0 | 765 | void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable); |
aoqi@0 | 766 | public: |
aoqi@0 | 767 | void sethi(const AddressLiteral& addrlit, Register d); |
aoqi@0 | 768 | void patchable_sethi(const AddressLiteral& addrlit, Register d); |
aoqi@0 | 769 | |
aoqi@0 | 770 | // compute the number of instructions for a sethi/set |
aoqi@0 | 771 | static int insts_for_sethi( address a, bool worst_case = false ); |
aoqi@0 | 772 | static int worst_case_insts_for_set(); |
aoqi@0 | 773 | |
aoqi@0 | 774 | // set may be either setsw or setuw (high 32 bits may be zero or sign) |
aoqi@0 | 775 | private: |
aoqi@0 | 776 | void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable); |
aoqi@0 | 777 | static int insts_for_internal_set(intptr_t value); |
aoqi@0 | 778 | public: |
aoqi@0 | 779 | void set(const AddressLiteral& addrlit, Register d); |
aoqi@0 | 780 | void set(intptr_t value, Register d); |
aoqi@0 | 781 | void set(address addr, Register d, RelocationHolder const& rspec); |
aoqi@0 | 782 | static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); } |
aoqi@0 | 783 | |
aoqi@0 | 784 | void patchable_set(const AddressLiteral& addrlit, Register d); |
aoqi@0 | 785 | void patchable_set(intptr_t value, Register d); |
aoqi@0 | 786 | void set64(jlong value, Register d, Register tmp); |
aoqi@0 | 787 | static int insts_for_set64(jlong value); |
aoqi@0 | 788 | |
aoqi@0 | 789 | // sign-extend 32 to 64 |
aoqi@0 | 790 | inline void signx( Register s, Register d ) { sra( s, G0, d); } |
aoqi@0 | 791 | inline void signx( Register d ) { sra( d, G0, d); } |
aoqi@0 | 792 | |
aoqi@0 | 793 | inline void not1( Register s, Register d ) { xnor( s, G0, d ); } |
aoqi@0 | 794 | inline void not1( Register d ) { xnor( d, G0, d ); } |
aoqi@0 | 795 | |
aoqi@0 | 796 | inline void neg( Register s, Register d ) { sub( G0, s, d ); } |
aoqi@0 | 797 | inline void neg( Register d ) { sub( G0, d, d ); } |
aoqi@0 | 798 | |
aoqi@0 | 799 | inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); } |
aoqi@0 | 800 | inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); } |
aoqi@0 | 801 | // Functions for isolating 64 bit atomic swaps for LP64 |
aoqi@0 | 802 | // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's |
aoqi@0 | 803 | inline void cas_ptr( Register s1, Register s2, Register d) { |
aoqi@0 | 804 | #ifdef _LP64 |
aoqi@0 | 805 | casx( s1, s2, d ); |
aoqi@0 | 806 | #else |
aoqi@0 | 807 | cas( s1, s2, d ); |
aoqi@0 | 808 | #endif |
aoqi@0 | 809 | } |
aoqi@0 | 810 | |
aoqi@0 | 811 | // Functions for isolating 64 bit shifts for LP64 |
aoqi@0 | 812 | inline void sll_ptr( Register s1, Register s2, Register d ); |
aoqi@0 | 813 | inline void sll_ptr( Register s1, int imm6a, Register d ); |
aoqi@0 | 814 | inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 815 | inline void srl_ptr( Register s1, Register s2, Register d ); |
aoqi@0 | 816 | inline void srl_ptr( Register s1, int imm6a, Register d ); |
aoqi@0 | 817 | |
aoqi@0 | 818 | // little-endian |
aoqi@0 | 819 | inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); } |
aoqi@0 | 820 | inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); } |
aoqi@0 | 821 | |
aoqi@0 | 822 | inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); } |
aoqi@0 | 823 | inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); } |
aoqi@0 | 824 | |
aoqi@0 | 825 | inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); } |
aoqi@0 | 826 | inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); } |
aoqi@0 | 827 | |
aoqi@0 | 828 | using Assembler::add; |
aoqi@0 | 829 | inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype); |
aoqi@0 | 830 | inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec); |
aoqi@0 | 831 | inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0); |
aoqi@0 | 832 | inline void add(const Address& a, Register d, int offset = 0); |
aoqi@0 | 833 | |
aoqi@0 | 834 | using Assembler::andn; |
aoqi@0 | 835 | inline void andn( Register s1, RegisterOrConstant s2, Register d); |
aoqi@0 | 836 | |
aoqi@0 | 837 | inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); } |
aoqi@0 | 838 | inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); } |
aoqi@0 | 839 | |
aoqi@0 | 840 | inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); } |
aoqi@0 | 841 | inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); } |
aoqi@0 | 842 | |
aoqi@0 | 843 | inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); } |
aoqi@0 | 844 | inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); } |
aoqi@0 | 845 | |
aoqi@0 | 846 | inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); } |
aoqi@0 | 847 | inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); } |
aoqi@0 | 848 | |
aoqi@0 | 849 | inline void clr( Register d ) { or3( G0, G0, d ); } |
aoqi@0 | 850 | |
aoqi@0 | 851 | inline void clrb( Register s1, Register s2); |
aoqi@0 | 852 | inline void clrh( Register s1, Register s2); |
aoqi@0 | 853 | inline void clr( Register s1, Register s2); |
aoqi@0 | 854 | inline void clrx( Register s1, Register s2); |
aoqi@0 | 855 | |
aoqi@0 | 856 | inline void clrb( Register s1, int simm13a); |
aoqi@0 | 857 | inline void clrh( Register s1, int simm13a); |
aoqi@0 | 858 | inline void clr( Register s1, int simm13a); |
aoqi@0 | 859 | inline void clrx( Register s1, int simm13a); |
aoqi@0 | 860 | |
aoqi@0 | 861 | // copy & clear upper word |
aoqi@0 | 862 | inline void clruw( Register s, Register d ) { srl( s, G0, d); } |
aoqi@0 | 863 | // clear upper word |
aoqi@0 | 864 | inline void clruwu( Register d ) { srl( d, G0, d); } |
aoqi@0 | 865 | |
aoqi@0 | 866 | using Assembler::ldsb; |
aoqi@0 | 867 | using Assembler::ldsh; |
aoqi@0 | 868 | using Assembler::ldsw; |
aoqi@0 | 869 | using Assembler::ldub; |
aoqi@0 | 870 | using Assembler::lduh; |
aoqi@0 | 871 | using Assembler::lduw; |
aoqi@0 | 872 | using Assembler::ldx; |
aoqi@0 | 873 | using Assembler::ldd; |
aoqi@0 | 874 | |
aoqi@0 | 875 | #ifdef ASSERT |
aoqi@0 | 876 | // ByteSize is only a class when ASSERT is defined, otherwise it's an int. |
aoqi@0 | 877 | inline void ld(Register s1, ByteSize simm13a, Register d); |
aoqi@0 | 878 | #endif |
aoqi@0 | 879 | |
aoqi@0 | 880 | inline void ld(Register s1, Register s2, Register d); |
aoqi@0 | 881 | inline void ld(Register s1, int simm13a, Register d); |
aoqi@0 | 882 | |
aoqi@0 | 883 | inline void ldsb(const Address& a, Register d, int offset = 0); |
aoqi@0 | 884 | inline void ldsh(const Address& a, Register d, int offset = 0); |
aoqi@0 | 885 | inline void ldsw(const Address& a, Register d, int offset = 0); |
aoqi@0 | 886 | inline void ldub(const Address& a, Register d, int offset = 0); |
aoqi@0 | 887 | inline void lduh(const Address& a, Register d, int offset = 0); |
aoqi@0 | 888 | inline void lduw(const Address& a, Register d, int offset = 0); |
aoqi@0 | 889 | inline void ldx( const Address& a, Register d, int offset = 0); |
aoqi@0 | 890 | inline void ld( const Address& a, Register d, int offset = 0); |
aoqi@0 | 891 | inline void ldd( const Address& a, Register d, int offset = 0); |
aoqi@0 | 892 | |
aoqi@0 | 893 | inline void ldub(Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 894 | inline void ldsb(Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 895 | inline void lduh(Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 896 | inline void ldsh(Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 897 | inline void lduw(Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 898 | inline void ldsw(Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 899 | inline void ldx( Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 900 | inline void ld( Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 901 | inline void ldd( Register s1, RegisterOrConstant s2, Register d ); |
aoqi@0 | 902 | |
aoqi@0 | 903 | using Assembler::ldf; |
aoqi@0 | 904 | inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d); |
aoqi@0 | 905 | inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0); |
aoqi@0 | 906 | |
aoqi@0 | 907 | // membar psuedo instruction. takes into account target memory model. |
aoqi@0 | 908 | inline void membar( Assembler::Membar_mask_bits const7a ); |
aoqi@0 | 909 | |
aoqi@0 | 910 | // returns if membar generates anything. |
aoqi@0 | 911 | inline bool membar_has_effect( Assembler::Membar_mask_bits const7a ); |
aoqi@0 | 912 | |
aoqi@0 | 913 | // mov pseudo instructions |
aoqi@0 | 914 | inline void mov( Register s, Register d) { |
aoqi@0 | 915 | if ( s != d ) or3( G0, s, d); |
aoqi@0 | 916 | else assert_not_delayed(); // Put something useful in the delay slot! |
aoqi@0 | 917 | } |
aoqi@0 | 918 | |
aoqi@0 | 919 | inline void mov_or_nop( Register s, Register d) { |
aoqi@0 | 920 | if ( s != d ) or3( G0, s, d); |
aoqi@0 | 921 | else nop(); |
aoqi@0 | 922 | } |
aoqi@0 | 923 | |
aoqi@0 | 924 | inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); } |
aoqi@0 | 925 | |
aoqi@0 | 926 | using Assembler::prefetch; |
aoqi@0 | 927 | inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0); |
aoqi@0 | 928 | |
aoqi@0 | 929 | using Assembler::stb; |
aoqi@0 | 930 | using Assembler::sth; |
aoqi@0 | 931 | using Assembler::stw; |
aoqi@0 | 932 | using Assembler::stx; |
aoqi@0 | 933 | using Assembler::std; |
aoqi@0 | 934 | |
aoqi@0 | 935 | #ifdef ASSERT |
aoqi@0 | 936 | // ByteSize is only a class when ASSERT is defined, otherwise it's an int. |
aoqi@0 | 937 | inline void st(Register d, Register s1, ByteSize simm13a); |
aoqi@0 | 938 | #endif |
aoqi@0 | 939 | |
aoqi@0 | 940 | inline void st(Register d, Register s1, Register s2); |
aoqi@0 | 941 | inline void st(Register d, Register s1, int simm13a); |
aoqi@0 | 942 | |
aoqi@0 | 943 | inline void stb(Register d, const Address& a, int offset = 0 ); |
aoqi@0 | 944 | inline void sth(Register d, const Address& a, int offset = 0 ); |
aoqi@0 | 945 | inline void stw(Register d, const Address& a, int offset = 0 ); |
aoqi@0 | 946 | inline void stx(Register d, const Address& a, int offset = 0 ); |
aoqi@0 | 947 | inline void st( Register d, const Address& a, int offset = 0 ); |
aoqi@0 | 948 | inline void std(Register d, const Address& a, int offset = 0 ); |
aoqi@0 | 949 | |
aoqi@0 | 950 | inline void stb(Register d, Register s1, RegisterOrConstant s2 ); |
aoqi@0 | 951 | inline void sth(Register d, Register s1, RegisterOrConstant s2 ); |
aoqi@0 | 952 | inline void stw(Register d, Register s1, RegisterOrConstant s2 ); |
aoqi@0 | 953 | inline void stx(Register d, Register s1, RegisterOrConstant s2 ); |
aoqi@0 | 954 | inline void std(Register d, Register s1, RegisterOrConstant s2 ); |
aoqi@0 | 955 | inline void st( Register d, Register s1, RegisterOrConstant s2 ); |
aoqi@0 | 956 | |
aoqi@0 | 957 | using Assembler::stf; |
aoqi@0 | 958 | inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2); |
aoqi@0 | 959 | inline void stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0); |
aoqi@0 | 960 | |
aoqi@0 | 961 | // Note: offset is added to s2. |
aoqi@0 | 962 | using Assembler::sub; |
aoqi@0 | 963 | inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0); |
aoqi@0 | 964 | |
aoqi@0 | 965 | using Assembler::swap; |
aoqi@0 | 966 | inline void swap(const Address& a, Register d, int offset = 0); |
aoqi@0 | 967 | |
aoqi@0 | 968 | // address pseudos: make these names unlike instruction names to avoid confusion |
aoqi@0 | 969 | inline intptr_t load_pc_address( Register reg, int bytes_to_skip ); |
aoqi@0 | 970 | inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0); |
aoqi@0 | 971 | inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0); |
aoqi@0 | 972 | inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0); |
aoqi@0 | 973 | inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0); |
aoqi@0 | 974 | inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0); |
aoqi@0 | 975 | inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0); |
aoqi@0 | 976 | inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0); |
aoqi@0 | 977 | inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0); |
aoqi@0 | 978 | |
aoqi@0 | 979 | // ring buffer traceable jumps |
aoqi@0 | 980 | |
aoqi@0 | 981 | void jmp2( Register r1, Register r2, const char* file, int line ); |
aoqi@0 | 982 | void jmp ( Register r1, int offset, const char* file, int line ); |
aoqi@0 | 983 | |
aoqi@0 | 984 | void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line); |
aoqi@0 | 985 | void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line); |
aoqi@0 | 986 | |
aoqi@0 | 987 | |
aoqi@0 | 988 | // argument pseudos: |
aoqi@0 | 989 | |
aoqi@0 | 990 | inline void load_argument( Argument& a, Register d ); |
aoqi@0 | 991 | inline void store_argument( Register s, Argument& a ); |
aoqi@0 | 992 | inline void store_ptr_argument( Register s, Argument& a ); |
aoqi@0 | 993 | inline void store_float_argument( FloatRegister s, Argument& a ); |
aoqi@0 | 994 | inline void store_double_argument( FloatRegister s, Argument& a ); |
aoqi@0 | 995 | inline void store_long_argument( Register s, Argument& a ); |
aoqi@0 | 996 | |
aoqi@0 | 997 | // handy macros: |
aoqi@0 | 998 | |
aoqi@0 | 999 | inline void round_to( Register r, int modulus ) { |
aoqi@0 | 1000 | assert_not_delayed(); |
aoqi@0 | 1001 | inc( r, modulus - 1 ); |
aoqi@0 | 1002 | and3( r, -modulus, r ); |
aoqi@0 | 1003 | } |
aoqi@0 | 1004 | |
aoqi@0 | 1005 | // -------------------------------------------------- |
aoqi@0 | 1006 | |
aoqi@0 | 1007 | // Functions for isolating 64 bit loads for LP64 |
aoqi@0 | 1008 | // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's |
aoqi@0 | 1009 | // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's |
aoqi@0 | 1010 | inline void ld_ptr(Register s1, Register s2, Register d); |
aoqi@0 | 1011 | inline void ld_ptr(Register s1, int simm13a, Register d); |
aoqi@0 | 1012 | inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d); |
aoqi@0 | 1013 | inline void ld_ptr(const Address& a, Register d, int offset = 0); |
aoqi@0 | 1014 | inline void st_ptr(Register d, Register s1, Register s2); |
aoqi@0 | 1015 | inline void st_ptr(Register d, Register s1, int simm13a); |
aoqi@0 | 1016 | inline void st_ptr(Register d, Register s1, RegisterOrConstant s2); |
aoqi@0 | 1017 | inline void st_ptr(Register d, const Address& a, int offset = 0); |
aoqi@0 | 1018 | |
aoqi@0 | 1019 | #ifdef ASSERT |
aoqi@0 | 1020 | // ByteSize is only a class when ASSERT is defined, otherwise it's an int. |
aoqi@0 | 1021 | inline void ld_ptr(Register s1, ByteSize simm13a, Register d); |
aoqi@0 | 1022 | inline void st_ptr(Register d, Register s1, ByteSize simm13a); |
aoqi@0 | 1023 | #endif |
aoqi@0 | 1024 | |
aoqi@0 | 1025 | // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's |
aoqi@0 | 1026 | // st_long will perform std for 32 bit VM's and stx for 64 bit VM's |
aoqi@0 | 1027 | inline void ld_long(Register s1, Register s2, Register d); |
aoqi@0 | 1028 | inline void ld_long(Register s1, int simm13a, Register d); |
aoqi@0 | 1029 | inline void ld_long(Register s1, RegisterOrConstant s2, Register d); |
aoqi@0 | 1030 | inline void ld_long(const Address& a, Register d, int offset = 0); |
aoqi@0 | 1031 | inline void st_long(Register d, Register s1, Register s2); |
aoqi@0 | 1032 | inline void st_long(Register d, Register s1, int simm13a); |
aoqi@0 | 1033 | inline void st_long(Register d, Register s1, RegisterOrConstant s2); |
aoqi@0 | 1034 | inline void st_long(Register d, const Address& a, int offset = 0); |
aoqi@0 | 1035 | |
aoqi@0 | 1036 | // Helpers for address formation. |
aoqi@0 | 1037 | // - They emit only a move if s2 is a constant zero. |
aoqi@0 | 1038 | // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result. |
aoqi@0 | 1039 | // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant. |
aoqi@0 | 1040 | RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); |
aoqi@0 | 1041 | RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); |
aoqi@0 | 1042 | RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); |
aoqi@0 | 1043 | |
aoqi@0 | 1044 | RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) { |
aoqi@0 | 1045 | if (is_simm13(src.constant_or_zero())) |
aoqi@0 | 1046 | return src; // register or short constant |
aoqi@0 | 1047 | guarantee(temp != noreg, "constant offset overflow"); |
aoqi@0 | 1048 | set(src.as_constant(), temp); |
aoqi@0 | 1049 | return temp; |
aoqi@0 | 1050 | } |
aoqi@0 | 1051 | |
aoqi@0 | 1052 | // -------------------------------------------------- |
aoqi@0 | 1053 | |
aoqi@0 | 1054 | public: |
aoqi@0 | 1055 | // traps as per trap.h (SPARC ABI?) |
aoqi@0 | 1056 | |
aoqi@0 | 1057 | void breakpoint_trap(); |
aoqi@0 | 1058 | void breakpoint_trap(Condition c, CC cc); |
aoqi@0 | 1059 | |
aoqi@0 | 1060 | // Support for serializing memory accesses between threads |
aoqi@0 | 1061 | void serialize_memory(Register thread, Register tmp1, Register tmp2); |
aoqi@0 | 1062 | |
aoqi@0 | 1063 | // Stack frame creation/removal |
aoqi@0 | 1064 | void enter(); |
aoqi@0 | 1065 | void leave(); |
aoqi@0 | 1066 | |
aoqi@0 | 1067 | // Manipulation of C++ bools |
aoqi@0 | 1068 | // These are idioms to flag the need for care with accessing bools but on |
aoqi@0 | 1069 | // this platform we assume byte size |
aoqi@0 | 1070 | |
aoqi@0 | 1071 | inline void stbool(Register d, const Address& a) { stb(d, a); } |
aoqi@0 | 1072 | inline void ldbool(const Address& a, Register d) { ldub(a, d); } |
aoqi@0 | 1073 | inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); } |
aoqi@0 | 1074 | |
aoqi@0 | 1075 | // klass oop manipulations if compressed |
aoqi@0 | 1076 | void load_klass(Register src_oop, Register klass); |
aoqi@0 | 1077 | void store_klass(Register klass, Register dst_oop); |
aoqi@0 | 1078 | void store_klass_gap(Register s, Register dst_oop); |
aoqi@0 | 1079 | |
aoqi@0 | 1080 | // oop manipulations |
aoqi@0 | 1081 | void load_heap_oop(const Address& s, Register d); |
aoqi@0 | 1082 | void load_heap_oop(Register s1, Register s2, Register d); |
aoqi@0 | 1083 | void load_heap_oop(Register s1, int simm13a, Register d); |
aoqi@0 | 1084 | void load_heap_oop(Register s1, RegisterOrConstant s2, Register d); |
aoqi@0 | 1085 | void store_heap_oop(Register d, Register s1, Register s2); |
aoqi@0 | 1086 | void store_heap_oop(Register d, Register s1, int simm13a); |
aoqi@0 | 1087 | void store_heap_oop(Register d, const Address& a, int offset = 0); |
aoqi@0 | 1088 | |
aoqi@0 | 1089 | void encode_heap_oop(Register src, Register dst); |
aoqi@0 | 1090 | void encode_heap_oop(Register r) { |
aoqi@0 | 1091 | encode_heap_oop(r, r); |
aoqi@0 | 1092 | } |
aoqi@0 | 1093 | void decode_heap_oop(Register src, Register dst); |
aoqi@0 | 1094 | void decode_heap_oop(Register r) { |
aoqi@0 | 1095 | decode_heap_oop(r, r); |
aoqi@0 | 1096 | } |
aoqi@0 | 1097 | void encode_heap_oop_not_null(Register r); |
aoqi@0 | 1098 | void decode_heap_oop_not_null(Register r); |
aoqi@0 | 1099 | void encode_heap_oop_not_null(Register src, Register dst); |
aoqi@0 | 1100 | void decode_heap_oop_not_null(Register src, Register dst); |
aoqi@0 | 1101 | |
aoqi@0 | 1102 | void encode_klass_not_null(Register r); |
aoqi@0 | 1103 | void decode_klass_not_null(Register r); |
aoqi@0 | 1104 | void encode_klass_not_null(Register src, Register dst); |
aoqi@0 | 1105 | void decode_klass_not_null(Register src, Register dst); |
aoqi@0 | 1106 | |
aoqi@0 | 1107 | // Support for managing the JavaThread pointer (i.e.; the reference to |
aoqi@0 | 1108 | // thread-local information). |
aoqi@0 | 1109 | void get_thread(); // load G2_thread |
aoqi@0 | 1110 | void verify_thread(); // verify G2_thread contents |
aoqi@0 | 1111 | void save_thread (const Register threache); // save to cache |
aoqi@0 | 1112 | void restore_thread(const Register thread_cache); // restore from cache |
aoqi@0 | 1113 | |
aoqi@0 | 1114 | // Support for last Java frame (but use call_VM instead where possible) |
aoqi@0 | 1115 | void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); |
aoqi@0 | 1116 | void reset_last_Java_frame(void); |
aoqi@0 | 1117 | |
aoqi@0 | 1118 | // Call into the VM. |
aoqi@0 | 1119 | // Passes the thread pointer (in O0) as a prepended argument. |
aoqi@0 | 1120 | // Makes sure oop return values are visible to the GC. |
aoqi@0 | 1121 | void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
aoqi@0 | 1122 | void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); |
aoqi@0 | 1123 | void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
aoqi@0 | 1124 | void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
aoqi@0 | 1125 | |
aoqi@0 | 1126 | // these overloadings are not presently used on SPARC: |
aoqi@0 | 1127 | void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
aoqi@0 | 1128 | void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); |
aoqi@0 | 1129 | void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
aoqi@0 | 1130 | void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
aoqi@0 | 1131 | |
aoqi@0 | 1132 | void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0); |
aoqi@0 | 1133 | void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1); |
aoqi@0 | 1134 | void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2); |
aoqi@0 | 1135 | void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3); |
aoqi@0 | 1136 | |
aoqi@0 | 1137 | void get_vm_result (Register oop_result); |
aoqi@0 | 1138 | void get_vm_result_2(Register metadata_result); |
aoqi@0 | 1139 | |
aoqi@0 | 1140 | // vm result is currently getting hijacked to for oop preservation |
aoqi@0 | 1141 | void set_vm_result(Register oop_result); |
aoqi@0 | 1142 | |
aoqi@0 | 1143 | // Emit the CompiledIC call idiom |
aoqi@0 | 1144 | void ic_call(address entry, bool emit_delay = true); |
aoqi@0 | 1145 | |
aoqi@0 | 1146 | // if call_VM_base was called with check_exceptions=false, then call |
aoqi@0 | 1147 | // check_and_forward_exception to handle exceptions when it is safe |
aoqi@0 | 1148 | void check_and_forward_exception(Register scratch_reg); |
aoqi@0 | 1149 | |
aoqi@0 | 1150 | // Write to card table for - register is destroyed afterwards. |
aoqi@0 | 1151 | void card_table_write(jbyte* byte_map_base, Register tmp, Register obj); |
aoqi@0 | 1152 | |
aoqi@0 | 1153 | void card_write_barrier_post(Register store_addr, Register new_val, Register tmp); |
aoqi@0 | 1154 | |
aoqi@0 | 1155 | #if INCLUDE_ALL_GCS |
aoqi@0 | 1156 | // General G1 pre-barrier generator. |
aoqi@0 | 1157 | void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs); |
aoqi@0 | 1158 | |
aoqi@0 | 1159 | // General G1 post-barrier generator |
aoqi@0 | 1160 | void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp); |
aoqi@0 | 1161 | #endif // INCLUDE_ALL_GCS |
aoqi@0 | 1162 | |
aoqi@0 | 1163 | // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack |
aoqi@0 | 1164 | void push_fTOS(); |
aoqi@0 | 1165 | |
aoqi@0 | 1166 | // pops double TOS element from CPU stack and pushes on FPU stack |
aoqi@0 | 1167 | void pop_fTOS(); |
aoqi@0 | 1168 | |
aoqi@0 | 1169 | void empty_FPU_stack(); |
aoqi@0 | 1170 | |
aoqi@0 | 1171 | void push_IU_state(); |
aoqi@0 | 1172 | void pop_IU_state(); |
aoqi@0 | 1173 | |
aoqi@0 | 1174 | void push_FPU_state(); |
aoqi@0 | 1175 | void pop_FPU_state(); |
aoqi@0 | 1176 | |
aoqi@0 | 1177 | void push_CPU_state(); |
aoqi@0 | 1178 | void pop_CPU_state(); |
aoqi@0 | 1179 | |
aoqi@0 | 1180 | // Returns the byte size of the instructions generated by decode_klass_not_null(). |
aoqi@0 | 1181 | static int instr_size_for_decode_klass_not_null(); |
aoqi@0 | 1182 | |
aoqi@0 | 1183 | // if heap base register is used - reinit it with the correct value |
aoqi@0 | 1184 | void reinit_heapbase(); |
aoqi@0 | 1185 | |
aoqi@0 | 1186 | // Debugging |
aoqi@0 | 1187 | void _verify_oop(Register reg, const char * msg, const char * file, int line); |
aoqi@0 | 1188 | void _verify_oop_addr(Address addr, const char * msg, const char * file, int line); |
aoqi@0 | 1189 | |
aoqi@0 | 1190 | // TODO: verify_method and klass metadata (compare against vptr?) |
aoqi@0 | 1191 | void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} |
aoqi@0 | 1192 | void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} |
aoqi@0 | 1193 | |
aoqi@0 | 1194 | #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__) |
aoqi@0 | 1195 | #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__) |
aoqi@0 | 1196 | #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) |
aoqi@0 | 1197 | #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) |
aoqi@0 | 1198 | |
aoqi@0 | 1199 | // only if +VerifyOops |
aoqi@0 | 1200 | void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); |
aoqi@0 | 1201 | // only if +VerifyFPU |
aoqi@0 | 1202 | void stop(const char* msg); // prints msg, dumps registers and stops execution |
aoqi@0 | 1203 | void warn(const char* msg); // prints msg, but don't stop |
aoqi@0 | 1204 | void untested(const char* what = ""); |
aoqi@0 | 1205 | void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
aoqi@0 | 1206 | void should_not_reach_here() { stop("should not reach here"); } |
aoqi@0 | 1207 | void print_CPU_state(); |
aoqi@0 | 1208 | |
aoqi@0 | 1209 | // oops in code |
aoqi@0 | 1210 | AddressLiteral allocate_oop_address(jobject obj); // allocate_index |
aoqi@0 | 1211 | AddressLiteral constant_oop_address(jobject obj); // find_index |
aoqi@0 | 1212 | inline void set_oop (jobject obj, Register d); // uses allocate_oop_address |
aoqi@0 | 1213 | inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address |
aoqi@0 | 1214 | inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address |
aoqi@0 | 1215 | |
aoqi@0 | 1216 | // metadata in code that we have to keep track of |
aoqi@0 | 1217 | AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index |
aoqi@0 | 1218 | AddressLiteral constant_metadata_address(Metadata* obj); // find_index |
aoqi@0 | 1219 | inline void set_metadata (Metadata* obj, Register d); // uses allocate_metadata_address |
aoqi@0 | 1220 | inline void set_metadata_constant (Metadata* obj, Register d); // uses constant_metadata_address |
aoqi@0 | 1221 | inline void set_metadata (const AddressLiteral& obj_addr, Register d); // same as load_address |
aoqi@0 | 1222 | |
aoqi@0 | 1223 | void set_narrow_oop( jobject obj, Register d ); |
aoqi@0 | 1224 | void set_narrow_klass( Klass* k, Register d ); |
aoqi@0 | 1225 | |
aoqi@0 | 1226 | // nop padding |
aoqi@0 | 1227 | void align(int modulus); |
aoqi@0 | 1228 | |
aoqi@0 | 1229 | // declare a safepoint |
aoqi@0 | 1230 | void safepoint(); |
aoqi@0 | 1231 | |
aoqi@0 | 1232 | // factor out part of stop into subroutine to save space |
aoqi@0 | 1233 | void stop_subroutine(); |
aoqi@0 | 1234 | // factor out part of verify_oop into subroutine to save space |
aoqi@0 | 1235 | void verify_oop_subroutine(); |
aoqi@0 | 1236 | |
aoqi@0 | 1237 | // side-door communication with signalHandler in os_solaris.cpp |
aoqi@0 | 1238 | static address _verify_oop_implicit_branch[3]; |
aoqi@0 | 1239 | |
aoqi@0 | 1240 | int total_frame_size_in_bytes(int extraWords); |
aoqi@0 | 1241 | |
aoqi@0 | 1242 | // used when extraWords known statically |
aoqi@0 | 1243 | void save_frame(int extraWords = 0); |
aoqi@0 | 1244 | void save_frame_c1(int size_in_bytes); |
aoqi@0 | 1245 | // make a frame, and simultaneously pass up one or two register value |
aoqi@0 | 1246 | // into the new register window |
aoqi@0 | 1247 | void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register()); |
aoqi@0 | 1248 | |
aoqi@0 | 1249 | // give no. (outgoing) params, calc # of words will need on frame |
aoqi@0 | 1250 | void calc_mem_param_words(Register Rparam_words, Register Rresult); |
aoqi@0 | 1251 | |
aoqi@0 | 1252 | // used to calculate frame size dynamically |
aoqi@0 | 1253 | // result is in bytes and must be negated for save inst |
aoqi@0 | 1254 | void calc_frame_size(Register extraWords, Register resultReg); |
aoqi@0 | 1255 | |
aoqi@0 | 1256 | // calc and also save |
aoqi@0 | 1257 | void calc_frame_size_and_save(Register extraWords, Register resultReg); |
aoqi@0 | 1258 | |
aoqi@0 | 1259 | static void debug(char* msg, RegistersForDebugging* outWindow); |
aoqi@0 | 1260 | |
aoqi@0 | 1261 | // implementations of bytecodes used by both interpreter and compiler |
aoqi@0 | 1262 | |
aoqi@0 | 1263 | void lcmp( Register Ra_hi, Register Ra_low, |
aoqi@0 | 1264 | Register Rb_hi, Register Rb_low, |
aoqi@0 | 1265 | Register Rresult); |
aoqi@0 | 1266 | |
aoqi@0 | 1267 | void lneg( Register Rhi, Register Rlow ); |
aoqi@0 | 1268 | |
aoqi@0 | 1269 | void lshl( Register Rin_high, Register Rin_low, Register Rcount, |
aoqi@0 | 1270 | Register Rout_high, Register Rout_low, Register Rtemp ); |
aoqi@0 | 1271 | |
aoqi@0 | 1272 | void lshr( Register Rin_high, Register Rin_low, Register Rcount, |
aoqi@0 | 1273 | Register Rout_high, Register Rout_low, Register Rtemp ); |
aoqi@0 | 1274 | |
aoqi@0 | 1275 | void lushr( Register Rin_high, Register Rin_low, Register Rcount, |
aoqi@0 | 1276 | Register Rout_high, Register Rout_low, Register Rtemp ); |
aoqi@0 | 1277 | |
aoqi@0 | 1278 | #ifdef _LP64 |
aoqi@0 | 1279 | void lcmp( Register Ra, Register Rb, Register Rresult); |
aoqi@0 | 1280 | #endif |
aoqi@0 | 1281 | |
aoqi@0 | 1282 | // Load and store values by size and signed-ness |
aoqi@0 | 1283 | void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed); |
aoqi@0 | 1284 | void store_sized_value(Register src, Address dst, size_t size_in_bytes); |
aoqi@0 | 1285 | |
aoqi@0 | 1286 | void float_cmp( bool is_float, int unordered_result, |
aoqi@0 | 1287 | FloatRegister Fa, FloatRegister Fb, |
aoqi@0 | 1288 | Register Rresult); |
aoqi@0 | 1289 | |
aoqi@0 | 1290 | void save_all_globals_into_locals(); |
aoqi@0 | 1291 | void restore_globals_from_locals(); |
aoqi@0 | 1292 | |
aoqi@0 | 1293 | // These set the icc condition code to equal if the lock succeeded |
aoqi@0 | 1294 | // and notEqual if it failed and requires a slow case |
aoqi@0 | 1295 | void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, |
aoqi@0 | 1296 | Register Rscratch, |
aoqi@0 | 1297 | BiasedLockingCounters* counters = NULL, |
aoqi@0 | 1298 | bool try_bias = UseBiasedLocking); |
aoqi@0 | 1299 | void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, |
aoqi@0 | 1300 | Register Rscratch, |
aoqi@0 | 1301 | bool try_bias = UseBiasedLocking); |
aoqi@0 | 1302 | |
aoqi@0 | 1303 | // Biased locking support |
aoqi@0 | 1304 | // Upon entry, lock_reg must point to the lock record on the stack, |
aoqi@0 | 1305 | // obj_reg must contain the target object, and mark_reg must contain |
aoqi@0 | 1306 | // the target object's header. |
aoqi@0 | 1307 | // Destroys mark_reg if an attempt is made to bias an anonymously |
aoqi@0 | 1308 | // biased lock. In this case a failure will go either to the slow |
aoqi@0 | 1309 | // case or fall through with the notEqual condition code set with |
aoqi@0 | 1310 | // the expectation that the slow case in the runtime will be called. |
aoqi@0 | 1311 | // In the fall-through case where the CAS-based lock is done, |
aoqi@0 | 1312 | // mark_reg is not destroyed. |
aoqi@0 | 1313 | void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, |
aoqi@0 | 1314 | Label& done, Label* slow_case = NULL, |
aoqi@0 | 1315 | BiasedLockingCounters* counters = NULL); |
aoqi@0 | 1316 | // Upon entry, the base register of mark_addr must contain the oop. |
aoqi@0 | 1317 | // Destroys temp_reg. |
aoqi@0 | 1318 | |
aoqi@0 | 1319 | // If allow_delay_slot_filling is set to true, the next instruction |
aoqi@0 | 1320 | // emitted after this one will go in an annulled delay slot if the |
aoqi@0 | 1321 | // biased locking exit case failed. |
aoqi@0 | 1322 | void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false); |
aoqi@0 | 1323 | |
aoqi@0 | 1324 | // allocation |
aoqi@0 | 1325 | void eden_allocate( |
aoqi@0 | 1326 | Register obj, // result: pointer to object after successful allocation |
aoqi@0 | 1327 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
aoqi@0 | 1328 | int con_size_in_bytes, // object size in bytes if known at compile time |
aoqi@0 | 1329 | Register t1, // temp register |
aoqi@0 | 1330 | Register t2, // temp register |
aoqi@0 | 1331 | Label& slow_case // continuation point if fast allocation fails |
aoqi@0 | 1332 | ); |
aoqi@0 | 1333 | void tlab_allocate( |
aoqi@0 | 1334 | Register obj, // result: pointer to object after successful allocation |
aoqi@0 | 1335 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
aoqi@0 | 1336 | int con_size_in_bytes, // object size in bytes if known at compile time |
aoqi@0 | 1337 | Register t1, // temp register |
aoqi@0 | 1338 | Label& slow_case // continuation point if fast allocation fails |
aoqi@0 | 1339 | ); |
aoqi@0 | 1340 | void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); |
aoqi@0 | 1341 | void incr_allocated_bytes(RegisterOrConstant size_in_bytes, |
aoqi@0 | 1342 | Register t1, Register t2); |
aoqi@0 | 1343 | |
aoqi@0 | 1344 | // interface method calling |
aoqi@0 | 1345 | void lookup_interface_method(Register recv_klass, |
aoqi@0 | 1346 | Register intf_klass, |
aoqi@0 | 1347 | RegisterOrConstant itable_index, |
aoqi@0 | 1348 | Register method_result, |
aoqi@0 | 1349 | Register temp_reg, Register temp2_reg, |
aoqi@0 | 1350 | Label& no_such_interface); |
aoqi@0 | 1351 | |
aoqi@0 | 1352 | // virtual method calling |
aoqi@0 | 1353 | void lookup_virtual_method(Register recv_klass, |
aoqi@0 | 1354 | RegisterOrConstant vtable_index, |
aoqi@0 | 1355 | Register method_result); |
aoqi@0 | 1356 | |
aoqi@0 | 1357 | // Test sub_klass against super_klass, with fast and slow paths. |
aoqi@0 | 1358 | |
aoqi@0 | 1359 | // The fast path produces a tri-state answer: yes / no / maybe-slow. |
aoqi@0 | 1360 | // One of the three labels can be NULL, meaning take the fall-through. |
aoqi@0 | 1361 | // If super_check_offset is -1, the value is loaded up from super_klass. |
aoqi@0 | 1362 | // No registers are killed, except temp_reg and temp2_reg. |
aoqi@0 | 1363 | // If super_check_offset is not -1, temp2_reg is not used and can be noreg. |
aoqi@0 | 1364 | void check_klass_subtype_fast_path(Register sub_klass, |
aoqi@0 | 1365 | Register super_klass, |
aoqi@0 | 1366 | Register temp_reg, |
aoqi@0 | 1367 | Register temp2_reg, |
aoqi@0 | 1368 | Label* L_success, |
aoqi@0 | 1369 | Label* L_failure, |
aoqi@0 | 1370 | Label* L_slow_path, |
aoqi@0 | 1371 | RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
aoqi@0 | 1372 | |
aoqi@0 | 1373 | // The rest of the type check; must be wired to a corresponding fast path. |
aoqi@0 | 1374 | // It does not repeat the fast path logic, so don't use it standalone. |
aoqi@0 | 1375 | // The temp_reg can be noreg, if no temps are available. |
aoqi@0 | 1376 | // It can also be sub_klass or super_klass, meaning it's OK to kill that one. |
aoqi@0 | 1377 | // Updates the sub's secondary super cache as necessary. |
aoqi@0 | 1378 | void check_klass_subtype_slow_path(Register sub_klass, |
aoqi@0 | 1379 | Register super_klass, |
aoqi@0 | 1380 | Register temp_reg, |
aoqi@0 | 1381 | Register temp2_reg, |
aoqi@0 | 1382 | Register temp3_reg, |
aoqi@0 | 1383 | Register temp4_reg, |
aoqi@0 | 1384 | Label* L_success, |
aoqi@0 | 1385 | Label* L_failure); |
aoqi@0 | 1386 | |
aoqi@0 | 1387 | // Simplified, combined version, good for typical uses. |
aoqi@0 | 1388 | // Falls through on failure. |
aoqi@0 | 1389 | void check_klass_subtype(Register sub_klass, |
aoqi@0 | 1390 | Register super_klass, |
aoqi@0 | 1391 | Register temp_reg, |
aoqi@0 | 1392 | Register temp2_reg, |
aoqi@0 | 1393 | Label& L_success); |
aoqi@0 | 1394 | |
aoqi@0 | 1395 | // method handles (JSR 292) |
aoqi@0 | 1396 | // offset relative to Gargs of argument at tos[arg_slot]. |
aoqi@0 | 1397 | // (arg_slot == 0 means the last argument, not the first). |
aoqi@0 | 1398 | RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, |
aoqi@0 | 1399 | Register temp_reg, |
aoqi@0 | 1400 | int extra_slot_offset = 0); |
aoqi@0 | 1401 | // Address of Gargs and argument_offset. |
aoqi@0 | 1402 | Address argument_address(RegisterOrConstant arg_slot, |
aoqi@0 | 1403 | Register temp_reg = noreg, |
aoqi@0 | 1404 | int extra_slot_offset = 0); |
aoqi@0 | 1405 | |
aoqi@0 | 1406 | // Stack overflow checking |
aoqi@0 | 1407 | |
aoqi@0 | 1408 | // Note: this clobbers G3_scratch |
aoqi@0 | 1409 | void bang_stack_with_offset(int offset) { |
aoqi@0 | 1410 | // stack grows down, caller passes positive offset |
aoqi@0 | 1411 | assert(offset > 0, "must bang with negative offset"); |
aoqi@0 | 1412 | set((-offset)+STACK_BIAS, G3_scratch); |
aoqi@0 | 1413 | st(G0, SP, G3_scratch); |
aoqi@0 | 1414 | } |
aoqi@0 | 1415 | |
aoqi@0 | 1416 | // Writes to stack successive pages until offset reached to check for |
aoqi@0 | 1417 | // stack overflow + shadow pages. Clobbers tsp and scratch registers. |
aoqi@0 | 1418 | void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch); |
aoqi@0 | 1419 | |
aoqi@0 | 1420 | virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset); |
aoqi@0 | 1421 | |
aoqi@0 | 1422 | void verify_tlab(); |
aoqi@0 | 1423 | |
aoqi@0 | 1424 | Condition negate_condition(Condition cond); |
aoqi@0 | 1425 | |
aoqi@0 | 1426 | // Helper functions for statistics gathering. |
aoqi@0 | 1427 | // Conditionally (non-atomically) increments passed counter address, preserving condition codes. |
aoqi@0 | 1428 | void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2); |
aoqi@0 | 1429 | // Unconditional increment. |
aoqi@0 | 1430 | void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2); |
aoqi@0 | 1431 | void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2); |
aoqi@0 | 1432 | |
aoqi@0 | 1433 | // Compare char[] arrays aligned to 4 bytes. |
aoqi@0 | 1434 | void char_arrays_equals(Register ary1, Register ary2, |
aoqi@0 | 1435 | Register limit, Register result, |
aoqi@0 | 1436 | Register chr1, Register chr2, Label& Ldone); |
aoqi@0 | 1437 | // Use BIS for zeroing |
aoqi@0 | 1438 | void bis_zeroing(Register to, Register count, Register temp, Label& Ldone); |
aoqi@0 | 1439 | |
aoqi@0 | 1440 | #undef VIRTUAL |
aoqi@0 | 1441 | }; |
aoqi@0 | 1442 | |
aoqi@0 | 1443 | /** |
aoqi@0 | 1444 | * class SkipIfEqual: |
aoqi@0 | 1445 | * |
aoqi@0 | 1446 | * Instantiating this class will result in assembly code being output that will |
aoqi@0 | 1447 | * jump around any code emitted between the creation of the instance and it's |
aoqi@0 | 1448 | * automatic destruction at the end of a scope block, depending on the value of |
aoqi@0 | 1449 | * the flag passed to the constructor, which will be checked at run-time. |
aoqi@0 | 1450 | */ |
aoqi@0 | 1451 | class SkipIfEqual : public StackObj { |
aoqi@0 | 1452 | private: |
aoqi@0 | 1453 | MacroAssembler* _masm; |
aoqi@0 | 1454 | Label _label; |
aoqi@0 | 1455 | |
aoqi@0 | 1456 | public: |
aoqi@0 | 1457 | // 'temp' is a temp register that this object can use (and trash) |
aoqi@0 | 1458 | SkipIfEqual(MacroAssembler*, Register temp, |
aoqi@0 | 1459 | const bool* flag_addr, Assembler::Condition condition); |
aoqi@0 | 1460 | ~SkipIfEqual(); |
aoqi@0 | 1461 | }; |
aoqi@0 | 1462 | |
aoqi@0 | 1463 | #endif // CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP |