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src/os_cpu/bsd_x86/vm/bsd_x86_64.ad@e961c11b85fe (annotated)

src/os_cpu/bsd_x86/vm/bsd_x86_64.ad

Wed, 03 Apr 2013 11:12:57 -0700

author

kvn

date

Wed, 03 Apr 2013 11:12:57 -0700

changeset 4873

e961c11b85fe

parent 3577

9b8ce46870df

permissions

-rw-r--r--

8011102: Clear AVX registers after return from JNI call
Summary: Execute vzeroupper instruction after JNI call and on exits in jit compiled code which use 256bit vectors.
Reviewed-by: roland

never@3156	1	//
kvn@3577	2	// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
never@3156	3	// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
never@3156	4	//
never@3156	5	// This code is free software; you can redistribute it and/or modify it
never@3156	6	// under the terms of the GNU General Public License version 2 only, as
never@3156	7	// published by the Free Software Foundation.
never@3156	8	//
never@3156	9	// This code is distributed in the hope that it will be useful, but WITHOUT
never@3156	10	// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
never@3156	11	// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
never@3156	12	// version 2 for more details (a copy is included in the LICENSE file that
never@3156	13	// accompanied this code).
never@3156	14	//
never@3156	15	// You should have received a copy of the GNU General Public License version
never@3156	16	// 2 along with this work; if not, write to the Free Software Foundation,
never@3156	17	// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
never@3156	18	//
never@3156	19	// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
never@3156	20	// or visit www.oracle.com if you need additional information or have any
never@3156	21	// questions.
never@3156	22	//
never@3156	23	//
never@3156	24
never@3156	25	// AMD64 Bsd Architecture Description File
never@3156	26
never@3156	27	//----------OS-DEPENDENT ENCODING BLOCK----------------------------------------
never@3156	28	// This block specifies the encoding classes used by the compiler to
never@3156	29	// output byte streams. Encoding classes generate functions which are
never@3156	30	// called by Machine Instruction Nodes in order to generate the bit
never@3156	31	// encoding of the instruction. Operands specify their base encoding
never@3156	32	// interface with the interface keyword. There are currently
never@3156	33	// supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
never@3156	34	// COND_INTER. REG_INTER causes an operand to generate a function
never@3156	35	// which returns its register number when queried. CONST_INTER causes
never@3156	36	// an operand to generate a function which returns the value of the
never@3156	37	// constant when queried. MEMORY_INTER causes an operand to generate
never@3156	38	// four functions which return the Base Register, the Index Register,
never@3156	39	// the Scale Value, and the Offset Value of the operand when queried.
never@3156	40	// COND_INTER causes an operand to generate six functions which return
never@3156	41	// the encoding code (ie - encoding bits for the instruction)
never@3156	42	// associated with each basic boolean condition for a conditional
never@3156	43	// instruction. Instructions specify two basic values for encoding.
never@3156	44	// They use the ins_encode keyword to specify their encoding class
never@3156	45	// (which must be one of the class names specified in the encoding
never@3156	46	// block), and they use the opcode keyword to specify, in order, their
never@3156	47	// primary, secondary, and tertiary opcode. Only the opcode sections
never@3156	48	// which a particular instruction needs for encoding need to be
never@3156	49	// specified.
never@3156	50	encode %{
never@3156	51	// Build emit functions for each basic byte or larger field in the intel
never@3156	52	// encoding scheme (opcode, rm, sib, immediate), and call them from C++
never@3156	53	// code in the enc_class source block. Emit functions will live in the
never@3156	54	// main source block for now. In future, we can generalize this by
never@3156	55	// adding a syntax that specifies the sizes of fields in an order,
never@3156	56	// so that the adlc can build the emit functions automagically
never@3156	57
never@3156	58	%}
never@3156	59
never@3156	60
never@3156	61	// Platform dependent source
never@3156	62
kvn@3577	63	source %{
never@3156	64
never@3156	65	%}