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src/cpu/x86/vm/globals_x86.hpp@e8260b6328fb (annotated)

src/cpu/x86/vm/globals_x86.hpp

Fri, 29 May 2015 10:58:45 +0200

author

zmajo

date

Fri, 29 May 2015 10:58:45 +0200

changeset 7854

e8260b6328fb

parent 7152

166d744df0de

child 7994

04ff2f6cd0eb

child 9834

bb1da64b0492

permissions

-rw-r--r--

8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
Summary: Introduce the PreserveFramePointer flag to control if RBP is used as the frame pointer or as a general purpose register.
Reviewed-by: kvn, roland, dlong, enevill, shade

duke@435	1	/*
minqi@5274	2	* Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
trims@1907	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907	20	* or visit www.oracle.com if you need additional information or have any
trims@1907	21	* questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
stefank@2314	25	#ifndef CPU_X86_VM_GLOBALS_X86_HPP
stefank@2314	26	#define CPU_X86_VM_GLOBALS_X86_HPP
stefank@2314	27
stefank@2314	28	#include "utilities/globalDefinitions.hpp"
stefank@2314	29	#include "utilities/macros.hpp"
stefank@2314	30
duke@435	31	// Sets the default values for platform dependent flags used by the runtime system.
duke@435	32	// (see globals.hpp)
duke@435	33
phh@1499	34	define_pd_global(bool, ConvertSleepToYield, true);
phh@1499	35	define_pd_global(bool, ShareVtableStubs, true);
phh@1499	36	define_pd_global(bool, CountInterpCalls, true);
phh@1499	37	define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this
duke@435	38
phh@1499	39	define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks
goetz@6490	40	define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86.
goetz@6490	41	define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast
duke@435	42
duke@435	43	// See 4827828 for this change. There is no globals_core_i486.hpp. I can't
duke@435	44	// assign a different value for C2 without touching a number of files. Use
duke@435	45	// #ifdef to minimize the change as it's late in Mantis. -- FIXME.
duke@435	46	// c1 doesn't have this problem because the fix to 4858033 assures us
duke@435	47	// the the vep is aligned at CodeEntryAlignment whereas c2 only aligns
duke@435	48	// the uep and the vep doesn't get real alignment but just slops on by
duke@435	49	// only assured that the entry instruction meets the 5 byte size requirement.
duke@435	50	#ifdef COMPILER2
phh@1499	51	define_pd_global(intx, CodeEntryAlignment, 32);
duke@435	52	#else
phh@1499	53	define_pd_global(intx, CodeEntryAlignment, 16);
duke@435	54	#endif // COMPILER2
kvn@1800	55	define_pd_global(intx, OptoLoopAlignment, 16);
phh@1499	56	define_pd_global(intx, InlineFrequencyCount, 100);
phh@1499	57	define_pd_global(intx, InlineSmallCode, 1000);
duke@435	58
minqi@5274	59	define_pd_global(intx, StackYellowPages, NOT_WINDOWS(2) WINDOWS_ONLY(3));
phh@1499	60	define_pd_global(intx, StackRedPages, 1);
duke@435	61	#ifdef AMD64
duke@435	62	// Very large C++ stack frames using solaris-amd64 optimized builds
duke@435	63	// due to lack of optimization caused by C++ compiler bugs
coleenp@3548	64	define_pd_global(intx, StackShadowPages, NOT_WIN64(20) WIN64_ONLY(6) DEBUG_ONLY(+2));
duke@435	65	#else
never@3569	66	define_pd_global(intx, StackShadowPages, 4 DEBUG_ONLY(+5));
duke@435	67	#endif // AMD64
duke@435	68
phh@1499	69	define_pd_global(intx, PreInflateSpin, 10);
duke@435	70
duke@435	71	define_pd_global(bool, RewriteBytecodes, true);
duke@435	72	define_pd_global(bool, RewriteFrequentPairs, true);
bobv@2223	73
never@3156	74	#ifdef _ALLBSD_SOURCE
never@3156	75	define_pd_global(bool, UseMembar, true);
never@3156	76	#else
bobv@2223	77	define_pd_global(bool, UseMembar, false);
never@3156	78	#endif
stefank@2314	79
ysr@2650	80	// GC Ergo Flags
tschatzl@5119	81	define_pd_global(uintx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread
twisti@4020	82
roland@5987	83	define_pd_global(uintx, TypeProfileLevel, 111);
roland@5914	84
zmajo@7854	85	define_pd_global(bool, PreserveFramePointer, false);
zmajo@7854	86
twisti@4020	87	#define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \
twisti@4020	88	\
twisti@4020	89	develop(bool, IEEEPrecision, true, \
twisti@4020	90	"Enables IEEE precision (for INTEL only)") \
twisti@4020	91	\
twisti@4020	92	product(intx, FenceInstruction, 0, \
twisti@4020	93	"(Unsafe,Unstable) Experimental") \
twisti@4020	94	\
twisti@4020	95	product(intx, ReadPrefetchInstr, 0, \
twisti@4020	96	"Prefetch instruction to prefetch ahead") \
twisti@4020	97	\
twisti@4020	98	product(bool, UseStoreImmI16, true, \
twisti@4020	99	"Use store immediate 16-bits value instruction on x86") \
twisti@4020	100	\
twisti@4020	101	product(intx, UseAVX, 99, \
twisti@4020	102	"Highest supported AVX instructions set on x86/x64") \
twisti@4020	103	\
drchase@5353	104	product(bool, UseCLMUL, false, \
drchase@5353	105	"Control whether CLMUL instructions can be used on x86/x64") \
drchase@5353	106	\
twisti@4020	107	diagnostic(bool, UseIncDec, true, \
twisti@4020	108	"Use INC, DEC instructions on x86") \
twisti@4020	109	\
twisti@4020	110	product(bool, UseNewLongLShift, false, \
twisti@4020	111	"Use optimized bitwise shift left") \
twisti@4020	112	\
twisti@4020	113	product(bool, UseAddressNop, false, \
twisti@4020	114	"Use '0F 1F [addr]' NOP instructions on x86 cpus") \
twisti@4020	115	\
twisti@4020	116	product(bool, UseXmmLoadAndClearUpper, true, \
twisti@4020	117	"Load low part of XMM register and clear upper part") \
twisti@4020	118	\
twisti@4020	119	product(bool, UseXmmRegToRegMoveAll, false, \
twisti@4020	120	"Copy all XMM register bits when moving value between registers") \
twisti@4020	121	\
twisti@4020	122	product(bool, UseXmmI2D, false, \
twisti@4020	123	"Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \
twisti@4020	124	\
twisti@4020	125	product(bool, UseXmmI2F, false, \
twisti@4020	126	"Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \
twisti@4020	127	\
twisti@4020	128	product(bool, UseUnalignedLoadStores, false, \
twisti@4020	129	"Use SSE2 MOVDQU instruction for Arraycopy") \
twisti@4020	130	\
kvn@4410	131	product(bool, UseFastStosb, false, \
kvn@4410	132	"Use fast-string operation for zeroing: rep stosb") \
kvn@4410	133	\
kvn@6429	134	/* Use Restricted Transactional Memory for lock eliding */ \
kvn@6998	135	product(bool, UseRTMLocking, false, \
kvn@6429	136	"Enable RTM lock eliding for inflated locks in compiled code") \
kvn@6429	137	\
kvn@6429	138	experimental(bool, UseRTMForStackLocks, false, \
kvn@6429	139	"Enable RTM lock eliding for stack locks in compiled code") \
kvn@6429	140	\
kvn@6998	141	product(bool, UseRTMDeopt, false, \
kvn@6429	142	"Perform deopt and recompilation based on RTM abort ratio") \
kvn@6429	143	\
kvn@6998	144	product(uintx, RTMRetryCount, 5, \
kvn@6429	145	"Number of RTM retries on lock abort or busy") \
kvn@6429	146	\
kvn@6429	147	experimental(intx, RTMSpinLoopCount, 100, \
kvn@6429	148	"Spin count for lock to become free before RTM retry") \
kvn@6429	149	\
kvn@6429	150	experimental(intx, RTMAbortThreshold, 1000, \
kvn@6429	151	"Calculate abort ratio after this number of aborts") \
kvn@6429	152	\
kvn@6429	153	experimental(intx, RTMLockingThreshold, 10000, \
kvn@6429	154	"Lock count at which to do RTM lock eliding without " \
kvn@6429	155	"abort ratio calculation") \
kvn@6429	156	\
kvn@6429	157	experimental(intx, RTMAbortRatio, 50, \
kvn@6429	158	"Lock abort ratio at which to stop use RTM lock eliding") \
kvn@6429	159	\
kvn@6429	160	experimental(intx, RTMTotalCountIncrRate, 64, \
kvn@6429	161	"Increment total RTM attempted lock count once every n times") \
kvn@6429	162	\
kvn@6429	163	experimental(intx, RTMLockingCalculationDelay, 0, \
kvn@6429	164	"Number of milliseconds to wait before start calculating aborts " \
kvn@6429	165	"for RTM locking") \
kvn@6429	166	\
kvn@6557	167	experimental(bool, UseRTMXendForLockBusy, true, \
kvn@6429	168	"Use RTM Xend instead of Xabort when lock busy") \
kvn@6429	169	\
twisti@4020	170	/* assembler */ \
twisti@4020	171	product(bool, Use486InstrsOnly, false, \
twisti@4020	172	"Use 80486 Compliant instruction subset") \
twisti@4020	173	\
twisti@4020	174	product(bool, UseCountLeadingZerosInstruction, false, \
twisti@4020	175	"Use count leading zeros instruction") \
iveresov@6378	176	\
iveresov@6378	177	product(bool, UseCountTrailingZerosInstruction, false, \
iveresov@6378	178	"Use count trailing zeros instruction") \
iveresov@6378	179	\
iveresov@6378	180	product(bool, UseBMI1Instructions, false, \
kvn@7152	181	"Use BMI1 instructions") \
kvn@7152	182	\
kvn@7152	183	product(bool, UseBMI2Instructions, false, \
kvn@7152	184	"Use BMI2 instructions")
stefank@2314	185	#endif // CPU_X86_VM_GLOBALS_X86_HPP