Wed, 08 Apr 2009 10:56:49 -0700
6655638: dynamic languages need method handles
Summary: initial implementation, with known omissions (x86/64, sparc, compiler optim., c-oops, C++ interp.)
Reviewed-by: kvn, twisti, never
duke@435 | 1 | /* |
jrose@1100 | 2 | * Copyright 2000-2009 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | # include "incls/_precompiled.incl" |
duke@435 | 26 | # include "incls/_c1_LIRAssembler_sparc.cpp.incl" |
duke@435 | 27 | |
duke@435 | 28 | #define __ _masm-> |
duke@435 | 29 | |
duke@435 | 30 | |
duke@435 | 31 | //------------------------------------------------------------ |
duke@435 | 32 | |
duke@435 | 33 | |
duke@435 | 34 | bool LIR_Assembler::is_small_constant(LIR_Opr opr) { |
duke@435 | 35 | if (opr->is_constant()) { |
duke@435 | 36 | LIR_Const* constant = opr->as_constant_ptr(); |
duke@435 | 37 | switch (constant->type()) { |
duke@435 | 38 | case T_INT: { |
duke@435 | 39 | jint value = constant->as_jint(); |
duke@435 | 40 | return Assembler::is_simm13(value); |
duke@435 | 41 | } |
duke@435 | 42 | |
duke@435 | 43 | default: |
duke@435 | 44 | return false; |
duke@435 | 45 | } |
duke@435 | 46 | } |
duke@435 | 47 | return false; |
duke@435 | 48 | } |
duke@435 | 49 | |
duke@435 | 50 | |
duke@435 | 51 | bool LIR_Assembler::is_single_instruction(LIR_Op* op) { |
duke@435 | 52 | switch (op->code()) { |
duke@435 | 53 | case lir_null_check: |
duke@435 | 54 | return true; |
duke@435 | 55 | |
duke@435 | 56 | |
duke@435 | 57 | case lir_add: |
duke@435 | 58 | case lir_ushr: |
duke@435 | 59 | case lir_shr: |
duke@435 | 60 | case lir_shl: |
duke@435 | 61 | // integer shifts and adds are always one instruction |
duke@435 | 62 | return op->result_opr()->is_single_cpu(); |
duke@435 | 63 | |
duke@435 | 64 | |
duke@435 | 65 | case lir_move: { |
duke@435 | 66 | LIR_Op1* op1 = op->as_Op1(); |
duke@435 | 67 | LIR_Opr src = op1->in_opr(); |
duke@435 | 68 | LIR_Opr dst = op1->result_opr(); |
duke@435 | 69 | |
duke@435 | 70 | if (src == dst) { |
duke@435 | 71 | NEEDS_CLEANUP; |
duke@435 | 72 | // this works around a problem where moves with the same src and dst |
duke@435 | 73 | // end up in the delay slot and then the assembler swallows the mov |
duke@435 | 74 | // since it has no effect and then it complains because the delay slot |
duke@435 | 75 | // is empty. returning false stops the optimizer from putting this in |
duke@435 | 76 | // the delay slot |
duke@435 | 77 | return false; |
duke@435 | 78 | } |
duke@435 | 79 | |
duke@435 | 80 | // don't put moves involving oops into the delay slot since the VerifyOops code |
duke@435 | 81 | // will make it much larger than a single instruction. |
duke@435 | 82 | if (VerifyOops) { |
duke@435 | 83 | return false; |
duke@435 | 84 | } |
duke@435 | 85 | |
duke@435 | 86 | if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || |
duke@435 | 87 | ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { |
duke@435 | 88 | return false; |
duke@435 | 89 | } |
duke@435 | 90 | |
duke@435 | 91 | if (dst->is_register()) { |
duke@435 | 92 | if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { |
duke@435 | 93 | return !PatchALot; |
duke@435 | 94 | } else if (src->is_single_stack()) { |
duke@435 | 95 | return true; |
duke@435 | 96 | } |
duke@435 | 97 | } |
duke@435 | 98 | |
duke@435 | 99 | if (src->is_register()) { |
duke@435 | 100 | if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { |
duke@435 | 101 | return !PatchALot; |
duke@435 | 102 | } else if (dst->is_single_stack()) { |
duke@435 | 103 | return true; |
duke@435 | 104 | } |
duke@435 | 105 | } |
duke@435 | 106 | |
duke@435 | 107 | if (dst->is_register() && |
duke@435 | 108 | ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || |
duke@435 | 109 | (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { |
duke@435 | 110 | return true; |
duke@435 | 111 | } |
duke@435 | 112 | |
duke@435 | 113 | return false; |
duke@435 | 114 | } |
duke@435 | 115 | |
duke@435 | 116 | default: |
duke@435 | 117 | return false; |
duke@435 | 118 | } |
duke@435 | 119 | ShouldNotReachHere(); |
duke@435 | 120 | } |
duke@435 | 121 | |
duke@435 | 122 | |
duke@435 | 123 | LIR_Opr LIR_Assembler::receiverOpr() { |
duke@435 | 124 | return FrameMap::O0_oop_opr; |
duke@435 | 125 | } |
duke@435 | 126 | |
duke@435 | 127 | |
duke@435 | 128 | LIR_Opr LIR_Assembler::incomingReceiverOpr() { |
duke@435 | 129 | return FrameMap::I0_oop_opr; |
duke@435 | 130 | } |
duke@435 | 131 | |
duke@435 | 132 | |
duke@435 | 133 | LIR_Opr LIR_Assembler::osrBufferPointer() { |
duke@435 | 134 | return FrameMap::I0_opr; |
duke@435 | 135 | } |
duke@435 | 136 | |
duke@435 | 137 | |
duke@435 | 138 | int LIR_Assembler::initial_frame_size_in_bytes() { |
duke@435 | 139 | return in_bytes(frame_map()->framesize_in_bytes()); |
duke@435 | 140 | } |
duke@435 | 141 | |
duke@435 | 142 | |
duke@435 | 143 | // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); |
duke@435 | 144 | // we fetch the class of the receiver (O0) and compare it with the cached class. |
duke@435 | 145 | // If they do not match we jump to slow case. |
duke@435 | 146 | int LIR_Assembler::check_icache() { |
duke@435 | 147 | int offset = __ offset(); |
duke@435 | 148 | __ inline_cache_check(O0, G5_inline_cache_reg); |
duke@435 | 149 | return offset; |
duke@435 | 150 | } |
duke@435 | 151 | |
duke@435 | 152 | |
duke@435 | 153 | void LIR_Assembler::osr_entry() { |
duke@435 | 154 | // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): |
duke@435 | 155 | // |
duke@435 | 156 | // 1. Create a new compiled activation. |
duke@435 | 157 | // 2. Initialize local variables in the compiled activation. The expression stack must be empty |
duke@435 | 158 | // at the osr_bci; it is not initialized. |
duke@435 | 159 | // 3. Jump to the continuation address in compiled code to resume execution. |
duke@435 | 160 | |
duke@435 | 161 | // OSR entry point |
duke@435 | 162 | offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); |
duke@435 | 163 | BlockBegin* osr_entry = compilation()->hir()->osr_entry(); |
duke@435 | 164 | ValueStack* entry_state = osr_entry->end()->state(); |
duke@435 | 165 | int number_of_locks = entry_state->locks_size(); |
duke@435 | 166 | |
duke@435 | 167 | // Create a frame for the compiled activation. |
duke@435 | 168 | __ build_frame(initial_frame_size_in_bytes()); |
duke@435 | 169 | |
duke@435 | 170 | // OSR buffer is |
duke@435 | 171 | // |
duke@435 | 172 | // locals[nlocals-1..0] |
duke@435 | 173 | // monitors[number_of_locks-1..0] |
duke@435 | 174 | // |
duke@435 | 175 | // locals is a direct copy of the interpreter frame so in the osr buffer |
duke@435 | 176 | // so first slot in the local array is the last local from the interpreter |
duke@435 | 177 | // and last slot is local[0] (receiver) from the interpreter |
duke@435 | 178 | // |
duke@435 | 179 | // Similarly with locks. The first lock slot in the osr buffer is the nth lock |
duke@435 | 180 | // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock |
duke@435 | 181 | // in the interpreter frame (the method lock if a sync method) |
duke@435 | 182 | |
duke@435 | 183 | // Initialize monitors in the compiled activation. |
duke@435 | 184 | // I0: pointer to osr buffer |
duke@435 | 185 | // |
duke@435 | 186 | // All other registers are dead at this point and the locals will be |
duke@435 | 187 | // copied into place by code emitted in the IR. |
duke@435 | 188 | |
duke@435 | 189 | Register OSR_buf = osrBufferPointer()->as_register(); |
duke@435 | 190 | { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
duke@435 | 191 | int monitor_offset = BytesPerWord * method()->max_locals() + |
duke@435 | 192 | (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); |
duke@435 | 193 | for (int i = 0; i < number_of_locks; i++) { |
duke@435 | 194 | int slot_offset = monitor_offset - ((i * BasicObjectLock::size()) * BytesPerWord); |
duke@435 | 195 | #ifdef ASSERT |
duke@435 | 196 | // verify the interpreter's monitor has a non-null object |
duke@435 | 197 | { |
duke@435 | 198 | Label L; |
duke@435 | 199 | __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7); |
duke@435 | 200 | __ cmp(G0, O7); |
duke@435 | 201 | __ br(Assembler::notEqual, false, Assembler::pt, L); |
duke@435 | 202 | __ delayed()->nop(); |
duke@435 | 203 | __ stop("locked object is NULL"); |
duke@435 | 204 | __ bind(L); |
duke@435 | 205 | } |
duke@435 | 206 | #endif // ASSERT |
duke@435 | 207 | // Copy the lock field into the compiled activation. |
duke@435 | 208 | __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::lock_offset_in_bytes()), O7); |
duke@435 | 209 | __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); |
duke@435 | 210 | __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7); |
duke@435 | 211 | __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); |
duke@435 | 212 | } |
duke@435 | 213 | } |
duke@435 | 214 | } |
duke@435 | 215 | |
duke@435 | 216 | |
duke@435 | 217 | // Optimized Library calls |
duke@435 | 218 | // This is the fast version of java.lang.String.compare; it has not |
duke@435 | 219 | // OSR-entry and therefore, we generate a slow version for OSR's |
duke@435 | 220 | void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { |
duke@435 | 221 | Register str0 = left->as_register(); |
duke@435 | 222 | Register str1 = right->as_register(); |
duke@435 | 223 | |
duke@435 | 224 | Label Ldone; |
duke@435 | 225 | |
duke@435 | 226 | Register result = dst->as_register(); |
duke@435 | 227 | { |
duke@435 | 228 | // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0 |
duke@435 | 229 | // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1 |
duke@435 | 230 | // Also, get string0.count-string1.count in o7 and get the condition code set |
duke@435 | 231 | // Note: some instructions have been hoisted for better instruction scheduling |
duke@435 | 232 | |
duke@435 | 233 | Register tmp0 = L0; |
duke@435 | 234 | Register tmp1 = L1; |
duke@435 | 235 | Register tmp2 = L2; |
duke@435 | 236 | |
duke@435 | 237 | int value_offset = java_lang_String:: value_offset_in_bytes(); // char array |
duke@435 | 238 | int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position |
duke@435 | 239 | int count_offset = java_lang_String:: count_offset_in_bytes(); |
duke@435 | 240 | |
duke@435 | 241 | __ ld_ptr(Address(str0, 0, value_offset), tmp0); |
duke@435 | 242 | __ ld(Address(str0, 0, offset_offset), tmp2); |
duke@435 | 243 | __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); |
duke@435 | 244 | __ ld(Address(str0, 0, count_offset), str0); |
duke@435 | 245 | __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); |
duke@435 | 246 | |
duke@435 | 247 | // str1 may be null |
duke@435 | 248 | add_debug_info_for_null_check_here(info); |
duke@435 | 249 | |
duke@435 | 250 | __ ld_ptr(Address(str1, 0, value_offset), tmp1); |
duke@435 | 251 | __ add(tmp0, tmp2, tmp0); |
duke@435 | 252 | |
duke@435 | 253 | __ ld(Address(str1, 0, offset_offset), tmp2); |
duke@435 | 254 | __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); |
duke@435 | 255 | __ ld(Address(str1, 0, count_offset), str1); |
duke@435 | 256 | __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); |
duke@435 | 257 | __ subcc(str0, str1, O7); |
duke@435 | 258 | __ add(tmp1, tmp2, tmp1); |
duke@435 | 259 | } |
duke@435 | 260 | |
duke@435 | 261 | { |
duke@435 | 262 | // Compute the minimum of the string lengths, scale it and store it in limit |
duke@435 | 263 | Register count0 = I0; |
duke@435 | 264 | Register count1 = I1; |
duke@435 | 265 | Register limit = L3; |
duke@435 | 266 | |
duke@435 | 267 | Label Lskip; |
duke@435 | 268 | __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter |
duke@435 | 269 | __ br(Assembler::greater, true, Assembler::pt, Lskip); |
duke@435 | 270 | __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter |
duke@435 | 271 | __ bind(Lskip); |
duke@435 | 272 | |
duke@435 | 273 | // If either string is empty (or both of them) the result is the difference in lengths |
duke@435 | 274 | __ cmp(limit, 0); |
duke@435 | 275 | __ br(Assembler::equal, true, Assembler::pn, Ldone); |
duke@435 | 276 | __ delayed()->mov(O7, result); // result is difference in lengths |
duke@435 | 277 | } |
duke@435 | 278 | |
duke@435 | 279 | { |
duke@435 | 280 | // Neither string is empty |
duke@435 | 281 | Label Lloop; |
duke@435 | 282 | |
duke@435 | 283 | Register base0 = L0; |
duke@435 | 284 | Register base1 = L1; |
duke@435 | 285 | Register chr0 = I0; |
duke@435 | 286 | Register chr1 = I1; |
duke@435 | 287 | Register limit = L3; |
duke@435 | 288 | |
duke@435 | 289 | // Shift base0 and base1 to the end of the arrays, negate limit |
duke@435 | 290 | __ add(base0, limit, base0); |
duke@435 | 291 | __ add(base1, limit, base1); |
duke@435 | 292 | __ neg(limit); // limit = -min{string0.count, strin1.count} |
duke@435 | 293 | |
duke@435 | 294 | __ lduh(base0, limit, chr0); |
duke@435 | 295 | __ bind(Lloop); |
duke@435 | 296 | __ lduh(base1, limit, chr1); |
duke@435 | 297 | __ subcc(chr0, chr1, chr0); |
duke@435 | 298 | __ br(Assembler::notZero, false, Assembler::pn, Ldone); |
duke@435 | 299 | assert(chr0 == result, "result must be pre-placed"); |
duke@435 | 300 | __ delayed()->inccc(limit, sizeof(jchar)); |
duke@435 | 301 | __ br(Assembler::notZero, true, Assembler::pt, Lloop); |
duke@435 | 302 | __ delayed()->lduh(base0, limit, chr0); |
duke@435 | 303 | } |
duke@435 | 304 | |
duke@435 | 305 | // If strings are equal up to min length, return the length difference. |
duke@435 | 306 | __ mov(O7, result); |
duke@435 | 307 | |
duke@435 | 308 | // Otherwise, return the difference between the first mismatched chars. |
duke@435 | 309 | __ bind(Ldone); |
duke@435 | 310 | } |
duke@435 | 311 | |
duke@435 | 312 | |
duke@435 | 313 | // -------------------------------------------------------------------------------------------- |
duke@435 | 314 | |
duke@435 | 315 | void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { |
duke@435 | 316 | if (!GenerateSynchronizationCode) return; |
duke@435 | 317 | |
duke@435 | 318 | Register obj_reg = obj_opr->as_register(); |
duke@435 | 319 | Register lock_reg = lock_opr->as_register(); |
duke@435 | 320 | |
duke@435 | 321 | Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); |
duke@435 | 322 | Register reg = mon_addr.base(); |
duke@435 | 323 | int offset = mon_addr.disp(); |
duke@435 | 324 | // compute pointer to BasicLock |
duke@435 | 325 | if (mon_addr.is_simm13()) { |
duke@435 | 326 | __ add(reg, offset, lock_reg); |
duke@435 | 327 | } |
duke@435 | 328 | else { |
duke@435 | 329 | __ set(offset, lock_reg); |
duke@435 | 330 | __ add(reg, lock_reg, lock_reg); |
duke@435 | 331 | } |
duke@435 | 332 | // unlock object |
duke@435 | 333 | MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); |
duke@435 | 334 | // _slow_case_stubs->append(slow_case); |
duke@435 | 335 | // temporary fix: must be created after exceptionhandler, therefore as call stub |
duke@435 | 336 | _slow_case_stubs->append(slow_case); |
duke@435 | 337 | if (UseFastLocking) { |
duke@435 | 338 | // try inlined fast unlocking first, revert to slow locking if it fails |
duke@435 | 339 | // note: lock_reg points to the displaced header since the displaced header offset is 0! |
duke@435 | 340 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 341 | __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); |
duke@435 | 342 | } else { |
duke@435 | 343 | // always do slow unlocking |
duke@435 | 344 | // note: the slow unlocking code could be inlined here, however if we use |
duke@435 | 345 | // slow unlocking, speed doesn't matter anyway and this solution is |
duke@435 | 346 | // simpler and requires less duplicated code - additionally, the |
duke@435 | 347 | // slow unlocking code is the same in either case which simplifies |
duke@435 | 348 | // debugging |
duke@435 | 349 | __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); |
duke@435 | 350 | __ delayed()->nop(); |
duke@435 | 351 | } |
duke@435 | 352 | // done |
duke@435 | 353 | __ bind(*slow_case->continuation()); |
duke@435 | 354 | } |
duke@435 | 355 | |
duke@435 | 356 | |
duke@435 | 357 | void LIR_Assembler::emit_exception_handler() { |
duke@435 | 358 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 359 | // is coming at the end after block reordering) the return address |
duke@435 | 360 | // must still point into the code area in order to avoid assertion |
duke@435 | 361 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 362 | // (was bug 5/14/1999 - gri) |
duke@435 | 363 | __ nop(); |
duke@435 | 364 | |
duke@435 | 365 | // generate code for exception handler |
duke@435 | 366 | ciMethod* method = compilation()->method(); |
duke@435 | 367 | |
duke@435 | 368 | address handler_base = __ start_a_stub(exception_handler_size); |
duke@435 | 369 | |
duke@435 | 370 | if (handler_base == NULL) { |
duke@435 | 371 | // not enough space left for the handler |
duke@435 | 372 | bailout("exception handler overflow"); |
duke@435 | 373 | return; |
duke@435 | 374 | } |
duke@435 | 375 | #ifdef ASSERT |
duke@435 | 376 | int offset = code_offset(); |
duke@435 | 377 | #endif // ASSERT |
duke@435 | 378 | compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset()); |
duke@435 | 379 | |
duke@435 | 380 | |
duke@435 | 381 | if (compilation()->has_exception_handlers() || JvmtiExport::can_post_exceptions()) { |
duke@435 | 382 | __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); |
duke@435 | 383 | __ delayed()->nop(); |
duke@435 | 384 | } |
duke@435 | 385 | |
duke@435 | 386 | __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); |
duke@435 | 387 | __ delayed()->nop(); |
duke@435 | 388 | debug_only(__ stop("should have gone to the caller");) |
duke@435 | 389 | assert(code_offset() - offset <= exception_handler_size, "overflow"); |
duke@435 | 390 | |
duke@435 | 391 | __ end_a_stub(); |
duke@435 | 392 | } |
duke@435 | 393 | |
duke@435 | 394 | void LIR_Assembler::emit_deopt_handler() { |
duke@435 | 395 | // if the last instruction is a call (typically to do a throw which |
duke@435 | 396 | // is coming at the end after block reordering) the return address |
duke@435 | 397 | // must still point into the code area in order to avoid assertion |
duke@435 | 398 | // failures when searching for the corresponding bci => add a nop |
duke@435 | 399 | // (was bug 5/14/1999 - gri) |
duke@435 | 400 | __ nop(); |
duke@435 | 401 | |
duke@435 | 402 | // generate code for deopt handler |
duke@435 | 403 | ciMethod* method = compilation()->method(); |
duke@435 | 404 | address handler_base = __ start_a_stub(deopt_handler_size); |
duke@435 | 405 | if (handler_base == NULL) { |
duke@435 | 406 | // not enough space left for the handler |
duke@435 | 407 | bailout("deopt handler overflow"); |
duke@435 | 408 | return; |
duke@435 | 409 | } |
duke@435 | 410 | #ifdef ASSERT |
duke@435 | 411 | int offset = code_offset(); |
duke@435 | 412 | #endif // ASSERT |
duke@435 | 413 | compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset()); |
duke@435 | 414 | |
duke@435 | 415 | Address deopt_blob(G3_scratch, SharedRuntime::deopt_blob()->unpack()); |
duke@435 | 416 | |
duke@435 | 417 | __ JUMP(deopt_blob, 0); // sethi;jmp |
duke@435 | 418 | __ delayed()->nop(); |
duke@435 | 419 | |
duke@435 | 420 | assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
duke@435 | 421 | |
duke@435 | 422 | debug_only(__ stop("should have gone to the caller");) |
duke@435 | 423 | |
duke@435 | 424 | __ end_a_stub(); |
duke@435 | 425 | } |
duke@435 | 426 | |
duke@435 | 427 | |
duke@435 | 428 | void LIR_Assembler::jobject2reg(jobject o, Register reg) { |
duke@435 | 429 | if (o == NULL) { |
duke@435 | 430 | __ set(NULL_WORD, reg); |
duke@435 | 431 | } else { |
duke@435 | 432 | int oop_index = __ oop_recorder()->find_index(o); |
duke@435 | 433 | RelocationHolder rspec = oop_Relocation::spec(oop_index); |
duke@435 | 434 | __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created |
duke@435 | 435 | } |
duke@435 | 436 | } |
duke@435 | 437 | |
duke@435 | 438 | |
duke@435 | 439 | void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { |
duke@435 | 440 | // Allocate a new index in oop table to hold the oop once it's been patched |
duke@435 | 441 | int oop_index = __ oop_recorder()->allocate_index((jobject)NULL); |
duke@435 | 442 | PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index); |
duke@435 | 443 | |
duke@435 | 444 | Address addr = Address(reg, address(NULL), oop_Relocation::spec(oop_index)); |
duke@435 | 445 | assert(addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); |
duke@435 | 446 | // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the |
duke@435 | 447 | // NULL will be dynamically patched later and the patched value may be large. We must |
duke@435 | 448 | // therefore generate the sethi/add as a placeholders |
duke@435 | 449 | __ sethi(addr, true); |
duke@435 | 450 | __ add(addr, reg, 0); |
duke@435 | 451 | |
duke@435 | 452 | patching_epilog(patch, lir_patch_normal, reg, info); |
duke@435 | 453 | } |
duke@435 | 454 | |
duke@435 | 455 | |
duke@435 | 456 | void LIR_Assembler::emit_op3(LIR_Op3* op) { |
duke@435 | 457 | Register Rdividend = op->in_opr1()->as_register(); |
duke@435 | 458 | Register Rdivisor = noreg; |
duke@435 | 459 | Register Rscratch = op->in_opr3()->as_register(); |
duke@435 | 460 | Register Rresult = op->result_opr()->as_register(); |
duke@435 | 461 | int divisor = -1; |
duke@435 | 462 | |
duke@435 | 463 | if (op->in_opr2()->is_register()) { |
duke@435 | 464 | Rdivisor = op->in_opr2()->as_register(); |
duke@435 | 465 | } else { |
duke@435 | 466 | divisor = op->in_opr2()->as_constant_ptr()->as_jint(); |
duke@435 | 467 | assert(Assembler::is_simm13(divisor), "can only handle simm13"); |
duke@435 | 468 | } |
duke@435 | 469 | |
duke@435 | 470 | assert(Rdividend != Rscratch, ""); |
duke@435 | 471 | assert(Rdivisor != Rscratch, ""); |
duke@435 | 472 | assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); |
duke@435 | 473 | |
duke@435 | 474 | if (Rdivisor == noreg && is_power_of_2(divisor)) { |
duke@435 | 475 | // convert division by a power of two into some shifts and logical operations |
duke@435 | 476 | if (op->code() == lir_idiv) { |
duke@435 | 477 | if (divisor == 2) { |
duke@435 | 478 | __ srl(Rdividend, 31, Rscratch); |
duke@435 | 479 | } else { |
duke@435 | 480 | __ sra(Rdividend, 31, Rscratch); |
duke@435 | 481 | __ and3(Rscratch, divisor - 1, Rscratch); |
duke@435 | 482 | } |
duke@435 | 483 | __ add(Rdividend, Rscratch, Rscratch); |
duke@435 | 484 | __ sra(Rscratch, log2_intptr(divisor), Rresult); |
duke@435 | 485 | return; |
duke@435 | 486 | } else { |
duke@435 | 487 | if (divisor == 2) { |
duke@435 | 488 | __ srl(Rdividend, 31, Rscratch); |
duke@435 | 489 | } else { |
duke@435 | 490 | __ sra(Rdividend, 31, Rscratch); |
duke@435 | 491 | __ and3(Rscratch, divisor - 1,Rscratch); |
duke@435 | 492 | } |
duke@435 | 493 | __ add(Rdividend, Rscratch, Rscratch); |
duke@435 | 494 | __ andn(Rscratch, divisor - 1,Rscratch); |
duke@435 | 495 | __ sub(Rdividend, Rscratch, Rresult); |
duke@435 | 496 | return; |
duke@435 | 497 | } |
duke@435 | 498 | } |
duke@435 | 499 | |
duke@435 | 500 | __ sra(Rdividend, 31, Rscratch); |
duke@435 | 501 | __ wry(Rscratch); |
duke@435 | 502 | if (!VM_Version::v9_instructions_work()) { |
duke@435 | 503 | // v9 doesn't require these nops |
duke@435 | 504 | __ nop(); |
duke@435 | 505 | __ nop(); |
duke@435 | 506 | __ nop(); |
duke@435 | 507 | __ nop(); |
duke@435 | 508 | } |
duke@435 | 509 | |
duke@435 | 510 | add_debug_info_for_div0_here(op->info()); |
duke@435 | 511 | |
duke@435 | 512 | if (Rdivisor != noreg) { |
duke@435 | 513 | __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); |
duke@435 | 514 | } else { |
duke@435 | 515 | assert(Assembler::is_simm13(divisor), "can only handle simm13"); |
duke@435 | 516 | __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); |
duke@435 | 517 | } |
duke@435 | 518 | |
duke@435 | 519 | Label skip; |
duke@435 | 520 | __ br(Assembler::overflowSet, true, Assembler::pn, skip); |
duke@435 | 521 | __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); |
duke@435 | 522 | __ bind(skip); |
duke@435 | 523 | |
duke@435 | 524 | if (op->code() == lir_irem) { |
duke@435 | 525 | if (Rdivisor != noreg) { |
duke@435 | 526 | __ smul(Rscratch, Rdivisor, Rscratch); |
duke@435 | 527 | } else { |
duke@435 | 528 | __ smul(Rscratch, divisor, Rscratch); |
duke@435 | 529 | } |
duke@435 | 530 | __ sub(Rdividend, Rscratch, Rresult); |
duke@435 | 531 | } |
duke@435 | 532 | } |
duke@435 | 533 | |
duke@435 | 534 | |
duke@435 | 535 | void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { |
duke@435 | 536 | #ifdef ASSERT |
duke@435 | 537 | assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); |
duke@435 | 538 | if (op->block() != NULL) _branch_target_blocks.append(op->block()); |
duke@435 | 539 | if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); |
duke@435 | 540 | #endif |
duke@435 | 541 | assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); |
duke@435 | 542 | |
duke@435 | 543 | if (op->cond() == lir_cond_always) { |
duke@435 | 544 | __ br(Assembler::always, false, Assembler::pt, *(op->label())); |
duke@435 | 545 | } else if (op->code() == lir_cond_float_branch) { |
duke@435 | 546 | assert(op->ublock() != NULL, "must have unordered successor"); |
duke@435 | 547 | bool is_unordered = (op->ublock() == op->block()); |
duke@435 | 548 | Assembler::Condition acond; |
duke@435 | 549 | switch (op->cond()) { |
duke@435 | 550 | case lir_cond_equal: acond = Assembler::f_equal; break; |
duke@435 | 551 | case lir_cond_notEqual: acond = Assembler::f_notEqual; break; |
duke@435 | 552 | case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; |
duke@435 | 553 | case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; |
duke@435 | 554 | case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; |
duke@435 | 555 | case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; |
duke@435 | 556 | default : ShouldNotReachHere(); |
duke@435 | 557 | }; |
duke@435 | 558 | |
duke@435 | 559 | if (!VM_Version::v9_instructions_work()) { |
duke@435 | 560 | __ nop(); |
duke@435 | 561 | } |
duke@435 | 562 | __ fb( acond, false, Assembler::pn, *(op->label())); |
duke@435 | 563 | } else { |
duke@435 | 564 | assert (op->code() == lir_branch, "just checking"); |
duke@435 | 565 | |
duke@435 | 566 | Assembler::Condition acond; |
duke@435 | 567 | switch (op->cond()) { |
duke@435 | 568 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 569 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 570 | case lir_cond_less: acond = Assembler::less; break; |
duke@435 | 571 | case lir_cond_lessEqual: acond = Assembler::lessEqual; break; |
duke@435 | 572 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; |
duke@435 | 573 | case lir_cond_greater: acond = Assembler::greater; break; |
duke@435 | 574 | case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; |
duke@435 | 575 | case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; |
duke@435 | 576 | default: ShouldNotReachHere(); |
duke@435 | 577 | }; |
duke@435 | 578 | |
duke@435 | 579 | // sparc has different condition codes for testing 32-bit |
duke@435 | 580 | // vs. 64-bit values. We could always test xcc is we could |
duke@435 | 581 | // guarantee that 32-bit loads always sign extended but that isn't |
duke@435 | 582 | // true and since sign extension isn't free, it would impose a |
duke@435 | 583 | // slight cost. |
duke@435 | 584 | #ifdef _LP64 |
duke@435 | 585 | if (op->type() == T_INT) { |
duke@435 | 586 | __ br(acond, false, Assembler::pn, *(op->label())); |
duke@435 | 587 | } else |
duke@435 | 588 | #endif |
duke@435 | 589 | __ brx(acond, false, Assembler::pn, *(op->label())); |
duke@435 | 590 | } |
duke@435 | 591 | // The peephole pass fills the delay slot |
duke@435 | 592 | } |
duke@435 | 593 | |
duke@435 | 594 | |
duke@435 | 595 | void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { |
duke@435 | 596 | Bytecodes::Code code = op->bytecode(); |
duke@435 | 597 | LIR_Opr dst = op->result_opr(); |
duke@435 | 598 | |
duke@435 | 599 | switch(code) { |
duke@435 | 600 | case Bytecodes::_i2l: { |
duke@435 | 601 | Register rlo = dst->as_register_lo(); |
duke@435 | 602 | Register rhi = dst->as_register_hi(); |
duke@435 | 603 | Register rval = op->in_opr()->as_register(); |
duke@435 | 604 | #ifdef _LP64 |
duke@435 | 605 | __ sra(rval, 0, rlo); |
duke@435 | 606 | #else |
duke@435 | 607 | __ mov(rval, rlo); |
duke@435 | 608 | __ sra(rval, BitsPerInt-1, rhi); |
duke@435 | 609 | #endif |
duke@435 | 610 | break; |
duke@435 | 611 | } |
duke@435 | 612 | case Bytecodes::_i2d: |
duke@435 | 613 | case Bytecodes::_i2f: { |
duke@435 | 614 | bool is_double = (code == Bytecodes::_i2d); |
duke@435 | 615 | FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); |
duke@435 | 616 | FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; |
duke@435 | 617 | FloatRegister rsrc = op->in_opr()->as_float_reg(); |
duke@435 | 618 | if (rsrc != rdst) { |
duke@435 | 619 | __ fmov(FloatRegisterImpl::S, rsrc, rdst); |
duke@435 | 620 | } |
duke@435 | 621 | __ fitof(w, rdst, rdst); |
duke@435 | 622 | break; |
duke@435 | 623 | } |
duke@435 | 624 | case Bytecodes::_f2i:{ |
duke@435 | 625 | FloatRegister rsrc = op->in_opr()->as_float_reg(); |
duke@435 | 626 | Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); |
duke@435 | 627 | Label L; |
duke@435 | 628 | // result must be 0 if value is NaN; test by comparing value to itself |
duke@435 | 629 | __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); |
duke@435 | 630 | if (!VM_Version::v9_instructions_work()) { |
duke@435 | 631 | __ nop(); |
duke@435 | 632 | } |
duke@435 | 633 | __ fb(Assembler::f_unordered, true, Assembler::pn, L); |
duke@435 | 634 | __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN |
duke@435 | 635 | __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); |
duke@435 | 636 | // move integer result from float register to int register |
duke@435 | 637 | __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); |
duke@435 | 638 | __ bind (L); |
duke@435 | 639 | break; |
duke@435 | 640 | } |
duke@435 | 641 | case Bytecodes::_l2i: { |
duke@435 | 642 | Register rlo = op->in_opr()->as_register_lo(); |
duke@435 | 643 | Register rhi = op->in_opr()->as_register_hi(); |
duke@435 | 644 | Register rdst = dst->as_register(); |
duke@435 | 645 | #ifdef _LP64 |
duke@435 | 646 | __ sra(rlo, 0, rdst); |
duke@435 | 647 | #else |
duke@435 | 648 | __ mov(rlo, rdst); |
duke@435 | 649 | #endif |
duke@435 | 650 | break; |
duke@435 | 651 | } |
duke@435 | 652 | case Bytecodes::_d2f: |
duke@435 | 653 | case Bytecodes::_f2d: { |
duke@435 | 654 | bool is_double = (code == Bytecodes::_f2d); |
duke@435 | 655 | assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); |
duke@435 | 656 | LIR_Opr val = op->in_opr(); |
duke@435 | 657 | FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); |
duke@435 | 658 | FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); |
duke@435 | 659 | FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; |
duke@435 | 660 | FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; |
duke@435 | 661 | __ ftof(vw, dw, rval, rdst); |
duke@435 | 662 | break; |
duke@435 | 663 | } |
duke@435 | 664 | case Bytecodes::_i2s: |
duke@435 | 665 | case Bytecodes::_i2b: { |
duke@435 | 666 | Register rval = op->in_opr()->as_register(); |
duke@435 | 667 | Register rdst = dst->as_register(); |
duke@435 | 668 | int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); |
duke@435 | 669 | __ sll (rval, shift, rdst); |
duke@435 | 670 | __ sra (rdst, shift, rdst); |
duke@435 | 671 | break; |
duke@435 | 672 | } |
duke@435 | 673 | case Bytecodes::_i2c: { |
duke@435 | 674 | Register rval = op->in_opr()->as_register(); |
duke@435 | 675 | Register rdst = dst->as_register(); |
duke@435 | 676 | int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; |
duke@435 | 677 | __ sll (rval, shift, rdst); |
duke@435 | 678 | __ srl (rdst, shift, rdst); |
duke@435 | 679 | break; |
duke@435 | 680 | } |
duke@435 | 681 | |
duke@435 | 682 | default: ShouldNotReachHere(); |
duke@435 | 683 | } |
duke@435 | 684 | } |
duke@435 | 685 | |
duke@435 | 686 | |
duke@435 | 687 | void LIR_Assembler::align_call(LIR_Code) { |
duke@435 | 688 | // do nothing since all instructions are word aligned on sparc |
duke@435 | 689 | } |
duke@435 | 690 | |
duke@435 | 691 | |
duke@435 | 692 | void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) { |
duke@435 | 693 | __ call(entry, rtype); |
duke@435 | 694 | // the peephole pass fills the delay slot |
duke@435 | 695 | } |
duke@435 | 696 | |
duke@435 | 697 | |
duke@435 | 698 | void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) { |
duke@435 | 699 | RelocationHolder rspec = virtual_call_Relocation::spec(pc()); |
duke@435 | 700 | __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); |
duke@435 | 701 | __ relocate(rspec); |
duke@435 | 702 | __ call(entry, relocInfo::none); |
duke@435 | 703 | // the peephole pass fills the delay slot |
duke@435 | 704 | } |
duke@435 | 705 | |
duke@435 | 706 | |
duke@435 | 707 | void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) { |
duke@435 | 708 | add_debug_info_for_null_check_here(info); |
duke@435 | 709 | __ ld_ptr(Address(O0, 0, oopDesc::klass_offset_in_bytes()), G3_scratch); |
duke@435 | 710 | if (__ is_simm13(vtable_offset) ) { |
duke@435 | 711 | __ ld_ptr(G3_scratch, vtable_offset, G5_method); |
duke@435 | 712 | } else { |
duke@435 | 713 | // This will generate 2 instructions |
duke@435 | 714 | __ set(vtable_offset, G5_method); |
duke@435 | 715 | // ld_ptr, set_hi, set |
duke@435 | 716 | __ ld_ptr(G3_scratch, G5_method, G5_method); |
duke@435 | 717 | } |
duke@435 | 718 | __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); |
duke@435 | 719 | __ callr(G3_scratch, G0); |
duke@435 | 720 | // the peephole pass fills the delay slot |
duke@435 | 721 | } |
duke@435 | 722 | |
duke@435 | 723 | |
duke@435 | 724 | // load with 32-bit displacement |
duke@435 | 725 | int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) { |
duke@435 | 726 | int load_offset = code_offset(); |
duke@435 | 727 | if (Assembler::is_simm13(disp)) { |
duke@435 | 728 | if (info != NULL) add_debug_info_for_null_check_here(info); |
duke@435 | 729 | switch(ld_type) { |
duke@435 | 730 | case T_BOOLEAN: // fall through |
duke@435 | 731 | case T_BYTE : __ ldsb(s, disp, d); break; |
duke@435 | 732 | case T_CHAR : __ lduh(s, disp, d); break; |
duke@435 | 733 | case T_SHORT : __ ldsh(s, disp, d); break; |
duke@435 | 734 | case T_INT : __ ld(s, disp, d); break; |
duke@435 | 735 | case T_ADDRESS:// fall through |
duke@435 | 736 | case T_ARRAY : // fall through |
duke@435 | 737 | case T_OBJECT: __ ld_ptr(s, disp, d); break; |
duke@435 | 738 | default : ShouldNotReachHere(); |
duke@435 | 739 | } |
duke@435 | 740 | } else { |
duke@435 | 741 | __ sethi(disp & ~0x3ff, O7, true); |
duke@435 | 742 | __ add(O7, disp & 0x3ff, O7); |
duke@435 | 743 | if (info != NULL) add_debug_info_for_null_check_here(info); |
duke@435 | 744 | load_offset = code_offset(); |
duke@435 | 745 | switch(ld_type) { |
duke@435 | 746 | case T_BOOLEAN: // fall through |
duke@435 | 747 | case T_BYTE : __ ldsb(s, O7, d); break; |
duke@435 | 748 | case T_CHAR : __ lduh(s, O7, d); break; |
duke@435 | 749 | case T_SHORT : __ ldsh(s, O7, d); break; |
duke@435 | 750 | case T_INT : __ ld(s, O7, d); break; |
duke@435 | 751 | case T_ADDRESS:// fall through |
duke@435 | 752 | case T_ARRAY : // fall through |
duke@435 | 753 | case T_OBJECT: __ ld_ptr(s, O7, d); break; |
duke@435 | 754 | default : ShouldNotReachHere(); |
duke@435 | 755 | } |
duke@435 | 756 | } |
duke@435 | 757 | if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d); |
duke@435 | 758 | return load_offset; |
duke@435 | 759 | } |
duke@435 | 760 | |
duke@435 | 761 | |
duke@435 | 762 | // store with 32-bit displacement |
duke@435 | 763 | void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) { |
duke@435 | 764 | if (Assembler::is_simm13(offset)) { |
duke@435 | 765 | if (info != NULL) add_debug_info_for_null_check_here(info); |
duke@435 | 766 | switch (type) { |
duke@435 | 767 | case T_BOOLEAN: // fall through |
duke@435 | 768 | case T_BYTE : __ stb(value, base, offset); break; |
duke@435 | 769 | case T_CHAR : __ sth(value, base, offset); break; |
duke@435 | 770 | case T_SHORT : __ sth(value, base, offset); break; |
duke@435 | 771 | case T_INT : __ stw(value, base, offset); break; |
duke@435 | 772 | case T_ADDRESS:// fall through |
duke@435 | 773 | case T_ARRAY : // fall through |
duke@435 | 774 | case T_OBJECT: __ st_ptr(value, base, offset); break; |
duke@435 | 775 | default : ShouldNotReachHere(); |
duke@435 | 776 | } |
duke@435 | 777 | } else { |
duke@435 | 778 | __ sethi(offset & ~0x3ff, O7, true); |
duke@435 | 779 | __ add(O7, offset & 0x3ff, O7); |
duke@435 | 780 | if (info != NULL) add_debug_info_for_null_check_here(info); |
duke@435 | 781 | switch (type) { |
duke@435 | 782 | case T_BOOLEAN: // fall through |
duke@435 | 783 | case T_BYTE : __ stb(value, base, O7); break; |
duke@435 | 784 | case T_CHAR : __ sth(value, base, O7); break; |
duke@435 | 785 | case T_SHORT : __ sth(value, base, O7); break; |
duke@435 | 786 | case T_INT : __ stw(value, base, O7); break; |
duke@435 | 787 | case T_ADDRESS:// fall through |
duke@435 | 788 | case T_ARRAY : //fall through |
duke@435 | 789 | case T_OBJECT: __ st_ptr(value, base, O7); break; |
duke@435 | 790 | default : ShouldNotReachHere(); |
duke@435 | 791 | } |
duke@435 | 792 | } |
duke@435 | 793 | // Note: Do the store before verification as the code might be patched! |
duke@435 | 794 | if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value); |
duke@435 | 795 | } |
duke@435 | 796 | |
duke@435 | 797 | |
duke@435 | 798 | // load float with 32-bit displacement |
duke@435 | 799 | void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { |
duke@435 | 800 | FloatRegisterImpl::Width w; |
duke@435 | 801 | switch(ld_type) { |
duke@435 | 802 | case T_FLOAT : w = FloatRegisterImpl::S; break; |
duke@435 | 803 | case T_DOUBLE: w = FloatRegisterImpl::D; break; |
duke@435 | 804 | default : ShouldNotReachHere(); |
duke@435 | 805 | } |
duke@435 | 806 | |
duke@435 | 807 | if (Assembler::is_simm13(disp)) { |
duke@435 | 808 | if (info != NULL) add_debug_info_for_null_check_here(info); |
duke@435 | 809 | if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) { |
duke@435 | 810 | __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor()); |
duke@435 | 811 | __ ldf(FloatRegisterImpl::S, s, disp , d); |
duke@435 | 812 | } else { |
duke@435 | 813 | __ ldf(w, s, disp, d); |
duke@435 | 814 | } |
duke@435 | 815 | } else { |
duke@435 | 816 | __ sethi(disp & ~0x3ff, O7, true); |
duke@435 | 817 | __ add(O7, disp & 0x3ff, O7); |
duke@435 | 818 | if (info != NULL) add_debug_info_for_null_check_here(info); |
duke@435 | 819 | __ ldf(w, s, O7, d); |
duke@435 | 820 | } |
duke@435 | 821 | } |
duke@435 | 822 | |
duke@435 | 823 | |
duke@435 | 824 | // store float with 32-bit displacement |
duke@435 | 825 | void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) { |
duke@435 | 826 | FloatRegisterImpl::Width w; |
duke@435 | 827 | switch(type) { |
duke@435 | 828 | case T_FLOAT : w = FloatRegisterImpl::S; break; |
duke@435 | 829 | case T_DOUBLE: w = FloatRegisterImpl::D; break; |
duke@435 | 830 | default : ShouldNotReachHere(); |
duke@435 | 831 | } |
duke@435 | 832 | |
duke@435 | 833 | if (Assembler::is_simm13(offset)) { |
duke@435 | 834 | if (info != NULL) add_debug_info_for_null_check_here(info); |
duke@435 | 835 | if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) { |
duke@435 | 836 | __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord); |
duke@435 | 837 | __ stf(FloatRegisterImpl::S, value , base, offset); |
duke@435 | 838 | } else { |
duke@435 | 839 | __ stf(w, value, base, offset); |
duke@435 | 840 | } |
duke@435 | 841 | } else { |
duke@435 | 842 | __ sethi(offset & ~0x3ff, O7, true); |
duke@435 | 843 | __ add(O7, offset & 0x3ff, O7); |
duke@435 | 844 | if (info != NULL) add_debug_info_for_null_check_here(info); |
duke@435 | 845 | __ stf(w, value, O7, base); |
duke@435 | 846 | } |
duke@435 | 847 | } |
duke@435 | 848 | |
duke@435 | 849 | |
duke@435 | 850 | int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) { |
duke@435 | 851 | int store_offset; |
duke@435 | 852 | if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { |
duke@435 | 853 | assert(!unaligned, "can't handle this"); |
duke@435 | 854 | // for offsets larger than a simm13 we setup the offset in O7 |
duke@435 | 855 | __ sethi(offset & ~0x3ff, O7, true); |
duke@435 | 856 | __ add(O7, offset & 0x3ff, O7); |
duke@435 | 857 | store_offset = store(from_reg, base, O7, type); |
duke@435 | 858 | } else { |
duke@435 | 859 | if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); |
duke@435 | 860 | store_offset = code_offset(); |
duke@435 | 861 | switch (type) { |
duke@435 | 862 | case T_BOOLEAN: // fall through |
duke@435 | 863 | case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; |
duke@435 | 864 | case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; |
duke@435 | 865 | case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; |
duke@435 | 866 | case T_INT : __ stw(from_reg->as_register(), base, offset); break; |
duke@435 | 867 | case T_LONG : |
duke@435 | 868 | #ifdef _LP64 |
duke@435 | 869 | if (unaligned || PatchALot) { |
duke@435 | 870 | __ srax(from_reg->as_register_lo(), 32, O7); |
duke@435 | 871 | __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); |
duke@435 | 872 | __ stw(O7, base, offset + hi_word_offset_in_bytes); |
duke@435 | 873 | } else { |
duke@435 | 874 | __ stx(from_reg->as_register_lo(), base, offset); |
duke@435 | 875 | } |
duke@435 | 876 | #else |
duke@435 | 877 | assert(Assembler::is_simm13(offset + 4), "must be"); |
duke@435 | 878 | __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); |
duke@435 | 879 | __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); |
duke@435 | 880 | #endif |
duke@435 | 881 | break; |
duke@435 | 882 | case T_ADDRESS:// fall through |
duke@435 | 883 | case T_ARRAY : // fall through |
duke@435 | 884 | case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break; |
duke@435 | 885 | case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; |
duke@435 | 886 | case T_DOUBLE: |
duke@435 | 887 | { |
duke@435 | 888 | FloatRegister reg = from_reg->as_double_reg(); |
duke@435 | 889 | // split unaligned stores |
duke@435 | 890 | if (unaligned || PatchALot) { |
duke@435 | 891 | assert(Assembler::is_simm13(offset + 4), "must be"); |
duke@435 | 892 | __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); |
duke@435 | 893 | __ stf(FloatRegisterImpl::S, reg, base, offset); |
duke@435 | 894 | } else { |
duke@435 | 895 | __ stf(FloatRegisterImpl::D, reg, base, offset); |
duke@435 | 896 | } |
duke@435 | 897 | break; |
duke@435 | 898 | } |
duke@435 | 899 | default : ShouldNotReachHere(); |
duke@435 | 900 | } |
duke@435 | 901 | } |
duke@435 | 902 | return store_offset; |
duke@435 | 903 | } |
duke@435 | 904 | |
duke@435 | 905 | |
duke@435 | 906 | int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) { |
duke@435 | 907 | if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); |
duke@435 | 908 | int store_offset = code_offset(); |
duke@435 | 909 | switch (type) { |
duke@435 | 910 | case T_BOOLEAN: // fall through |
duke@435 | 911 | case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; |
duke@435 | 912 | case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; |
duke@435 | 913 | case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; |
duke@435 | 914 | case T_INT : __ stw(from_reg->as_register(), base, disp); break; |
duke@435 | 915 | case T_LONG : |
duke@435 | 916 | #ifdef _LP64 |
duke@435 | 917 | __ stx(from_reg->as_register_lo(), base, disp); |
duke@435 | 918 | #else |
duke@435 | 919 | assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); |
duke@435 | 920 | __ std(from_reg->as_register_hi(), base, disp); |
duke@435 | 921 | #endif |
duke@435 | 922 | break; |
duke@435 | 923 | case T_ADDRESS:// fall through |
duke@435 | 924 | case T_ARRAY : // fall through |
duke@435 | 925 | case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break; |
duke@435 | 926 | case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; |
duke@435 | 927 | case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; |
duke@435 | 928 | default : ShouldNotReachHere(); |
duke@435 | 929 | } |
duke@435 | 930 | return store_offset; |
duke@435 | 931 | } |
duke@435 | 932 | |
duke@435 | 933 | |
duke@435 | 934 | int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) { |
duke@435 | 935 | int load_offset; |
duke@435 | 936 | if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { |
duke@435 | 937 | assert(base != O7, "destroying register"); |
duke@435 | 938 | assert(!unaligned, "can't handle this"); |
duke@435 | 939 | // for offsets larger than a simm13 we setup the offset in O7 |
duke@435 | 940 | __ sethi(offset & ~0x3ff, O7, true); |
duke@435 | 941 | __ add(O7, offset & 0x3ff, O7); |
duke@435 | 942 | load_offset = load(base, O7, to_reg, type); |
duke@435 | 943 | } else { |
duke@435 | 944 | load_offset = code_offset(); |
duke@435 | 945 | switch(type) { |
duke@435 | 946 | case T_BOOLEAN: // fall through |
duke@435 | 947 | case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; |
duke@435 | 948 | case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; |
duke@435 | 949 | case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; |
duke@435 | 950 | case T_INT : __ ld(base, offset, to_reg->as_register()); break; |
duke@435 | 951 | case T_LONG : |
duke@435 | 952 | if (!unaligned) { |
duke@435 | 953 | #ifdef _LP64 |
duke@435 | 954 | __ ldx(base, offset, to_reg->as_register_lo()); |
duke@435 | 955 | #else |
duke@435 | 956 | assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), |
duke@435 | 957 | "must be sequential"); |
duke@435 | 958 | __ ldd(base, offset, to_reg->as_register_hi()); |
duke@435 | 959 | #endif |
duke@435 | 960 | } else { |
duke@435 | 961 | #ifdef _LP64 |
duke@435 | 962 | assert(base != to_reg->as_register_lo(), "can't handle this"); |
duke@435 | 963 | __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); |
duke@435 | 964 | __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); |
duke@435 | 965 | __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); |
duke@435 | 966 | #else |
duke@435 | 967 | if (base == to_reg->as_register_lo()) { |
duke@435 | 968 | __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); |
duke@435 | 969 | __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); |
duke@435 | 970 | } else { |
duke@435 | 971 | __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); |
duke@435 | 972 | __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); |
duke@435 | 973 | } |
duke@435 | 974 | #endif |
duke@435 | 975 | } |
duke@435 | 976 | break; |
duke@435 | 977 | case T_ADDRESS:// fall through |
duke@435 | 978 | case T_ARRAY : // fall through |
duke@435 | 979 | case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break; |
duke@435 | 980 | case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; |
duke@435 | 981 | case T_DOUBLE: |
duke@435 | 982 | { |
duke@435 | 983 | FloatRegister reg = to_reg->as_double_reg(); |
duke@435 | 984 | // split unaligned loads |
duke@435 | 985 | if (unaligned || PatchALot) { |
duke@435 | 986 | __ ldf(FloatRegisterImpl::S, base, offset + BytesPerWord, reg->successor()); |
duke@435 | 987 | __ ldf(FloatRegisterImpl::S, base, offset, reg); |
duke@435 | 988 | } else { |
duke@435 | 989 | __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); |
duke@435 | 990 | } |
duke@435 | 991 | break; |
duke@435 | 992 | } |
duke@435 | 993 | default : ShouldNotReachHere(); |
duke@435 | 994 | } |
duke@435 | 995 | if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); |
duke@435 | 996 | } |
duke@435 | 997 | return load_offset; |
duke@435 | 998 | } |
duke@435 | 999 | |
duke@435 | 1000 | |
duke@435 | 1001 | int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) { |
duke@435 | 1002 | int load_offset = code_offset(); |
duke@435 | 1003 | switch(type) { |
duke@435 | 1004 | case T_BOOLEAN: // fall through |
duke@435 | 1005 | case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; |
duke@435 | 1006 | case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; |
duke@435 | 1007 | case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; |
duke@435 | 1008 | case T_INT : __ ld(base, disp, to_reg->as_register()); break; |
duke@435 | 1009 | case T_ADDRESS:// fall through |
duke@435 | 1010 | case T_ARRAY : // fall through |
duke@435 | 1011 | case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break; |
duke@435 | 1012 | case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; |
duke@435 | 1013 | case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; |
duke@435 | 1014 | case T_LONG : |
duke@435 | 1015 | #ifdef _LP64 |
duke@435 | 1016 | __ ldx(base, disp, to_reg->as_register_lo()); |
duke@435 | 1017 | #else |
duke@435 | 1018 | assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), |
duke@435 | 1019 | "must be sequential"); |
duke@435 | 1020 | __ ldd(base, disp, to_reg->as_register_hi()); |
duke@435 | 1021 | #endif |
duke@435 | 1022 | break; |
duke@435 | 1023 | default : ShouldNotReachHere(); |
duke@435 | 1024 | } |
duke@435 | 1025 | if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); |
duke@435 | 1026 | return load_offset; |
duke@435 | 1027 | } |
duke@435 | 1028 | |
duke@435 | 1029 | |
duke@435 | 1030 | // load/store with an Address |
duke@435 | 1031 | void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) { |
duke@435 | 1032 | load(a.base(), a.disp() + offset, d, ld_type, info); |
duke@435 | 1033 | } |
duke@435 | 1034 | |
duke@435 | 1035 | |
duke@435 | 1036 | void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { |
duke@435 | 1037 | store(value, dest.base(), dest.disp() + offset, type, info); |
duke@435 | 1038 | } |
duke@435 | 1039 | |
duke@435 | 1040 | |
duke@435 | 1041 | // loadf/storef with an Address |
duke@435 | 1042 | void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) { |
duke@435 | 1043 | load(a.base(), a.disp() + offset, d, ld_type, info); |
duke@435 | 1044 | } |
duke@435 | 1045 | |
duke@435 | 1046 | |
duke@435 | 1047 | void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { |
duke@435 | 1048 | store(value, dest.base(), dest.disp() + offset, type, info); |
duke@435 | 1049 | } |
duke@435 | 1050 | |
duke@435 | 1051 | |
duke@435 | 1052 | // load/store with an Address |
duke@435 | 1053 | void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) { |
duke@435 | 1054 | load(as_Address(a), d, ld_type, info); |
duke@435 | 1055 | } |
duke@435 | 1056 | |
duke@435 | 1057 | |
duke@435 | 1058 | void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { |
duke@435 | 1059 | store(value, as_Address(dest), type, info); |
duke@435 | 1060 | } |
duke@435 | 1061 | |
duke@435 | 1062 | |
duke@435 | 1063 | // loadf/storef with an Address |
duke@435 | 1064 | void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { |
duke@435 | 1065 | load(as_Address(a), d, ld_type, info); |
duke@435 | 1066 | } |
duke@435 | 1067 | |
duke@435 | 1068 | |
duke@435 | 1069 | void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { |
duke@435 | 1070 | store(value, as_Address(dest), type, info); |
duke@435 | 1071 | } |
duke@435 | 1072 | |
duke@435 | 1073 | |
duke@435 | 1074 | void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { |
duke@435 | 1075 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 1076 | switch (c->type()) { |
duke@435 | 1077 | case T_INT: |
duke@435 | 1078 | case T_FLOAT: { |
duke@435 | 1079 | Register src_reg = O7; |
duke@435 | 1080 | int value = c->as_jint_bits(); |
duke@435 | 1081 | if (value == 0) { |
duke@435 | 1082 | src_reg = G0; |
duke@435 | 1083 | } else { |
duke@435 | 1084 | __ set(value, O7); |
duke@435 | 1085 | } |
duke@435 | 1086 | Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 1087 | __ stw(src_reg, addr.base(), addr.disp()); |
duke@435 | 1088 | break; |
duke@435 | 1089 | } |
duke@435 | 1090 | case T_OBJECT: { |
duke@435 | 1091 | Register src_reg = O7; |
duke@435 | 1092 | jobject2reg(c->as_jobject(), src_reg); |
duke@435 | 1093 | Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 1094 | __ st_ptr(src_reg, addr.base(), addr.disp()); |
duke@435 | 1095 | break; |
duke@435 | 1096 | } |
duke@435 | 1097 | case T_LONG: |
duke@435 | 1098 | case T_DOUBLE: { |
duke@435 | 1099 | Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); |
duke@435 | 1100 | |
duke@435 | 1101 | Register tmp = O7; |
duke@435 | 1102 | int value_lo = c->as_jint_lo_bits(); |
duke@435 | 1103 | if (value_lo == 0) { |
duke@435 | 1104 | tmp = G0; |
duke@435 | 1105 | } else { |
duke@435 | 1106 | __ set(value_lo, O7); |
duke@435 | 1107 | } |
duke@435 | 1108 | __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); |
duke@435 | 1109 | int value_hi = c->as_jint_hi_bits(); |
duke@435 | 1110 | if (value_hi == 0) { |
duke@435 | 1111 | tmp = G0; |
duke@435 | 1112 | } else { |
duke@435 | 1113 | __ set(value_hi, O7); |
duke@435 | 1114 | } |
duke@435 | 1115 | __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); |
duke@435 | 1116 | break; |
duke@435 | 1117 | } |
duke@435 | 1118 | default: |
duke@435 | 1119 | Unimplemented(); |
duke@435 | 1120 | } |
duke@435 | 1121 | } |
duke@435 | 1122 | |
duke@435 | 1123 | |
duke@435 | 1124 | void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { |
duke@435 | 1125 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 1126 | LIR_Address* addr = dest->as_address_ptr(); |
duke@435 | 1127 | Register base = addr->base()->as_pointer_register(); |
duke@435 | 1128 | |
duke@435 | 1129 | if (info != NULL) { |
duke@435 | 1130 | add_debug_info_for_null_check_here(info); |
duke@435 | 1131 | } |
duke@435 | 1132 | switch (c->type()) { |
duke@435 | 1133 | case T_INT: |
duke@435 | 1134 | case T_FLOAT: { |
duke@435 | 1135 | LIR_Opr tmp = FrameMap::O7_opr; |
duke@435 | 1136 | int value = c->as_jint_bits(); |
duke@435 | 1137 | if (value == 0) { |
duke@435 | 1138 | tmp = FrameMap::G0_opr; |
duke@435 | 1139 | } else if (Assembler::is_simm13(value)) { |
duke@435 | 1140 | __ set(value, O7); |
duke@435 | 1141 | } |
duke@435 | 1142 | if (addr->index()->is_valid()) { |
duke@435 | 1143 | assert(addr->disp() == 0, "must be zero"); |
duke@435 | 1144 | store(tmp, base, addr->index()->as_pointer_register(), type); |
duke@435 | 1145 | } else { |
duke@435 | 1146 | assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); |
duke@435 | 1147 | store(tmp, base, addr->disp(), type); |
duke@435 | 1148 | } |
duke@435 | 1149 | break; |
duke@435 | 1150 | } |
duke@435 | 1151 | case T_LONG: |
duke@435 | 1152 | case T_DOUBLE: { |
duke@435 | 1153 | assert(!addr->index()->is_valid(), "can't handle reg reg address here"); |
duke@435 | 1154 | assert(Assembler::is_simm13(addr->disp()) && |
duke@435 | 1155 | Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); |
duke@435 | 1156 | |
duke@435 | 1157 | Register tmp = O7; |
duke@435 | 1158 | int value_lo = c->as_jint_lo_bits(); |
duke@435 | 1159 | if (value_lo == 0) { |
duke@435 | 1160 | tmp = G0; |
duke@435 | 1161 | } else { |
duke@435 | 1162 | __ set(value_lo, O7); |
duke@435 | 1163 | } |
duke@435 | 1164 | store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT); |
duke@435 | 1165 | int value_hi = c->as_jint_hi_bits(); |
duke@435 | 1166 | if (value_hi == 0) { |
duke@435 | 1167 | tmp = G0; |
duke@435 | 1168 | } else { |
duke@435 | 1169 | __ set(value_hi, O7); |
duke@435 | 1170 | } |
duke@435 | 1171 | store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT); |
duke@435 | 1172 | break; |
duke@435 | 1173 | } |
duke@435 | 1174 | case T_OBJECT: { |
duke@435 | 1175 | jobject obj = c->as_jobject(); |
duke@435 | 1176 | LIR_Opr tmp; |
duke@435 | 1177 | if (obj == NULL) { |
duke@435 | 1178 | tmp = FrameMap::G0_opr; |
duke@435 | 1179 | } else { |
duke@435 | 1180 | tmp = FrameMap::O7_opr; |
duke@435 | 1181 | jobject2reg(c->as_jobject(), O7); |
duke@435 | 1182 | } |
duke@435 | 1183 | // handle either reg+reg or reg+disp address |
duke@435 | 1184 | if (addr->index()->is_valid()) { |
duke@435 | 1185 | assert(addr->disp() == 0, "must be zero"); |
duke@435 | 1186 | store(tmp, base, addr->index()->as_pointer_register(), type); |
duke@435 | 1187 | } else { |
duke@435 | 1188 | assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); |
duke@435 | 1189 | store(tmp, base, addr->disp(), type); |
duke@435 | 1190 | } |
duke@435 | 1191 | |
duke@435 | 1192 | break; |
duke@435 | 1193 | } |
duke@435 | 1194 | default: |
duke@435 | 1195 | Unimplemented(); |
duke@435 | 1196 | } |
duke@435 | 1197 | } |
duke@435 | 1198 | |
duke@435 | 1199 | |
duke@435 | 1200 | void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { |
duke@435 | 1201 | LIR_Const* c = src->as_constant_ptr(); |
duke@435 | 1202 | LIR_Opr to_reg = dest; |
duke@435 | 1203 | |
duke@435 | 1204 | switch (c->type()) { |
duke@435 | 1205 | case T_INT: |
duke@435 | 1206 | { |
duke@435 | 1207 | jint con = c->as_jint(); |
duke@435 | 1208 | if (to_reg->is_single_cpu()) { |
duke@435 | 1209 | assert(patch_code == lir_patch_none, "no patching handled here"); |
duke@435 | 1210 | __ set(con, to_reg->as_register()); |
duke@435 | 1211 | } else { |
duke@435 | 1212 | ShouldNotReachHere(); |
duke@435 | 1213 | assert(to_reg->is_single_fpu(), "wrong register kind"); |
duke@435 | 1214 | |
duke@435 | 1215 | __ set(con, O7); |
duke@435 | 1216 | Address temp_slot(SP, 0, (frame::register_save_words * wordSize) + STACK_BIAS); |
duke@435 | 1217 | __ st(O7, temp_slot); |
duke@435 | 1218 | __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); |
duke@435 | 1219 | } |
duke@435 | 1220 | } |
duke@435 | 1221 | break; |
duke@435 | 1222 | |
duke@435 | 1223 | case T_LONG: |
duke@435 | 1224 | { |
duke@435 | 1225 | jlong con = c->as_jlong(); |
duke@435 | 1226 | |
duke@435 | 1227 | if (to_reg->is_double_cpu()) { |
duke@435 | 1228 | #ifdef _LP64 |
duke@435 | 1229 | __ set(con, to_reg->as_register_lo()); |
duke@435 | 1230 | #else |
duke@435 | 1231 | __ set(low(con), to_reg->as_register_lo()); |
duke@435 | 1232 | __ set(high(con), to_reg->as_register_hi()); |
duke@435 | 1233 | #endif |
duke@435 | 1234 | #ifdef _LP64 |
duke@435 | 1235 | } else if (to_reg->is_single_cpu()) { |
duke@435 | 1236 | __ set(con, to_reg->as_register()); |
duke@435 | 1237 | #endif |
duke@435 | 1238 | } else { |
duke@435 | 1239 | ShouldNotReachHere(); |
duke@435 | 1240 | assert(to_reg->is_double_fpu(), "wrong register kind"); |
duke@435 | 1241 | Address temp_slot_lo(SP, 0, ((frame::register_save_words ) * wordSize) + STACK_BIAS); |
duke@435 | 1242 | Address temp_slot_hi(SP, 0, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); |
duke@435 | 1243 | __ set(low(con), O7); |
duke@435 | 1244 | __ st(O7, temp_slot_lo); |
duke@435 | 1245 | __ set(high(con), O7); |
duke@435 | 1246 | __ st(O7, temp_slot_hi); |
duke@435 | 1247 | __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); |
duke@435 | 1248 | } |
duke@435 | 1249 | } |
duke@435 | 1250 | break; |
duke@435 | 1251 | |
duke@435 | 1252 | case T_OBJECT: |
duke@435 | 1253 | { |
duke@435 | 1254 | if (patch_code == lir_patch_none) { |
duke@435 | 1255 | jobject2reg(c->as_jobject(), to_reg->as_register()); |
duke@435 | 1256 | } else { |
duke@435 | 1257 | jobject2reg_with_patching(to_reg->as_register(), info); |
duke@435 | 1258 | } |
duke@435 | 1259 | } |
duke@435 | 1260 | break; |
duke@435 | 1261 | |
duke@435 | 1262 | case T_FLOAT: |
duke@435 | 1263 | { |
duke@435 | 1264 | address const_addr = __ float_constant(c->as_jfloat()); |
duke@435 | 1265 | if (const_addr == NULL) { |
duke@435 | 1266 | bailout("const section overflow"); |
duke@435 | 1267 | break; |
duke@435 | 1268 | } |
duke@435 | 1269 | RelocationHolder rspec = internal_word_Relocation::spec(const_addr); |
duke@435 | 1270 | if (to_reg->is_single_fpu()) { |
duke@435 | 1271 | __ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec); |
duke@435 | 1272 | __ relocate(rspec); |
duke@435 | 1273 | |
duke@435 | 1274 | int offset = (intx)const_addr & 0x3ff; |
duke@435 | 1275 | __ ldf (FloatRegisterImpl::S, O7, offset, to_reg->as_float_reg()); |
duke@435 | 1276 | |
duke@435 | 1277 | } else { |
duke@435 | 1278 | assert(to_reg->is_single_cpu(), "Must be a cpu register."); |
duke@435 | 1279 | |
duke@435 | 1280 | __ set((intx)const_addr, O7, rspec); |
duke@435 | 1281 | load(O7, 0, to_reg->as_register(), T_INT); |
duke@435 | 1282 | } |
duke@435 | 1283 | } |
duke@435 | 1284 | break; |
duke@435 | 1285 | |
duke@435 | 1286 | case T_DOUBLE: |
duke@435 | 1287 | { |
duke@435 | 1288 | address const_addr = __ double_constant(c->as_jdouble()); |
duke@435 | 1289 | if (const_addr == NULL) { |
duke@435 | 1290 | bailout("const section overflow"); |
duke@435 | 1291 | break; |
duke@435 | 1292 | } |
duke@435 | 1293 | RelocationHolder rspec = internal_word_Relocation::spec(const_addr); |
duke@435 | 1294 | |
duke@435 | 1295 | if (to_reg->is_double_fpu()) { |
duke@435 | 1296 | __ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec); |
duke@435 | 1297 | int offset = (intx)const_addr & 0x3ff; |
duke@435 | 1298 | __ relocate(rspec); |
duke@435 | 1299 | __ ldf (FloatRegisterImpl::D, O7, offset, to_reg->as_double_reg()); |
duke@435 | 1300 | } else { |
duke@435 | 1301 | assert(to_reg->is_double_cpu(), "Must be a long register."); |
duke@435 | 1302 | #ifdef _LP64 |
duke@435 | 1303 | __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); |
duke@435 | 1304 | #else |
duke@435 | 1305 | __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); |
duke@435 | 1306 | __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); |
duke@435 | 1307 | #endif |
duke@435 | 1308 | } |
duke@435 | 1309 | |
duke@435 | 1310 | } |
duke@435 | 1311 | break; |
duke@435 | 1312 | |
duke@435 | 1313 | default: |
duke@435 | 1314 | ShouldNotReachHere(); |
duke@435 | 1315 | } |
duke@435 | 1316 | } |
duke@435 | 1317 | |
duke@435 | 1318 | Address LIR_Assembler::as_Address(LIR_Address* addr) { |
duke@435 | 1319 | Register reg = addr->base()->as_register(); |
duke@435 | 1320 | return Address(reg, 0, addr->disp()); |
duke@435 | 1321 | } |
duke@435 | 1322 | |
duke@435 | 1323 | |
duke@435 | 1324 | void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1325 | switch (type) { |
duke@435 | 1326 | case T_INT: |
duke@435 | 1327 | case T_FLOAT: { |
duke@435 | 1328 | Register tmp = O7; |
duke@435 | 1329 | Address from = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1330 | Address to = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 1331 | __ lduw(from.base(), from.disp(), tmp); |
duke@435 | 1332 | __ stw(tmp, to.base(), to.disp()); |
duke@435 | 1333 | break; |
duke@435 | 1334 | } |
duke@435 | 1335 | case T_OBJECT: { |
duke@435 | 1336 | Register tmp = O7; |
duke@435 | 1337 | Address from = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1338 | Address to = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 1339 | __ ld_ptr(from.base(), from.disp(), tmp); |
duke@435 | 1340 | __ st_ptr(tmp, to.base(), to.disp()); |
duke@435 | 1341 | break; |
duke@435 | 1342 | } |
duke@435 | 1343 | case T_LONG: |
duke@435 | 1344 | case T_DOUBLE: { |
duke@435 | 1345 | Register tmp = O7; |
duke@435 | 1346 | Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); |
duke@435 | 1347 | Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); |
duke@435 | 1348 | __ lduw(from.base(), from.disp(), tmp); |
duke@435 | 1349 | __ stw(tmp, to.base(), to.disp()); |
duke@435 | 1350 | __ lduw(from.base(), from.disp() + 4, tmp); |
duke@435 | 1351 | __ stw(tmp, to.base(), to.disp() + 4); |
duke@435 | 1352 | break; |
duke@435 | 1353 | } |
duke@435 | 1354 | |
duke@435 | 1355 | default: |
duke@435 | 1356 | ShouldNotReachHere(); |
duke@435 | 1357 | } |
duke@435 | 1358 | } |
duke@435 | 1359 | |
duke@435 | 1360 | |
duke@435 | 1361 | Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { |
duke@435 | 1362 | Address base = as_Address(addr); |
duke@435 | 1363 | return Address(base.base(), 0, base.disp() + hi_word_offset_in_bytes); |
duke@435 | 1364 | } |
duke@435 | 1365 | |
duke@435 | 1366 | |
duke@435 | 1367 | Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { |
duke@435 | 1368 | Address base = as_Address(addr); |
duke@435 | 1369 | return Address(base.base(), 0, base.disp() + lo_word_offset_in_bytes); |
duke@435 | 1370 | } |
duke@435 | 1371 | |
duke@435 | 1372 | |
duke@435 | 1373 | void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, |
duke@435 | 1374 | LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) { |
duke@435 | 1375 | |
duke@435 | 1376 | LIR_Address* addr = src_opr->as_address_ptr(); |
duke@435 | 1377 | LIR_Opr to_reg = dest; |
duke@435 | 1378 | |
duke@435 | 1379 | Register src = addr->base()->as_pointer_register(); |
duke@435 | 1380 | Register disp_reg = noreg; |
duke@435 | 1381 | int disp_value = addr->disp(); |
duke@435 | 1382 | bool needs_patching = (patch_code != lir_patch_none); |
duke@435 | 1383 | |
duke@435 | 1384 | if (addr->base()->type() == T_OBJECT) { |
duke@435 | 1385 | __ verify_oop(src); |
duke@435 | 1386 | } |
duke@435 | 1387 | |
duke@435 | 1388 | PatchingStub* patch = NULL; |
duke@435 | 1389 | if (needs_patching) { |
duke@435 | 1390 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1391 | assert(!to_reg->is_double_cpu() || |
duke@435 | 1392 | patch_code == lir_patch_none || |
duke@435 | 1393 | patch_code == lir_patch_normal, "patching doesn't match register"); |
duke@435 | 1394 | } |
duke@435 | 1395 | |
duke@435 | 1396 | if (addr->index()->is_illegal()) { |
duke@435 | 1397 | if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { |
duke@435 | 1398 | if (needs_patching) { |
duke@435 | 1399 | __ sethi(0, O7, true); |
duke@435 | 1400 | __ add(O7, 0, O7); |
duke@435 | 1401 | } else { |
duke@435 | 1402 | __ set(disp_value, O7); |
duke@435 | 1403 | } |
duke@435 | 1404 | disp_reg = O7; |
duke@435 | 1405 | } |
duke@435 | 1406 | } else if (unaligned || PatchALot) { |
duke@435 | 1407 | __ add(src, addr->index()->as_register(), O7); |
duke@435 | 1408 | src = O7; |
duke@435 | 1409 | } else { |
duke@435 | 1410 | disp_reg = addr->index()->as_pointer_register(); |
duke@435 | 1411 | assert(disp_value == 0, "can't handle 3 operand addresses"); |
duke@435 | 1412 | } |
duke@435 | 1413 | |
duke@435 | 1414 | // remember the offset of the load. The patching_epilog must be done |
duke@435 | 1415 | // before the call to add_debug_info, otherwise the PcDescs don't get |
duke@435 | 1416 | // entered in increasing order. |
duke@435 | 1417 | int offset = code_offset(); |
duke@435 | 1418 | |
duke@435 | 1419 | assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); |
duke@435 | 1420 | if (disp_reg == noreg) { |
duke@435 | 1421 | offset = load(src, disp_value, to_reg, type, unaligned); |
duke@435 | 1422 | } else { |
duke@435 | 1423 | assert(!unaligned, "can't handle this"); |
duke@435 | 1424 | offset = load(src, disp_reg, to_reg, type); |
duke@435 | 1425 | } |
duke@435 | 1426 | |
duke@435 | 1427 | if (patch != NULL) { |
duke@435 | 1428 | patching_epilog(patch, patch_code, src, info); |
duke@435 | 1429 | } |
duke@435 | 1430 | |
duke@435 | 1431 | if (info != NULL) add_debug_info_for_null_check(offset, info); |
duke@435 | 1432 | } |
duke@435 | 1433 | |
duke@435 | 1434 | |
duke@435 | 1435 | void LIR_Assembler::prefetchr(LIR_Opr src) { |
duke@435 | 1436 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1437 | Address from_addr = as_Address(addr); |
duke@435 | 1438 | |
duke@435 | 1439 | if (VM_Version::has_v9()) { |
duke@435 | 1440 | __ prefetch(from_addr, Assembler::severalReads); |
duke@435 | 1441 | } |
duke@435 | 1442 | } |
duke@435 | 1443 | |
duke@435 | 1444 | |
duke@435 | 1445 | void LIR_Assembler::prefetchw(LIR_Opr src) { |
duke@435 | 1446 | LIR_Address* addr = src->as_address_ptr(); |
duke@435 | 1447 | Address from_addr = as_Address(addr); |
duke@435 | 1448 | |
duke@435 | 1449 | if (VM_Version::has_v9()) { |
duke@435 | 1450 | __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); |
duke@435 | 1451 | } |
duke@435 | 1452 | } |
duke@435 | 1453 | |
duke@435 | 1454 | |
duke@435 | 1455 | void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { |
duke@435 | 1456 | Address addr; |
duke@435 | 1457 | if (src->is_single_word()) { |
duke@435 | 1458 | addr = frame_map()->address_for_slot(src->single_stack_ix()); |
duke@435 | 1459 | } else if (src->is_double_word()) { |
duke@435 | 1460 | addr = frame_map()->address_for_double_slot(src->double_stack_ix()); |
duke@435 | 1461 | } |
duke@435 | 1462 | |
duke@435 | 1463 | bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; |
duke@435 | 1464 | load(addr.base(), addr.disp(), dest, dest->type(), unaligned); |
duke@435 | 1465 | } |
duke@435 | 1466 | |
duke@435 | 1467 | |
duke@435 | 1468 | void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { |
duke@435 | 1469 | Address addr; |
duke@435 | 1470 | if (dest->is_single_word()) { |
duke@435 | 1471 | addr = frame_map()->address_for_slot(dest->single_stack_ix()); |
duke@435 | 1472 | } else if (dest->is_double_word()) { |
duke@435 | 1473 | addr = frame_map()->address_for_slot(dest->double_stack_ix()); |
duke@435 | 1474 | } |
duke@435 | 1475 | bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; |
duke@435 | 1476 | store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned); |
duke@435 | 1477 | } |
duke@435 | 1478 | |
duke@435 | 1479 | |
duke@435 | 1480 | void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { |
duke@435 | 1481 | if (from_reg->is_float_kind() && to_reg->is_float_kind()) { |
duke@435 | 1482 | if (from_reg->is_double_fpu()) { |
duke@435 | 1483 | // double to double moves |
duke@435 | 1484 | assert(to_reg->is_double_fpu(), "should match"); |
duke@435 | 1485 | __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); |
duke@435 | 1486 | } else { |
duke@435 | 1487 | // float to float moves |
duke@435 | 1488 | assert(to_reg->is_single_fpu(), "should match"); |
duke@435 | 1489 | __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); |
duke@435 | 1490 | } |
duke@435 | 1491 | } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { |
duke@435 | 1492 | if (from_reg->is_double_cpu()) { |
duke@435 | 1493 | #ifdef _LP64 |
duke@435 | 1494 | __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); |
duke@435 | 1495 | #else |
duke@435 | 1496 | assert(to_reg->is_double_cpu() && |
duke@435 | 1497 | from_reg->as_register_hi() != to_reg->as_register_lo() && |
duke@435 | 1498 | from_reg->as_register_lo() != to_reg->as_register_hi(), |
duke@435 | 1499 | "should both be long and not overlap"); |
duke@435 | 1500 | // long to long moves |
duke@435 | 1501 | __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); |
duke@435 | 1502 | __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); |
duke@435 | 1503 | #endif |
duke@435 | 1504 | #ifdef _LP64 |
duke@435 | 1505 | } else if (to_reg->is_double_cpu()) { |
duke@435 | 1506 | // int to int moves |
duke@435 | 1507 | __ mov(from_reg->as_register(), to_reg->as_register_lo()); |
duke@435 | 1508 | #endif |
duke@435 | 1509 | } else { |
duke@435 | 1510 | // int to int moves |
duke@435 | 1511 | __ mov(from_reg->as_register(), to_reg->as_register()); |
duke@435 | 1512 | } |
duke@435 | 1513 | } else { |
duke@435 | 1514 | ShouldNotReachHere(); |
duke@435 | 1515 | } |
duke@435 | 1516 | if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { |
duke@435 | 1517 | __ verify_oop(to_reg->as_register()); |
duke@435 | 1518 | } |
duke@435 | 1519 | } |
duke@435 | 1520 | |
duke@435 | 1521 | |
duke@435 | 1522 | void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, |
duke@435 | 1523 | LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, |
duke@435 | 1524 | bool unaligned) { |
duke@435 | 1525 | LIR_Address* addr = dest->as_address_ptr(); |
duke@435 | 1526 | |
duke@435 | 1527 | Register src = addr->base()->as_pointer_register(); |
duke@435 | 1528 | Register disp_reg = noreg; |
duke@435 | 1529 | int disp_value = addr->disp(); |
duke@435 | 1530 | bool needs_patching = (patch_code != lir_patch_none); |
duke@435 | 1531 | |
duke@435 | 1532 | if (addr->base()->is_oop_register()) { |
duke@435 | 1533 | __ verify_oop(src); |
duke@435 | 1534 | } |
duke@435 | 1535 | |
duke@435 | 1536 | PatchingStub* patch = NULL; |
duke@435 | 1537 | if (needs_patching) { |
duke@435 | 1538 | patch = new PatchingStub(_masm, PatchingStub::access_field_id); |
duke@435 | 1539 | assert(!from_reg->is_double_cpu() || |
duke@435 | 1540 | patch_code == lir_patch_none || |
duke@435 | 1541 | patch_code == lir_patch_normal, "patching doesn't match register"); |
duke@435 | 1542 | } |
duke@435 | 1543 | |
duke@435 | 1544 | if (addr->index()->is_illegal()) { |
duke@435 | 1545 | if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { |
duke@435 | 1546 | if (needs_patching) { |
duke@435 | 1547 | __ sethi(0, O7, true); |
duke@435 | 1548 | __ add(O7, 0, O7); |
duke@435 | 1549 | } else { |
duke@435 | 1550 | __ set(disp_value, O7); |
duke@435 | 1551 | } |
duke@435 | 1552 | disp_reg = O7; |
duke@435 | 1553 | } |
duke@435 | 1554 | } else if (unaligned || PatchALot) { |
duke@435 | 1555 | __ add(src, addr->index()->as_register(), O7); |
duke@435 | 1556 | src = O7; |
duke@435 | 1557 | } else { |
duke@435 | 1558 | disp_reg = addr->index()->as_pointer_register(); |
duke@435 | 1559 | assert(disp_value == 0, "can't handle 3 operand addresses"); |
duke@435 | 1560 | } |
duke@435 | 1561 | |
duke@435 | 1562 | // remember the offset of the store. The patching_epilog must be done |
duke@435 | 1563 | // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get |
duke@435 | 1564 | // entered in increasing order. |
duke@435 | 1565 | int offset; |
duke@435 | 1566 | |
duke@435 | 1567 | assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); |
duke@435 | 1568 | if (disp_reg == noreg) { |
duke@435 | 1569 | offset = store(from_reg, src, disp_value, type, unaligned); |
duke@435 | 1570 | } else { |
duke@435 | 1571 | assert(!unaligned, "can't handle this"); |
duke@435 | 1572 | offset = store(from_reg, src, disp_reg, type); |
duke@435 | 1573 | } |
duke@435 | 1574 | |
duke@435 | 1575 | if (patch != NULL) { |
duke@435 | 1576 | patching_epilog(patch, patch_code, src, info); |
duke@435 | 1577 | } |
duke@435 | 1578 | |
duke@435 | 1579 | if (info != NULL) add_debug_info_for_null_check(offset, info); |
duke@435 | 1580 | } |
duke@435 | 1581 | |
duke@435 | 1582 | |
duke@435 | 1583 | void LIR_Assembler::return_op(LIR_Opr result) { |
duke@435 | 1584 | // the poll may need a register so just pick one that isn't the return register |
duke@435 | 1585 | #ifdef TIERED |
duke@435 | 1586 | if (result->type_field() == LIR_OprDesc::long_type) { |
duke@435 | 1587 | // Must move the result to G1 |
duke@435 | 1588 | // Must leave proper result in O0,O1 and G1 (TIERED only) |
duke@435 | 1589 | __ sllx(I0, 32, G1); // Shift bits into high G1 |
duke@435 | 1590 | __ srl (I1, 0, I1); // Zero extend O1 (harmless?) |
duke@435 | 1591 | __ or3 (I1, G1, G1); // OR 64 bits into G1 |
duke@435 | 1592 | } |
duke@435 | 1593 | #endif // TIERED |
duke@435 | 1594 | __ set((intptr_t)os::get_polling_page(), L0); |
duke@435 | 1595 | __ relocate(relocInfo::poll_return_type); |
duke@435 | 1596 | __ ld_ptr(L0, 0, G0); |
duke@435 | 1597 | __ ret(); |
duke@435 | 1598 | __ delayed()->restore(); |
duke@435 | 1599 | } |
duke@435 | 1600 | |
duke@435 | 1601 | |
duke@435 | 1602 | int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 1603 | __ set((intptr_t)os::get_polling_page(), tmp->as_register()); |
duke@435 | 1604 | if (info != NULL) { |
duke@435 | 1605 | add_debug_info_for_branch(info); |
duke@435 | 1606 | } else { |
duke@435 | 1607 | __ relocate(relocInfo::poll_type); |
duke@435 | 1608 | } |
duke@435 | 1609 | |
duke@435 | 1610 | int offset = __ offset(); |
duke@435 | 1611 | __ ld_ptr(tmp->as_register(), 0, G0); |
duke@435 | 1612 | |
duke@435 | 1613 | return offset; |
duke@435 | 1614 | } |
duke@435 | 1615 | |
duke@435 | 1616 | |
duke@435 | 1617 | void LIR_Assembler::emit_static_call_stub() { |
duke@435 | 1618 | address call_pc = __ pc(); |
duke@435 | 1619 | address stub = __ start_a_stub(call_stub_size); |
duke@435 | 1620 | if (stub == NULL) { |
duke@435 | 1621 | bailout("static call stub overflow"); |
duke@435 | 1622 | return; |
duke@435 | 1623 | } |
duke@435 | 1624 | |
duke@435 | 1625 | int start = __ offset(); |
duke@435 | 1626 | __ relocate(static_stub_Relocation::spec(call_pc)); |
duke@435 | 1627 | |
duke@435 | 1628 | __ set_oop(NULL, G5); |
duke@435 | 1629 | // must be set to -1 at code generation time |
duke@435 | 1630 | Address a(G3, (address)-1); |
duke@435 | 1631 | __ jump_to(a, 0); |
duke@435 | 1632 | __ delayed()->nop(); |
duke@435 | 1633 | |
duke@435 | 1634 | assert(__ offset() - start <= call_stub_size, "stub too big"); |
duke@435 | 1635 | __ end_a_stub(); |
duke@435 | 1636 | } |
duke@435 | 1637 | |
duke@435 | 1638 | |
duke@435 | 1639 | void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { |
duke@435 | 1640 | if (opr1->is_single_fpu()) { |
duke@435 | 1641 | __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); |
duke@435 | 1642 | } else if (opr1->is_double_fpu()) { |
duke@435 | 1643 | __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); |
duke@435 | 1644 | } else if (opr1->is_single_cpu()) { |
duke@435 | 1645 | if (opr2->is_constant()) { |
duke@435 | 1646 | switch (opr2->as_constant_ptr()->type()) { |
duke@435 | 1647 | case T_INT: |
duke@435 | 1648 | { jint con = opr2->as_constant_ptr()->as_jint(); |
duke@435 | 1649 | if (Assembler::is_simm13(con)) { |
duke@435 | 1650 | __ cmp(opr1->as_register(), con); |
duke@435 | 1651 | } else { |
duke@435 | 1652 | __ set(con, O7); |
duke@435 | 1653 | __ cmp(opr1->as_register(), O7); |
duke@435 | 1654 | } |
duke@435 | 1655 | } |
duke@435 | 1656 | break; |
duke@435 | 1657 | |
duke@435 | 1658 | case T_OBJECT: |
duke@435 | 1659 | // there are only equal/notequal comparisions on objects |
duke@435 | 1660 | { jobject con = opr2->as_constant_ptr()->as_jobject(); |
duke@435 | 1661 | if (con == NULL) { |
duke@435 | 1662 | __ cmp(opr1->as_register(), 0); |
duke@435 | 1663 | } else { |
duke@435 | 1664 | jobject2reg(con, O7); |
duke@435 | 1665 | __ cmp(opr1->as_register(), O7); |
duke@435 | 1666 | } |
duke@435 | 1667 | } |
duke@435 | 1668 | break; |
duke@435 | 1669 | |
duke@435 | 1670 | default: |
duke@435 | 1671 | ShouldNotReachHere(); |
duke@435 | 1672 | break; |
duke@435 | 1673 | } |
duke@435 | 1674 | } else { |
duke@435 | 1675 | if (opr2->is_address()) { |
duke@435 | 1676 | LIR_Address * addr = opr2->as_address_ptr(); |
duke@435 | 1677 | BasicType type = addr->type(); |
duke@435 | 1678 | if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); |
duke@435 | 1679 | else __ ld(as_Address(addr), O7); |
duke@435 | 1680 | __ cmp(opr1->as_register(), O7); |
duke@435 | 1681 | } else { |
duke@435 | 1682 | __ cmp(opr1->as_register(), opr2->as_register()); |
duke@435 | 1683 | } |
duke@435 | 1684 | } |
duke@435 | 1685 | } else if (opr1->is_double_cpu()) { |
duke@435 | 1686 | Register xlo = opr1->as_register_lo(); |
duke@435 | 1687 | Register xhi = opr1->as_register_hi(); |
duke@435 | 1688 | if (opr2->is_constant() && opr2->as_jlong() == 0) { |
duke@435 | 1689 | assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); |
duke@435 | 1690 | #ifdef _LP64 |
duke@435 | 1691 | __ orcc(xhi, G0, G0); |
duke@435 | 1692 | #else |
duke@435 | 1693 | __ orcc(xhi, xlo, G0); |
duke@435 | 1694 | #endif |
duke@435 | 1695 | } else if (opr2->is_register()) { |
duke@435 | 1696 | Register ylo = opr2->as_register_lo(); |
duke@435 | 1697 | Register yhi = opr2->as_register_hi(); |
duke@435 | 1698 | #ifdef _LP64 |
duke@435 | 1699 | __ cmp(xlo, ylo); |
duke@435 | 1700 | #else |
duke@435 | 1701 | __ subcc(xlo, ylo, xlo); |
duke@435 | 1702 | __ subccc(xhi, yhi, xhi); |
duke@435 | 1703 | if (condition == lir_cond_equal || condition == lir_cond_notEqual) { |
duke@435 | 1704 | __ orcc(xhi, xlo, G0); |
duke@435 | 1705 | } |
duke@435 | 1706 | #endif |
duke@435 | 1707 | } else { |
duke@435 | 1708 | ShouldNotReachHere(); |
duke@435 | 1709 | } |
duke@435 | 1710 | } else if (opr1->is_address()) { |
duke@435 | 1711 | LIR_Address * addr = opr1->as_address_ptr(); |
duke@435 | 1712 | BasicType type = addr->type(); |
duke@435 | 1713 | assert (opr2->is_constant(), "Checking"); |
duke@435 | 1714 | if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); |
duke@435 | 1715 | else __ ld(as_Address(addr), O7); |
duke@435 | 1716 | __ cmp(O7, opr2->as_constant_ptr()->as_jint()); |
duke@435 | 1717 | } else { |
duke@435 | 1718 | ShouldNotReachHere(); |
duke@435 | 1719 | } |
duke@435 | 1720 | } |
duke@435 | 1721 | |
duke@435 | 1722 | |
duke@435 | 1723 | void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ |
duke@435 | 1724 | if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { |
duke@435 | 1725 | bool is_unordered_less = (code == lir_ucmp_fd2i); |
duke@435 | 1726 | if (left->is_single_fpu()) { |
duke@435 | 1727 | __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); |
duke@435 | 1728 | } else if (left->is_double_fpu()) { |
duke@435 | 1729 | __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); |
duke@435 | 1730 | } else { |
duke@435 | 1731 | ShouldNotReachHere(); |
duke@435 | 1732 | } |
duke@435 | 1733 | } else if (code == lir_cmp_l2i) { |
duke@435 | 1734 | __ lcmp(left->as_register_hi(), left->as_register_lo(), |
duke@435 | 1735 | right->as_register_hi(), right->as_register_lo(), |
duke@435 | 1736 | dst->as_register()); |
duke@435 | 1737 | } else { |
duke@435 | 1738 | ShouldNotReachHere(); |
duke@435 | 1739 | } |
duke@435 | 1740 | } |
duke@435 | 1741 | |
duke@435 | 1742 | |
duke@435 | 1743 | void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { |
duke@435 | 1744 | |
duke@435 | 1745 | Assembler::Condition acond; |
duke@435 | 1746 | switch (condition) { |
duke@435 | 1747 | case lir_cond_equal: acond = Assembler::equal; break; |
duke@435 | 1748 | case lir_cond_notEqual: acond = Assembler::notEqual; break; |
duke@435 | 1749 | case lir_cond_less: acond = Assembler::less; break; |
duke@435 | 1750 | case lir_cond_lessEqual: acond = Assembler::lessEqual; break; |
duke@435 | 1751 | case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; |
duke@435 | 1752 | case lir_cond_greater: acond = Assembler::greater; break; |
duke@435 | 1753 | case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; |
duke@435 | 1754 | case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; |
duke@435 | 1755 | default: ShouldNotReachHere(); |
duke@435 | 1756 | }; |
duke@435 | 1757 | |
duke@435 | 1758 | if (opr1->is_constant() && opr1->type() == T_INT) { |
duke@435 | 1759 | Register dest = result->as_register(); |
duke@435 | 1760 | // load up first part of constant before branch |
duke@435 | 1761 | // and do the rest in the delay slot. |
duke@435 | 1762 | if (!Assembler::is_simm13(opr1->as_jint())) { |
duke@435 | 1763 | __ sethi(opr1->as_jint(), dest); |
duke@435 | 1764 | } |
duke@435 | 1765 | } else if (opr1->is_constant()) { |
duke@435 | 1766 | const2reg(opr1, result, lir_patch_none, NULL); |
duke@435 | 1767 | } else if (opr1->is_register()) { |
duke@435 | 1768 | reg2reg(opr1, result); |
duke@435 | 1769 | } else if (opr1->is_stack()) { |
duke@435 | 1770 | stack2reg(opr1, result, result->type()); |
duke@435 | 1771 | } else { |
duke@435 | 1772 | ShouldNotReachHere(); |
duke@435 | 1773 | } |
duke@435 | 1774 | Label skip; |
duke@435 | 1775 | __ br(acond, false, Assembler::pt, skip); |
duke@435 | 1776 | if (opr1->is_constant() && opr1->type() == T_INT) { |
duke@435 | 1777 | Register dest = result->as_register(); |
duke@435 | 1778 | if (Assembler::is_simm13(opr1->as_jint())) { |
duke@435 | 1779 | __ delayed()->or3(G0, opr1->as_jint(), dest); |
duke@435 | 1780 | } else { |
duke@435 | 1781 | // the sethi has been done above, so just put in the low 10 bits |
duke@435 | 1782 | __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); |
duke@435 | 1783 | } |
duke@435 | 1784 | } else { |
duke@435 | 1785 | // can't do anything useful in the delay slot |
duke@435 | 1786 | __ delayed()->nop(); |
duke@435 | 1787 | } |
duke@435 | 1788 | if (opr2->is_constant()) { |
duke@435 | 1789 | const2reg(opr2, result, lir_patch_none, NULL); |
duke@435 | 1790 | } else if (opr2->is_register()) { |
duke@435 | 1791 | reg2reg(opr2, result); |
duke@435 | 1792 | } else if (opr2->is_stack()) { |
duke@435 | 1793 | stack2reg(opr2, result, result->type()); |
duke@435 | 1794 | } else { |
duke@435 | 1795 | ShouldNotReachHere(); |
duke@435 | 1796 | } |
duke@435 | 1797 | __ bind(skip); |
duke@435 | 1798 | } |
duke@435 | 1799 | |
duke@435 | 1800 | |
duke@435 | 1801 | void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { |
duke@435 | 1802 | assert(info == NULL, "unused on this code path"); |
duke@435 | 1803 | assert(left->is_register(), "wrong items state"); |
duke@435 | 1804 | assert(dest->is_register(), "wrong items state"); |
duke@435 | 1805 | |
duke@435 | 1806 | if (right->is_register()) { |
duke@435 | 1807 | if (dest->is_float_kind()) { |
duke@435 | 1808 | |
duke@435 | 1809 | FloatRegister lreg, rreg, res; |
duke@435 | 1810 | FloatRegisterImpl::Width w; |
duke@435 | 1811 | if (right->is_single_fpu()) { |
duke@435 | 1812 | w = FloatRegisterImpl::S; |
duke@435 | 1813 | lreg = left->as_float_reg(); |
duke@435 | 1814 | rreg = right->as_float_reg(); |
duke@435 | 1815 | res = dest->as_float_reg(); |
duke@435 | 1816 | } else { |
duke@435 | 1817 | w = FloatRegisterImpl::D; |
duke@435 | 1818 | lreg = left->as_double_reg(); |
duke@435 | 1819 | rreg = right->as_double_reg(); |
duke@435 | 1820 | res = dest->as_double_reg(); |
duke@435 | 1821 | } |
duke@435 | 1822 | |
duke@435 | 1823 | switch (code) { |
duke@435 | 1824 | case lir_add: __ fadd(w, lreg, rreg, res); break; |
duke@435 | 1825 | case lir_sub: __ fsub(w, lreg, rreg, res); break; |
duke@435 | 1826 | case lir_mul: // fall through |
duke@435 | 1827 | case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; |
duke@435 | 1828 | case lir_div: // fall through |
duke@435 | 1829 | case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; |
duke@435 | 1830 | default: ShouldNotReachHere(); |
duke@435 | 1831 | } |
duke@435 | 1832 | |
duke@435 | 1833 | } else if (dest->is_double_cpu()) { |
duke@435 | 1834 | #ifdef _LP64 |
duke@435 | 1835 | Register dst_lo = dest->as_register_lo(); |
duke@435 | 1836 | Register op1_lo = left->as_pointer_register(); |
duke@435 | 1837 | Register op2_lo = right->as_pointer_register(); |
duke@435 | 1838 | |
duke@435 | 1839 | switch (code) { |
duke@435 | 1840 | case lir_add: |
duke@435 | 1841 | __ add(op1_lo, op2_lo, dst_lo); |
duke@435 | 1842 | break; |
duke@435 | 1843 | |
duke@435 | 1844 | case lir_sub: |
duke@435 | 1845 | __ sub(op1_lo, op2_lo, dst_lo); |
duke@435 | 1846 | break; |
duke@435 | 1847 | |
duke@435 | 1848 | default: ShouldNotReachHere(); |
duke@435 | 1849 | } |
duke@435 | 1850 | #else |
duke@435 | 1851 | Register op1_lo = left->as_register_lo(); |
duke@435 | 1852 | Register op1_hi = left->as_register_hi(); |
duke@435 | 1853 | Register op2_lo = right->as_register_lo(); |
duke@435 | 1854 | Register op2_hi = right->as_register_hi(); |
duke@435 | 1855 | Register dst_lo = dest->as_register_lo(); |
duke@435 | 1856 | Register dst_hi = dest->as_register_hi(); |
duke@435 | 1857 | |
duke@435 | 1858 | switch (code) { |
duke@435 | 1859 | case lir_add: |
duke@435 | 1860 | __ addcc(op1_lo, op2_lo, dst_lo); |
duke@435 | 1861 | __ addc (op1_hi, op2_hi, dst_hi); |
duke@435 | 1862 | break; |
duke@435 | 1863 | |
duke@435 | 1864 | case lir_sub: |
duke@435 | 1865 | __ subcc(op1_lo, op2_lo, dst_lo); |
duke@435 | 1866 | __ subc (op1_hi, op2_hi, dst_hi); |
duke@435 | 1867 | break; |
duke@435 | 1868 | |
duke@435 | 1869 | default: ShouldNotReachHere(); |
duke@435 | 1870 | } |
duke@435 | 1871 | #endif |
duke@435 | 1872 | } else { |
duke@435 | 1873 | assert (right->is_single_cpu(), "Just Checking"); |
duke@435 | 1874 | |
duke@435 | 1875 | Register lreg = left->as_register(); |
duke@435 | 1876 | Register res = dest->as_register(); |
duke@435 | 1877 | Register rreg = right->as_register(); |
duke@435 | 1878 | switch (code) { |
duke@435 | 1879 | case lir_add: __ add (lreg, rreg, res); break; |
duke@435 | 1880 | case lir_sub: __ sub (lreg, rreg, res); break; |
duke@435 | 1881 | case lir_mul: __ mult (lreg, rreg, res); break; |
duke@435 | 1882 | default: ShouldNotReachHere(); |
duke@435 | 1883 | } |
duke@435 | 1884 | } |
duke@435 | 1885 | } else { |
duke@435 | 1886 | assert (right->is_constant(), "must be constant"); |
duke@435 | 1887 | |
duke@435 | 1888 | if (dest->is_single_cpu()) { |
duke@435 | 1889 | Register lreg = left->as_register(); |
duke@435 | 1890 | Register res = dest->as_register(); |
duke@435 | 1891 | int simm13 = right->as_constant_ptr()->as_jint(); |
duke@435 | 1892 | |
duke@435 | 1893 | switch (code) { |
duke@435 | 1894 | case lir_add: __ add (lreg, simm13, res); break; |
duke@435 | 1895 | case lir_sub: __ sub (lreg, simm13, res); break; |
duke@435 | 1896 | case lir_mul: __ mult (lreg, simm13, res); break; |
duke@435 | 1897 | default: ShouldNotReachHere(); |
duke@435 | 1898 | } |
duke@435 | 1899 | } else { |
duke@435 | 1900 | Register lreg = left->as_pointer_register(); |
duke@435 | 1901 | Register res = dest->as_register_lo(); |
duke@435 | 1902 | long con = right->as_constant_ptr()->as_jlong(); |
duke@435 | 1903 | assert(Assembler::is_simm13(con), "must be simm13"); |
duke@435 | 1904 | |
duke@435 | 1905 | switch (code) { |
duke@435 | 1906 | case lir_add: __ add (lreg, (int)con, res); break; |
duke@435 | 1907 | case lir_sub: __ sub (lreg, (int)con, res); break; |
duke@435 | 1908 | case lir_mul: __ mult (lreg, (int)con, res); break; |
duke@435 | 1909 | default: ShouldNotReachHere(); |
duke@435 | 1910 | } |
duke@435 | 1911 | } |
duke@435 | 1912 | } |
duke@435 | 1913 | } |
duke@435 | 1914 | |
duke@435 | 1915 | |
duke@435 | 1916 | void LIR_Assembler::fpop() { |
duke@435 | 1917 | // do nothing |
duke@435 | 1918 | } |
duke@435 | 1919 | |
duke@435 | 1920 | |
duke@435 | 1921 | void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { |
duke@435 | 1922 | switch (code) { |
duke@435 | 1923 | case lir_sin: |
duke@435 | 1924 | case lir_tan: |
duke@435 | 1925 | case lir_cos: { |
duke@435 | 1926 | assert(thread->is_valid(), "preserve the thread object for performance reasons"); |
duke@435 | 1927 | assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); |
duke@435 | 1928 | break; |
duke@435 | 1929 | } |
duke@435 | 1930 | case lir_sqrt: { |
duke@435 | 1931 | assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); |
duke@435 | 1932 | FloatRegister src_reg = value->as_double_reg(); |
duke@435 | 1933 | FloatRegister dst_reg = dest->as_double_reg(); |
duke@435 | 1934 | __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); |
duke@435 | 1935 | break; |
duke@435 | 1936 | } |
duke@435 | 1937 | case lir_abs: { |
duke@435 | 1938 | assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); |
duke@435 | 1939 | FloatRegister src_reg = value->as_double_reg(); |
duke@435 | 1940 | FloatRegister dst_reg = dest->as_double_reg(); |
duke@435 | 1941 | __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); |
duke@435 | 1942 | break; |
duke@435 | 1943 | } |
duke@435 | 1944 | default: { |
duke@435 | 1945 | ShouldNotReachHere(); |
duke@435 | 1946 | break; |
duke@435 | 1947 | } |
duke@435 | 1948 | } |
duke@435 | 1949 | } |
duke@435 | 1950 | |
duke@435 | 1951 | |
duke@435 | 1952 | void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { |
duke@435 | 1953 | if (right->is_constant()) { |
duke@435 | 1954 | if (dest->is_single_cpu()) { |
duke@435 | 1955 | int simm13 = right->as_constant_ptr()->as_jint(); |
duke@435 | 1956 | switch (code) { |
duke@435 | 1957 | case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; |
duke@435 | 1958 | case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; |
duke@435 | 1959 | case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; |
duke@435 | 1960 | default: ShouldNotReachHere(); |
duke@435 | 1961 | } |
duke@435 | 1962 | } else { |
duke@435 | 1963 | long c = right->as_constant_ptr()->as_jlong(); |
duke@435 | 1964 | assert(c == (int)c && Assembler::is_simm13(c), "out of range"); |
duke@435 | 1965 | int simm13 = (int)c; |
duke@435 | 1966 | switch (code) { |
duke@435 | 1967 | case lir_logic_and: |
duke@435 | 1968 | #ifndef _LP64 |
duke@435 | 1969 | __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); |
duke@435 | 1970 | #endif |
duke@435 | 1971 | __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); |
duke@435 | 1972 | break; |
duke@435 | 1973 | |
duke@435 | 1974 | case lir_logic_or: |
duke@435 | 1975 | #ifndef _LP64 |
duke@435 | 1976 | __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); |
duke@435 | 1977 | #endif |
duke@435 | 1978 | __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); |
duke@435 | 1979 | break; |
duke@435 | 1980 | |
duke@435 | 1981 | case lir_logic_xor: |
duke@435 | 1982 | #ifndef _LP64 |
duke@435 | 1983 | __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); |
duke@435 | 1984 | #endif |
duke@435 | 1985 | __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); |
duke@435 | 1986 | break; |
duke@435 | 1987 | |
duke@435 | 1988 | default: ShouldNotReachHere(); |
duke@435 | 1989 | } |
duke@435 | 1990 | } |
duke@435 | 1991 | } else { |
duke@435 | 1992 | assert(right->is_register(), "right should be in register"); |
duke@435 | 1993 | |
duke@435 | 1994 | if (dest->is_single_cpu()) { |
duke@435 | 1995 | switch (code) { |
duke@435 | 1996 | case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; |
duke@435 | 1997 | case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; |
duke@435 | 1998 | case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; |
duke@435 | 1999 | default: ShouldNotReachHere(); |
duke@435 | 2000 | } |
duke@435 | 2001 | } else { |
duke@435 | 2002 | #ifdef _LP64 |
duke@435 | 2003 | Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : |
duke@435 | 2004 | left->as_register_lo(); |
duke@435 | 2005 | Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : |
duke@435 | 2006 | right->as_register_lo(); |
duke@435 | 2007 | |
duke@435 | 2008 | switch (code) { |
duke@435 | 2009 | case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; |
duke@435 | 2010 | case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; |
duke@435 | 2011 | case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; |
duke@435 | 2012 | default: ShouldNotReachHere(); |
duke@435 | 2013 | } |
duke@435 | 2014 | #else |
duke@435 | 2015 | switch (code) { |
duke@435 | 2016 | case lir_logic_and: |
duke@435 | 2017 | __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); |
duke@435 | 2018 | __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); |
duke@435 | 2019 | break; |
duke@435 | 2020 | |
duke@435 | 2021 | case lir_logic_or: |
duke@435 | 2022 | __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); |
duke@435 | 2023 | __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); |
duke@435 | 2024 | break; |
duke@435 | 2025 | |
duke@435 | 2026 | case lir_logic_xor: |
duke@435 | 2027 | __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); |
duke@435 | 2028 | __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); |
duke@435 | 2029 | break; |
duke@435 | 2030 | |
duke@435 | 2031 | default: ShouldNotReachHere(); |
duke@435 | 2032 | } |
duke@435 | 2033 | #endif |
duke@435 | 2034 | } |
duke@435 | 2035 | } |
duke@435 | 2036 | } |
duke@435 | 2037 | |
duke@435 | 2038 | |
duke@435 | 2039 | int LIR_Assembler::shift_amount(BasicType t) { |
kvn@464 | 2040 | int elem_size = type2aelembytes(t); |
duke@435 | 2041 | switch (elem_size) { |
duke@435 | 2042 | case 1 : return 0; |
duke@435 | 2043 | case 2 : return 1; |
duke@435 | 2044 | case 4 : return 2; |
duke@435 | 2045 | case 8 : return 3; |
duke@435 | 2046 | } |
duke@435 | 2047 | ShouldNotReachHere(); |
duke@435 | 2048 | return -1; |
duke@435 | 2049 | } |
duke@435 | 2050 | |
duke@435 | 2051 | |
duke@435 | 2052 | void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { |
duke@435 | 2053 | assert(exceptionOop->as_register() == Oexception, "should match"); |
duke@435 | 2054 | assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match"); |
duke@435 | 2055 | |
duke@435 | 2056 | info->add_register_oop(exceptionOop); |
duke@435 | 2057 | |
duke@435 | 2058 | if (unwind) { |
duke@435 | 2059 | __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); |
duke@435 | 2060 | __ delayed()->nop(); |
duke@435 | 2061 | } else { |
duke@435 | 2062 | // reuse the debug info from the safepoint poll for the throw op itself |
duke@435 | 2063 | address pc_for_athrow = __ pc(); |
duke@435 | 2064 | int pc_for_athrow_offset = __ offset(); |
duke@435 | 2065 | RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); |
duke@435 | 2066 | __ set((intptr_t)pc_for_athrow, Oissuing_pc, rspec); |
duke@435 | 2067 | add_call_info(pc_for_athrow_offset, info); // for exception handler |
duke@435 | 2068 | |
duke@435 | 2069 | __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); |
duke@435 | 2070 | __ delayed()->nop(); |
duke@435 | 2071 | } |
duke@435 | 2072 | } |
duke@435 | 2073 | |
duke@435 | 2074 | |
duke@435 | 2075 | void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { |
duke@435 | 2076 | Register src = op->src()->as_register(); |
duke@435 | 2077 | Register dst = op->dst()->as_register(); |
duke@435 | 2078 | Register src_pos = op->src_pos()->as_register(); |
duke@435 | 2079 | Register dst_pos = op->dst_pos()->as_register(); |
duke@435 | 2080 | Register length = op->length()->as_register(); |
duke@435 | 2081 | Register tmp = op->tmp()->as_register(); |
duke@435 | 2082 | Register tmp2 = O7; |
duke@435 | 2083 | |
duke@435 | 2084 | int flags = op->flags(); |
duke@435 | 2085 | ciArrayKlass* default_type = op->expected_type(); |
duke@435 | 2086 | BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; |
duke@435 | 2087 | if (basic_type == T_ARRAY) basic_type = T_OBJECT; |
duke@435 | 2088 | |
duke@435 | 2089 | // set up the arraycopy stub information |
duke@435 | 2090 | ArrayCopyStub* stub = op->stub(); |
duke@435 | 2091 | |
duke@435 | 2092 | // always do stub if no type information is available. it's ok if |
duke@435 | 2093 | // the known type isn't loaded since the code sanity checks |
duke@435 | 2094 | // in debug mode and the type isn't required when we know the exact type |
duke@435 | 2095 | // also check that the type is an array type. |
ysr@777 | 2096 | // We also, for now, always call the stub if the barrier set requires a |
ysr@777 | 2097 | // write_ref_pre barrier (which the stub does, but none of the optimized |
ysr@777 | 2098 | // cases currently does). |
ysr@777 | 2099 | if (op->expected_type() == NULL || |
ysr@777 | 2100 | Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) { |
duke@435 | 2101 | __ mov(src, O0); |
duke@435 | 2102 | __ mov(src_pos, O1); |
duke@435 | 2103 | __ mov(dst, O2); |
duke@435 | 2104 | __ mov(dst_pos, O3); |
duke@435 | 2105 | __ mov(length, O4); |
duke@435 | 2106 | __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); |
duke@435 | 2107 | |
duke@435 | 2108 | __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry()); |
duke@435 | 2109 | __ delayed()->nop(); |
duke@435 | 2110 | __ bind(*stub->continuation()); |
duke@435 | 2111 | return; |
duke@435 | 2112 | } |
duke@435 | 2113 | |
duke@435 | 2114 | assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); |
duke@435 | 2115 | |
duke@435 | 2116 | // make sure src and dst are non-null and load array length |
duke@435 | 2117 | if (flags & LIR_OpArrayCopy::src_null_check) { |
duke@435 | 2118 | __ tst(src); |
duke@435 | 2119 | __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); |
duke@435 | 2120 | __ delayed()->nop(); |
duke@435 | 2121 | } |
duke@435 | 2122 | |
duke@435 | 2123 | if (flags & LIR_OpArrayCopy::dst_null_check) { |
duke@435 | 2124 | __ tst(dst); |
duke@435 | 2125 | __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); |
duke@435 | 2126 | __ delayed()->nop(); |
duke@435 | 2127 | } |
duke@435 | 2128 | |
duke@435 | 2129 | if (flags & LIR_OpArrayCopy::src_pos_positive_check) { |
duke@435 | 2130 | // test src_pos register |
duke@435 | 2131 | __ tst(src_pos); |
duke@435 | 2132 | __ br(Assembler::less, false, Assembler::pn, *stub->entry()); |
duke@435 | 2133 | __ delayed()->nop(); |
duke@435 | 2134 | } |
duke@435 | 2135 | |
duke@435 | 2136 | if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { |
duke@435 | 2137 | // test dst_pos register |
duke@435 | 2138 | __ tst(dst_pos); |
duke@435 | 2139 | __ br(Assembler::less, false, Assembler::pn, *stub->entry()); |
duke@435 | 2140 | __ delayed()->nop(); |
duke@435 | 2141 | } |
duke@435 | 2142 | |
duke@435 | 2143 | if (flags & LIR_OpArrayCopy::length_positive_check) { |
duke@435 | 2144 | // make sure length isn't negative |
duke@435 | 2145 | __ tst(length); |
duke@435 | 2146 | __ br(Assembler::less, false, Assembler::pn, *stub->entry()); |
duke@435 | 2147 | __ delayed()->nop(); |
duke@435 | 2148 | } |
duke@435 | 2149 | |
duke@435 | 2150 | if (flags & LIR_OpArrayCopy::src_range_check) { |
duke@435 | 2151 | __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); |
duke@435 | 2152 | __ add(length, src_pos, tmp); |
duke@435 | 2153 | __ cmp(tmp2, tmp); |
duke@435 | 2154 | __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); |
duke@435 | 2155 | __ delayed()->nop(); |
duke@435 | 2156 | } |
duke@435 | 2157 | |
duke@435 | 2158 | if (flags & LIR_OpArrayCopy::dst_range_check) { |
duke@435 | 2159 | __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); |
duke@435 | 2160 | __ add(length, dst_pos, tmp); |
duke@435 | 2161 | __ cmp(tmp2, tmp); |
duke@435 | 2162 | __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); |
duke@435 | 2163 | __ delayed()->nop(); |
duke@435 | 2164 | } |
duke@435 | 2165 | |
duke@435 | 2166 | if (flags & LIR_OpArrayCopy::type_check) { |
duke@435 | 2167 | __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); |
duke@435 | 2168 | __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); |
duke@435 | 2169 | __ cmp(tmp, tmp2); |
duke@435 | 2170 | __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); |
duke@435 | 2171 | __ delayed()->nop(); |
duke@435 | 2172 | } |
duke@435 | 2173 | |
duke@435 | 2174 | #ifdef ASSERT |
duke@435 | 2175 | if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { |
duke@435 | 2176 | // Sanity check the known type with the incoming class. For the |
duke@435 | 2177 | // primitive case the types must match exactly with src.klass and |
duke@435 | 2178 | // dst.klass each exactly matching the default type. For the |
duke@435 | 2179 | // object array case, if no type check is needed then either the |
duke@435 | 2180 | // dst type is exactly the expected type and the src type is a |
duke@435 | 2181 | // subtype which we can't check or src is the same array as dst |
duke@435 | 2182 | // but not necessarily exactly of type default_type. |
duke@435 | 2183 | Label known_ok, halt; |
duke@435 | 2184 | jobject2reg(op->expected_type()->encoding(), tmp); |
duke@435 | 2185 | __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); |
duke@435 | 2186 | if (basic_type != T_OBJECT) { |
duke@435 | 2187 | __ cmp(tmp, tmp2); |
duke@435 | 2188 | __ br(Assembler::notEqual, false, Assembler::pn, halt); |
duke@435 | 2189 | __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); |
duke@435 | 2190 | __ cmp(tmp, tmp2); |
duke@435 | 2191 | __ br(Assembler::equal, false, Assembler::pn, known_ok); |
duke@435 | 2192 | __ delayed()->nop(); |
duke@435 | 2193 | } else { |
duke@435 | 2194 | __ cmp(tmp, tmp2); |
duke@435 | 2195 | __ br(Assembler::equal, false, Assembler::pn, known_ok); |
duke@435 | 2196 | __ delayed()->cmp(src, dst); |
duke@435 | 2197 | __ br(Assembler::equal, false, Assembler::pn, known_ok); |
duke@435 | 2198 | __ delayed()->nop(); |
duke@435 | 2199 | } |
duke@435 | 2200 | __ bind(halt); |
duke@435 | 2201 | __ stop("incorrect type information in arraycopy"); |
duke@435 | 2202 | __ bind(known_ok); |
duke@435 | 2203 | } |
duke@435 | 2204 | #endif |
duke@435 | 2205 | |
duke@435 | 2206 | int shift = shift_amount(basic_type); |
duke@435 | 2207 | |
duke@435 | 2208 | Register src_ptr = O0; |
duke@435 | 2209 | Register dst_ptr = O1; |
duke@435 | 2210 | Register len = O2; |
duke@435 | 2211 | |
duke@435 | 2212 | __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); |
duke@435 | 2213 | if (shift == 0) { |
duke@435 | 2214 | __ add(src_ptr, src_pos, src_ptr); |
duke@435 | 2215 | } else { |
duke@435 | 2216 | __ sll(src_pos, shift, tmp); |
duke@435 | 2217 | __ add(src_ptr, tmp, src_ptr); |
duke@435 | 2218 | } |
duke@435 | 2219 | |
duke@435 | 2220 | __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); |
duke@435 | 2221 | if (shift == 0) { |
duke@435 | 2222 | __ add(dst_ptr, dst_pos, dst_ptr); |
duke@435 | 2223 | } else { |
duke@435 | 2224 | __ sll(dst_pos, shift, tmp); |
duke@435 | 2225 | __ add(dst_ptr, tmp, dst_ptr); |
duke@435 | 2226 | } |
duke@435 | 2227 | |
duke@435 | 2228 | if (basic_type != T_OBJECT) { |
duke@435 | 2229 | if (shift == 0) { |
duke@435 | 2230 | __ mov(length, len); |
duke@435 | 2231 | } else { |
duke@435 | 2232 | __ sll(length, shift, len); |
duke@435 | 2233 | } |
duke@435 | 2234 | __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy)); |
duke@435 | 2235 | } else { |
duke@435 | 2236 | // oop_arraycopy takes a length in number of elements, so don't scale it. |
duke@435 | 2237 | __ mov(length, len); |
duke@435 | 2238 | __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy)); |
duke@435 | 2239 | } |
duke@435 | 2240 | |
duke@435 | 2241 | __ bind(*stub->continuation()); |
duke@435 | 2242 | } |
duke@435 | 2243 | |
duke@435 | 2244 | |
duke@435 | 2245 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
duke@435 | 2246 | if (dest->is_single_cpu()) { |
duke@435 | 2247 | #ifdef _LP64 |
duke@435 | 2248 | if (left->type() == T_OBJECT) { |
duke@435 | 2249 | switch (code) { |
duke@435 | 2250 | case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; |
duke@435 | 2251 | case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; |
duke@435 | 2252 | case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; |
duke@435 | 2253 | default: ShouldNotReachHere(); |
duke@435 | 2254 | } |
duke@435 | 2255 | } else |
duke@435 | 2256 | #endif |
duke@435 | 2257 | switch (code) { |
duke@435 | 2258 | case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; |
duke@435 | 2259 | case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; |
duke@435 | 2260 | case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; |
duke@435 | 2261 | default: ShouldNotReachHere(); |
duke@435 | 2262 | } |
duke@435 | 2263 | } else { |
duke@435 | 2264 | #ifdef _LP64 |
duke@435 | 2265 | switch (code) { |
duke@435 | 2266 | case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; |
duke@435 | 2267 | case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; |
duke@435 | 2268 | case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; |
duke@435 | 2269 | default: ShouldNotReachHere(); |
duke@435 | 2270 | } |
duke@435 | 2271 | #else |
duke@435 | 2272 | switch (code) { |
duke@435 | 2273 | case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; |
duke@435 | 2274 | case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; |
duke@435 | 2275 | case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; |
duke@435 | 2276 | default: ShouldNotReachHere(); |
duke@435 | 2277 | } |
duke@435 | 2278 | #endif |
duke@435 | 2279 | } |
duke@435 | 2280 | } |
duke@435 | 2281 | |
duke@435 | 2282 | |
duke@435 | 2283 | void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { |
duke@435 | 2284 | #ifdef _LP64 |
duke@435 | 2285 | if (left->type() == T_OBJECT) { |
duke@435 | 2286 | count = count & 63; // shouldn't shift by more than sizeof(intptr_t) |
duke@435 | 2287 | Register l = left->as_register(); |
duke@435 | 2288 | Register d = dest->as_register_lo(); |
duke@435 | 2289 | switch (code) { |
duke@435 | 2290 | case lir_shl: __ sllx (l, count, d); break; |
duke@435 | 2291 | case lir_shr: __ srax (l, count, d); break; |
duke@435 | 2292 | case lir_ushr: __ srlx (l, count, d); break; |
duke@435 | 2293 | default: ShouldNotReachHere(); |
duke@435 | 2294 | } |
duke@435 | 2295 | return; |
duke@435 | 2296 | } |
duke@435 | 2297 | #endif |
duke@435 | 2298 | |
duke@435 | 2299 | if (dest->is_single_cpu()) { |
duke@435 | 2300 | count = count & 0x1F; // Java spec |
duke@435 | 2301 | switch (code) { |
duke@435 | 2302 | case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; |
duke@435 | 2303 | case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; |
duke@435 | 2304 | case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; |
duke@435 | 2305 | default: ShouldNotReachHere(); |
duke@435 | 2306 | } |
duke@435 | 2307 | } else if (dest->is_double_cpu()) { |
duke@435 | 2308 | count = count & 63; // Java spec |
duke@435 | 2309 | switch (code) { |
duke@435 | 2310 | case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; |
duke@435 | 2311 | case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; |
duke@435 | 2312 | case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; |
duke@435 | 2313 | default: ShouldNotReachHere(); |
duke@435 | 2314 | } |
duke@435 | 2315 | } else { |
duke@435 | 2316 | ShouldNotReachHere(); |
duke@435 | 2317 | } |
duke@435 | 2318 | } |
duke@435 | 2319 | |
duke@435 | 2320 | |
duke@435 | 2321 | void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { |
duke@435 | 2322 | assert(op->tmp1()->as_register() == G1 && |
duke@435 | 2323 | op->tmp2()->as_register() == G3 && |
duke@435 | 2324 | op->tmp3()->as_register() == G4 && |
duke@435 | 2325 | op->obj()->as_register() == O0 && |
duke@435 | 2326 | op->klass()->as_register() == G5, "must be"); |
duke@435 | 2327 | if (op->init_check()) { |
duke@435 | 2328 | __ ld(op->klass()->as_register(), |
duke@435 | 2329 | instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc), |
duke@435 | 2330 | op->tmp1()->as_register()); |
duke@435 | 2331 | add_debug_info_for_null_check_here(op->stub()->info()); |
duke@435 | 2332 | __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized); |
duke@435 | 2333 | __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); |
duke@435 | 2334 | __ delayed()->nop(); |
duke@435 | 2335 | } |
duke@435 | 2336 | __ allocate_object(op->obj()->as_register(), |
duke@435 | 2337 | op->tmp1()->as_register(), |
duke@435 | 2338 | op->tmp2()->as_register(), |
duke@435 | 2339 | op->tmp3()->as_register(), |
duke@435 | 2340 | op->header_size(), |
duke@435 | 2341 | op->object_size(), |
duke@435 | 2342 | op->klass()->as_register(), |
duke@435 | 2343 | *op->stub()->entry()); |
duke@435 | 2344 | __ bind(*op->stub()->continuation()); |
duke@435 | 2345 | __ verify_oop(op->obj()->as_register()); |
duke@435 | 2346 | } |
duke@435 | 2347 | |
duke@435 | 2348 | |
duke@435 | 2349 | void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { |
duke@435 | 2350 | assert(op->tmp1()->as_register() == G1 && |
duke@435 | 2351 | op->tmp2()->as_register() == G3 && |
duke@435 | 2352 | op->tmp3()->as_register() == G4 && |
duke@435 | 2353 | op->tmp4()->as_register() == O1 && |
duke@435 | 2354 | op->klass()->as_register() == G5, "must be"); |
duke@435 | 2355 | if (UseSlowPath || |
duke@435 | 2356 | (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || |
duke@435 | 2357 | (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { |
duke@435 | 2358 | __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry()); |
duke@435 | 2359 | __ delayed()->nop(); |
duke@435 | 2360 | } else { |
duke@435 | 2361 | __ allocate_array(op->obj()->as_register(), |
duke@435 | 2362 | op->len()->as_register(), |
duke@435 | 2363 | op->tmp1()->as_register(), |
duke@435 | 2364 | op->tmp2()->as_register(), |
duke@435 | 2365 | op->tmp3()->as_register(), |
duke@435 | 2366 | arrayOopDesc::header_size(op->type()), |
kvn@464 | 2367 | type2aelembytes(op->type()), |
duke@435 | 2368 | op->klass()->as_register(), |
duke@435 | 2369 | *op->stub()->entry()); |
duke@435 | 2370 | } |
duke@435 | 2371 | __ bind(*op->stub()->continuation()); |
duke@435 | 2372 | } |
duke@435 | 2373 | |
duke@435 | 2374 | |
duke@435 | 2375 | void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
duke@435 | 2376 | LIR_Code code = op->code(); |
duke@435 | 2377 | if (code == lir_store_check) { |
duke@435 | 2378 | Register value = op->object()->as_register(); |
duke@435 | 2379 | Register array = op->array()->as_register(); |
duke@435 | 2380 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 2381 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 2382 | Register Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 2383 | |
duke@435 | 2384 | __ verify_oop(value); |
duke@435 | 2385 | |
duke@435 | 2386 | CodeStub* stub = op->stub(); |
duke@435 | 2387 | Label done; |
duke@435 | 2388 | __ cmp(value, 0); |
duke@435 | 2389 | __ br(Assembler::equal, false, Assembler::pn, done); |
duke@435 | 2390 | __ delayed()->nop(); |
duke@435 | 2391 | load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception()); |
duke@435 | 2392 | load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); |
duke@435 | 2393 | |
duke@435 | 2394 | // get instance klass |
duke@435 | 2395 | load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL); |
jrose@1079 | 2396 | // perform the fast part of the checking logic |
jrose@1079 | 2397 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL); |
jrose@1079 | 2398 | |
jrose@1079 | 2399 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
jrose@1079 | 2400 | assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
duke@435 | 2401 | __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
duke@435 | 2402 | __ delayed()->nop(); |
duke@435 | 2403 | __ cmp(G3, 0); |
duke@435 | 2404 | __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); |
duke@435 | 2405 | __ delayed()->nop(); |
duke@435 | 2406 | __ bind(done); |
duke@435 | 2407 | } else if (op->code() == lir_checkcast) { |
duke@435 | 2408 | // we always need a stub for the failure case. |
duke@435 | 2409 | CodeStub* stub = op->stub(); |
duke@435 | 2410 | Register obj = op->object()->as_register(); |
duke@435 | 2411 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 2412 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 2413 | Register dst = op->result_opr()->as_register(); |
duke@435 | 2414 | Register Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 2415 | ciKlass* k = op->klass(); |
duke@435 | 2416 | |
duke@435 | 2417 | if (obj == k_RInfo) { |
duke@435 | 2418 | k_RInfo = klass_RInfo; |
duke@435 | 2419 | klass_RInfo = obj; |
duke@435 | 2420 | } |
duke@435 | 2421 | if (op->profiled_method() != NULL) { |
duke@435 | 2422 | ciMethod* method = op->profiled_method(); |
duke@435 | 2423 | int bci = op->profiled_bci(); |
duke@435 | 2424 | |
duke@435 | 2425 | // We need two temporaries to perform this operation on SPARC, |
duke@435 | 2426 | // so to keep things simple we perform a redundant test here |
duke@435 | 2427 | Label profile_done; |
duke@435 | 2428 | __ cmp(obj, 0); |
duke@435 | 2429 | __ br(Assembler::notEqual, false, Assembler::pn, profile_done); |
duke@435 | 2430 | __ delayed()->nop(); |
duke@435 | 2431 | // Object is null; update methodDataOop |
duke@435 | 2432 | ciMethodData* md = method->method_data(); |
duke@435 | 2433 | if (md == NULL) { |
duke@435 | 2434 | bailout("out of memory building methodDataOop"); |
duke@435 | 2435 | return; |
duke@435 | 2436 | } |
duke@435 | 2437 | ciProfileData* data = md->bci_to_data(bci); |
duke@435 | 2438 | assert(data != NULL, "need data for checkcast"); |
duke@435 | 2439 | assert(data->is_BitData(), "need BitData for checkcast"); |
duke@435 | 2440 | Register mdo = k_RInfo; |
duke@435 | 2441 | Register data_val = Rtmp1; |
duke@435 | 2442 | jobject2reg(md->encoding(), mdo); |
duke@435 | 2443 | |
duke@435 | 2444 | int mdo_offset_bias = 0; |
duke@435 | 2445 | if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { |
duke@435 | 2446 | // The offset is large so bias the mdo by the base of the slot so |
duke@435 | 2447 | // that the ld can use simm13s to reference the slots of the data |
duke@435 | 2448 | mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); |
duke@435 | 2449 | __ set(mdo_offset_bias, data_val); |
duke@435 | 2450 | __ add(mdo, data_val, mdo); |
duke@435 | 2451 | } |
duke@435 | 2452 | |
duke@435 | 2453 | |
duke@435 | 2454 | Address flags_addr(mdo, 0, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); |
duke@435 | 2455 | __ ldub(flags_addr, data_val); |
duke@435 | 2456 | __ or3(data_val, BitData::null_seen_byte_constant(), data_val); |
duke@435 | 2457 | __ stb(data_val, flags_addr); |
duke@435 | 2458 | __ bind(profile_done); |
duke@435 | 2459 | } |
duke@435 | 2460 | |
duke@435 | 2461 | Label done; |
duke@435 | 2462 | // patching may screw with our temporaries on sparc, |
duke@435 | 2463 | // so let's do it before loading the class |
duke@435 | 2464 | if (k->is_loaded()) { |
duke@435 | 2465 | jobject2reg(k->encoding(), k_RInfo); |
duke@435 | 2466 | } else { |
duke@435 | 2467 | jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
duke@435 | 2468 | } |
duke@435 | 2469 | assert(obj != k_RInfo, "must be different"); |
duke@435 | 2470 | __ cmp(obj, 0); |
duke@435 | 2471 | __ br(Assembler::equal, false, Assembler::pn, done); |
duke@435 | 2472 | __ delayed()->nop(); |
duke@435 | 2473 | |
duke@435 | 2474 | // get object class |
duke@435 | 2475 | // not a safepoint as obj null check happens earlier |
duke@435 | 2476 | load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); |
duke@435 | 2477 | if (op->fast_check()) { |
duke@435 | 2478 | assert_different_registers(klass_RInfo, k_RInfo); |
duke@435 | 2479 | __ cmp(k_RInfo, klass_RInfo); |
duke@435 | 2480 | __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); |
duke@435 | 2481 | __ delayed()->nop(); |
duke@435 | 2482 | __ bind(done); |
duke@435 | 2483 | } else { |
jrose@1079 | 2484 | bool need_slow_path = true; |
duke@435 | 2485 | if (k->is_loaded()) { |
jrose@1079 | 2486 | if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()) |
jrose@1079 | 2487 | need_slow_path = false; |
jrose@1079 | 2488 | // perform the fast part of the checking logic |
jrose@1079 | 2489 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, |
jrose@1079 | 2490 | (need_slow_path ? &done : NULL), |
jrose@1079 | 2491 | stub->entry(), NULL, |
jrose@1100 | 2492 | RegisterOrConstant(k->super_check_offset())); |
duke@435 | 2493 | } else { |
jrose@1079 | 2494 | // perform the fast part of the checking logic |
jrose@1079 | 2495 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, |
jrose@1079 | 2496 | &done, stub->entry(), NULL); |
jrose@1079 | 2497 | } |
jrose@1079 | 2498 | if (need_slow_path) { |
jrose@1079 | 2499 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
jrose@1079 | 2500 | assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
duke@435 | 2501 | __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
duke@435 | 2502 | __ delayed()->nop(); |
duke@435 | 2503 | __ cmp(G3, 0); |
duke@435 | 2504 | __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); |
duke@435 | 2505 | __ delayed()->nop(); |
duke@435 | 2506 | } |
jrose@1079 | 2507 | __ bind(done); |
duke@435 | 2508 | } |
duke@435 | 2509 | __ mov(obj, dst); |
duke@435 | 2510 | } else if (code == lir_instanceof) { |
duke@435 | 2511 | Register obj = op->object()->as_register(); |
duke@435 | 2512 | Register k_RInfo = op->tmp1()->as_register(); |
duke@435 | 2513 | Register klass_RInfo = op->tmp2()->as_register(); |
duke@435 | 2514 | Register dst = op->result_opr()->as_register(); |
duke@435 | 2515 | Register Rtmp1 = op->tmp3()->as_register(); |
duke@435 | 2516 | ciKlass* k = op->klass(); |
duke@435 | 2517 | |
duke@435 | 2518 | Label done; |
duke@435 | 2519 | if (obj == k_RInfo) { |
duke@435 | 2520 | k_RInfo = klass_RInfo; |
duke@435 | 2521 | klass_RInfo = obj; |
duke@435 | 2522 | } |
duke@435 | 2523 | // patching may screw with our temporaries on sparc, |
duke@435 | 2524 | // so let's do it before loading the class |
duke@435 | 2525 | if (k->is_loaded()) { |
duke@435 | 2526 | jobject2reg(k->encoding(), k_RInfo); |
duke@435 | 2527 | } else { |
duke@435 | 2528 | jobject2reg_with_patching(k_RInfo, op->info_for_patch()); |
duke@435 | 2529 | } |
duke@435 | 2530 | assert(obj != k_RInfo, "must be different"); |
duke@435 | 2531 | __ cmp(obj, 0); |
duke@435 | 2532 | __ br(Assembler::equal, true, Assembler::pn, done); |
duke@435 | 2533 | __ delayed()->set(0, dst); |
duke@435 | 2534 | |
duke@435 | 2535 | // get object class |
duke@435 | 2536 | // not a safepoint as obj null check happens earlier |
duke@435 | 2537 | load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); |
duke@435 | 2538 | if (op->fast_check()) { |
duke@435 | 2539 | __ cmp(k_RInfo, klass_RInfo); |
duke@435 | 2540 | __ br(Assembler::equal, true, Assembler::pt, done); |
duke@435 | 2541 | __ delayed()->set(1, dst); |
duke@435 | 2542 | __ set(0, dst); |
duke@435 | 2543 | __ bind(done); |
duke@435 | 2544 | } else { |
jrose@1079 | 2545 | bool need_slow_path = true; |
duke@435 | 2546 | if (k->is_loaded()) { |
jrose@1079 | 2547 | if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()) |
jrose@1079 | 2548 | need_slow_path = false; |
jrose@1079 | 2549 | // perform the fast part of the checking logic |
jrose@1079 | 2550 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg, |
jrose@1079 | 2551 | (need_slow_path ? &done : NULL), |
jrose@1079 | 2552 | (need_slow_path ? &done : NULL), NULL, |
jrose@1100 | 2553 | RegisterOrConstant(k->super_check_offset()), |
jrose@1079 | 2554 | dst); |
duke@435 | 2555 | } else { |
duke@435 | 2556 | assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); |
jrose@1079 | 2557 | // perform the fast part of the checking logic |
jrose@1079 | 2558 | __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst, |
jrose@1079 | 2559 | &done, &done, NULL, |
jrose@1100 | 2560 | RegisterOrConstant(-1), |
jrose@1079 | 2561 | dst); |
jrose@1079 | 2562 | } |
jrose@1079 | 2563 | if (need_slow_path) { |
jrose@1079 | 2564 | // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
jrose@1079 | 2565 | assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
duke@435 | 2566 | __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
duke@435 | 2567 | __ delayed()->nop(); |
duke@435 | 2568 | __ mov(G3, dst); |
duke@435 | 2569 | } |
jrose@1079 | 2570 | __ bind(done); |
duke@435 | 2571 | } |
duke@435 | 2572 | } else { |
duke@435 | 2573 | ShouldNotReachHere(); |
duke@435 | 2574 | } |
duke@435 | 2575 | |
duke@435 | 2576 | } |
duke@435 | 2577 | |
duke@435 | 2578 | |
duke@435 | 2579 | void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { |
duke@435 | 2580 | if (op->code() == lir_cas_long) { |
duke@435 | 2581 | assert(VM_Version::supports_cx8(), "wrong machine"); |
duke@435 | 2582 | Register addr = op->addr()->as_pointer_register(); |
duke@435 | 2583 | Register cmp_value_lo = op->cmp_value()->as_register_lo(); |
duke@435 | 2584 | Register cmp_value_hi = op->cmp_value()->as_register_hi(); |
duke@435 | 2585 | Register new_value_lo = op->new_value()->as_register_lo(); |
duke@435 | 2586 | Register new_value_hi = op->new_value()->as_register_hi(); |
duke@435 | 2587 | Register t1 = op->tmp1()->as_register(); |
duke@435 | 2588 | Register t2 = op->tmp2()->as_register(); |
duke@435 | 2589 | #ifdef _LP64 |
duke@435 | 2590 | __ mov(cmp_value_lo, t1); |
duke@435 | 2591 | __ mov(new_value_lo, t2); |
duke@435 | 2592 | #else |
duke@435 | 2593 | // move high and low halves of long values into single registers |
duke@435 | 2594 | __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg |
duke@435 | 2595 | __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half |
duke@435 | 2596 | __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value |
duke@435 | 2597 | __ sllx(new_value_hi, 32, t2); |
duke@435 | 2598 | __ srl(new_value_lo, 0, new_value_lo); |
duke@435 | 2599 | __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap |
duke@435 | 2600 | #endif |
duke@435 | 2601 | // perform the compare and swap operation |
duke@435 | 2602 | __ casx(addr, t1, t2); |
duke@435 | 2603 | // generate condition code - if the swap succeeded, t2 ("new value" reg) was |
duke@435 | 2604 | // overwritten with the original value in "addr" and will be equal to t1. |
duke@435 | 2605 | __ cmp(t1, t2); |
duke@435 | 2606 | |
duke@435 | 2607 | } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { |
duke@435 | 2608 | Register addr = op->addr()->as_pointer_register(); |
duke@435 | 2609 | Register cmp_value = op->cmp_value()->as_register(); |
duke@435 | 2610 | Register new_value = op->new_value()->as_register(); |
duke@435 | 2611 | Register t1 = op->tmp1()->as_register(); |
duke@435 | 2612 | Register t2 = op->tmp2()->as_register(); |
duke@435 | 2613 | __ mov(cmp_value, t1); |
duke@435 | 2614 | __ mov(new_value, t2); |
duke@435 | 2615 | #ifdef _LP64 |
duke@435 | 2616 | if (op->code() == lir_cas_obj) { |
duke@435 | 2617 | __ casx(addr, t1, t2); |
duke@435 | 2618 | } else |
duke@435 | 2619 | #endif |
duke@435 | 2620 | { |
duke@435 | 2621 | __ cas(addr, t1, t2); |
duke@435 | 2622 | } |
duke@435 | 2623 | __ cmp(t1, t2); |
duke@435 | 2624 | } else { |
duke@435 | 2625 | Unimplemented(); |
duke@435 | 2626 | } |
duke@435 | 2627 | } |
duke@435 | 2628 | |
duke@435 | 2629 | void LIR_Assembler::set_24bit_FPU() { |
duke@435 | 2630 | Unimplemented(); |
duke@435 | 2631 | } |
duke@435 | 2632 | |
duke@435 | 2633 | |
duke@435 | 2634 | void LIR_Assembler::reset_FPU() { |
duke@435 | 2635 | Unimplemented(); |
duke@435 | 2636 | } |
duke@435 | 2637 | |
duke@435 | 2638 | |
duke@435 | 2639 | void LIR_Assembler::breakpoint() { |
duke@435 | 2640 | __ breakpoint_trap(); |
duke@435 | 2641 | } |
duke@435 | 2642 | |
duke@435 | 2643 | |
duke@435 | 2644 | void LIR_Assembler::push(LIR_Opr opr) { |
duke@435 | 2645 | Unimplemented(); |
duke@435 | 2646 | } |
duke@435 | 2647 | |
duke@435 | 2648 | |
duke@435 | 2649 | void LIR_Assembler::pop(LIR_Opr opr) { |
duke@435 | 2650 | Unimplemented(); |
duke@435 | 2651 | } |
duke@435 | 2652 | |
duke@435 | 2653 | |
duke@435 | 2654 | void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { |
duke@435 | 2655 | Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); |
duke@435 | 2656 | Register dst = dst_opr->as_register(); |
duke@435 | 2657 | Register reg = mon_addr.base(); |
duke@435 | 2658 | int offset = mon_addr.disp(); |
duke@435 | 2659 | // compute pointer to BasicLock |
duke@435 | 2660 | if (mon_addr.is_simm13()) { |
duke@435 | 2661 | __ add(reg, offset, dst); |
duke@435 | 2662 | } else { |
duke@435 | 2663 | __ set(offset, dst); |
duke@435 | 2664 | __ add(dst, reg, dst); |
duke@435 | 2665 | } |
duke@435 | 2666 | } |
duke@435 | 2667 | |
duke@435 | 2668 | |
duke@435 | 2669 | void LIR_Assembler::emit_lock(LIR_OpLock* op) { |
duke@435 | 2670 | Register obj = op->obj_opr()->as_register(); |
duke@435 | 2671 | Register hdr = op->hdr_opr()->as_register(); |
duke@435 | 2672 | Register lock = op->lock_opr()->as_register(); |
duke@435 | 2673 | |
duke@435 | 2674 | // obj may not be an oop |
duke@435 | 2675 | if (op->code() == lir_lock) { |
duke@435 | 2676 | MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); |
duke@435 | 2677 | if (UseFastLocking) { |
duke@435 | 2678 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 2679 | // add debug info for NullPointerException only if one is possible |
duke@435 | 2680 | if (op->info() != NULL) { |
duke@435 | 2681 | add_debug_info_for_null_check_here(op->info()); |
duke@435 | 2682 | } |
duke@435 | 2683 | __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); |
duke@435 | 2684 | } else { |
duke@435 | 2685 | // always do slow locking |
duke@435 | 2686 | // note: the slow locking code could be inlined here, however if we use |
duke@435 | 2687 | // slow locking, speed doesn't matter anyway and this solution is |
duke@435 | 2688 | // simpler and requires less duplicated code - additionally, the |
duke@435 | 2689 | // slow locking code is the same in either case which simplifies |
duke@435 | 2690 | // debugging |
duke@435 | 2691 | __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); |
duke@435 | 2692 | __ delayed()->nop(); |
duke@435 | 2693 | } |
duke@435 | 2694 | } else { |
duke@435 | 2695 | assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); |
duke@435 | 2696 | if (UseFastLocking) { |
duke@435 | 2697 | assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); |
duke@435 | 2698 | __ unlock_object(hdr, obj, lock, *op->stub()->entry()); |
duke@435 | 2699 | } else { |
duke@435 | 2700 | // always do slow unlocking |
duke@435 | 2701 | // note: the slow unlocking code could be inlined here, however if we use |
duke@435 | 2702 | // slow unlocking, speed doesn't matter anyway and this solution is |
duke@435 | 2703 | // simpler and requires less duplicated code - additionally, the |
duke@435 | 2704 | // slow unlocking code is the same in either case which simplifies |
duke@435 | 2705 | // debugging |
duke@435 | 2706 | __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); |
duke@435 | 2707 | __ delayed()->nop(); |
duke@435 | 2708 | } |
duke@435 | 2709 | } |
duke@435 | 2710 | __ bind(*op->stub()->continuation()); |
duke@435 | 2711 | } |
duke@435 | 2712 | |
duke@435 | 2713 | |
duke@435 | 2714 | void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { |
duke@435 | 2715 | ciMethod* method = op->profiled_method(); |
duke@435 | 2716 | int bci = op->profiled_bci(); |
duke@435 | 2717 | |
duke@435 | 2718 | // Update counter for all call types |
duke@435 | 2719 | ciMethodData* md = method->method_data(); |
duke@435 | 2720 | if (md == NULL) { |
duke@435 | 2721 | bailout("out of memory building methodDataOop"); |
duke@435 | 2722 | return; |
duke@435 | 2723 | } |
duke@435 | 2724 | ciProfileData* data = md->bci_to_data(bci); |
duke@435 | 2725 | assert(data->is_CounterData(), "need CounterData for calls"); |
duke@435 | 2726 | assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); |
duke@435 | 2727 | assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); |
duke@435 | 2728 | Register mdo = op->mdo()->as_register(); |
duke@435 | 2729 | Register tmp1 = op->tmp1()->as_register(); |
duke@435 | 2730 | jobject2reg(md->encoding(), mdo); |
duke@435 | 2731 | int mdo_offset_bias = 0; |
duke@435 | 2732 | if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + |
duke@435 | 2733 | data->size_in_bytes())) { |
duke@435 | 2734 | // The offset is large so bias the mdo by the base of the slot so |
duke@435 | 2735 | // that the ld can use simm13s to reference the slots of the data |
duke@435 | 2736 | mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); |
duke@435 | 2737 | __ set(mdo_offset_bias, O7); |
duke@435 | 2738 | __ add(mdo, O7, mdo); |
duke@435 | 2739 | } |
duke@435 | 2740 | |
duke@435 | 2741 | Address counter_addr(mdo, 0, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
duke@435 | 2742 | __ lduw(counter_addr, tmp1); |
duke@435 | 2743 | __ add(tmp1, DataLayout::counter_increment, tmp1); |
duke@435 | 2744 | __ stw(tmp1, counter_addr); |
duke@435 | 2745 | Bytecodes::Code bc = method->java_code_at_bci(bci); |
duke@435 | 2746 | // Perform additional virtual call profiling for invokevirtual and |
duke@435 | 2747 | // invokeinterface bytecodes |
duke@435 | 2748 | if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && |
duke@435 | 2749 | Tier1ProfileVirtualCalls) { |
duke@435 | 2750 | assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
duke@435 | 2751 | Register recv = op->recv()->as_register(); |
duke@435 | 2752 | assert_different_registers(mdo, tmp1, recv); |
duke@435 | 2753 | assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); |
duke@435 | 2754 | ciKlass* known_klass = op->known_holder(); |
duke@435 | 2755 | if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { |
duke@435 | 2756 | // We know the type that will be seen at this call site; we can |
duke@435 | 2757 | // statically update the methodDataOop rather than needing to do |
duke@435 | 2758 | // dynamic tests on the receiver type |
duke@435 | 2759 | |
duke@435 | 2760 | // NOTE: we should probably put a lock around this search to |
duke@435 | 2761 | // avoid collisions by concurrent compilations |
duke@435 | 2762 | ciVirtualCallData* vc_data = (ciVirtualCallData*) data; |
duke@435 | 2763 | uint i; |
duke@435 | 2764 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 2765 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 2766 | if (known_klass->equals(receiver)) { |
duke@435 | 2767 | Address data_addr(mdo, 0, md->byte_offset_of_slot(data, |
duke@435 | 2768 | VirtualCallData::receiver_count_offset(i)) - |
duke@435 | 2769 | mdo_offset_bias); |
duke@435 | 2770 | __ lduw(data_addr, tmp1); |
duke@435 | 2771 | __ add(tmp1, DataLayout::counter_increment, tmp1); |
duke@435 | 2772 | __ stw(tmp1, data_addr); |
duke@435 | 2773 | return; |
duke@435 | 2774 | } |
duke@435 | 2775 | } |
duke@435 | 2776 | |
duke@435 | 2777 | // Receiver type not found in profile data; select an empty slot |
duke@435 | 2778 | |
duke@435 | 2779 | // Note that this is less efficient than it should be because it |
duke@435 | 2780 | // always does a write to the receiver part of the |
duke@435 | 2781 | // VirtualCallData rather than just the first time |
duke@435 | 2782 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 2783 | ciKlass* receiver = vc_data->receiver(i); |
duke@435 | 2784 | if (receiver == NULL) { |
duke@435 | 2785 | Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
duke@435 | 2786 | mdo_offset_bias); |
duke@435 | 2787 | jobject2reg(known_klass->encoding(), tmp1); |
duke@435 | 2788 | __ st_ptr(tmp1, recv_addr); |
duke@435 | 2789 | Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
duke@435 | 2790 | mdo_offset_bias); |
duke@435 | 2791 | __ lduw(data_addr, tmp1); |
duke@435 | 2792 | __ add(tmp1, DataLayout::counter_increment, tmp1); |
duke@435 | 2793 | __ stw(tmp1, data_addr); |
duke@435 | 2794 | return; |
duke@435 | 2795 | } |
duke@435 | 2796 | } |
duke@435 | 2797 | } else { |
duke@435 | 2798 | load(Address(recv, 0, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); |
duke@435 | 2799 | Label update_done; |
duke@435 | 2800 | uint i; |
duke@435 | 2801 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 2802 | Label next_test; |
duke@435 | 2803 | // See if the receiver is receiver[n]. |
duke@435 | 2804 | Address receiver_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
duke@435 | 2805 | mdo_offset_bias); |
duke@435 | 2806 | __ ld_ptr(receiver_addr, tmp1); |
duke@435 | 2807 | __ verify_oop(tmp1); |
duke@435 | 2808 | __ cmp(recv, tmp1); |
duke@435 | 2809 | __ brx(Assembler::notEqual, false, Assembler::pt, next_test); |
duke@435 | 2810 | __ delayed()->nop(); |
duke@435 | 2811 | Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
duke@435 | 2812 | mdo_offset_bias); |
duke@435 | 2813 | __ lduw(data_addr, tmp1); |
duke@435 | 2814 | __ add(tmp1, DataLayout::counter_increment, tmp1); |
duke@435 | 2815 | __ stw(tmp1, data_addr); |
duke@435 | 2816 | __ br(Assembler::always, false, Assembler::pt, update_done); |
duke@435 | 2817 | __ delayed()->nop(); |
duke@435 | 2818 | __ bind(next_test); |
duke@435 | 2819 | } |
duke@435 | 2820 | |
duke@435 | 2821 | // Didn't find receiver; find next empty slot and fill it in |
duke@435 | 2822 | for (i = 0; i < VirtualCallData::row_limit(); i++) { |
duke@435 | 2823 | Label next_test; |
duke@435 | 2824 | Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
duke@435 | 2825 | mdo_offset_bias); |
duke@435 | 2826 | load(recv_addr, tmp1, T_OBJECT); |
duke@435 | 2827 | __ tst(tmp1); |
duke@435 | 2828 | __ brx(Assembler::notEqual, false, Assembler::pt, next_test); |
duke@435 | 2829 | __ delayed()->nop(); |
duke@435 | 2830 | __ st_ptr(recv, recv_addr); |
duke@435 | 2831 | __ set(DataLayout::counter_increment, tmp1); |
duke@435 | 2832 | __ st_ptr(tmp1, Address(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
duke@435 | 2833 | mdo_offset_bias)); |
duke@435 | 2834 | if (i < (VirtualCallData::row_limit() - 1)) { |
duke@435 | 2835 | __ br(Assembler::always, false, Assembler::pt, update_done); |
duke@435 | 2836 | __ delayed()->nop(); |
duke@435 | 2837 | } |
duke@435 | 2838 | __ bind(next_test); |
duke@435 | 2839 | } |
duke@435 | 2840 | |
duke@435 | 2841 | __ bind(update_done); |
duke@435 | 2842 | } |
duke@435 | 2843 | } |
duke@435 | 2844 | } |
duke@435 | 2845 | |
duke@435 | 2846 | |
duke@435 | 2847 | void LIR_Assembler::align_backward_branch_target() { |
duke@435 | 2848 | __ align(16); |
duke@435 | 2849 | } |
duke@435 | 2850 | |
duke@435 | 2851 | |
duke@435 | 2852 | void LIR_Assembler::emit_delay(LIR_OpDelay* op) { |
duke@435 | 2853 | // make sure we are expecting a delay |
duke@435 | 2854 | // this has the side effect of clearing the delay state |
duke@435 | 2855 | // so we can use _masm instead of _masm->delayed() to do the |
duke@435 | 2856 | // code generation. |
duke@435 | 2857 | __ delayed(); |
duke@435 | 2858 | |
duke@435 | 2859 | // make sure we only emit one instruction |
duke@435 | 2860 | int offset = code_offset(); |
duke@435 | 2861 | op->delay_op()->emit_code(this); |
duke@435 | 2862 | #ifdef ASSERT |
duke@435 | 2863 | if (code_offset() - offset != NativeInstruction::nop_instruction_size) { |
duke@435 | 2864 | op->delay_op()->print(); |
duke@435 | 2865 | } |
duke@435 | 2866 | assert(code_offset() - offset == NativeInstruction::nop_instruction_size, |
duke@435 | 2867 | "only one instruction can go in a delay slot"); |
duke@435 | 2868 | #endif |
duke@435 | 2869 | |
duke@435 | 2870 | // we may also be emitting the call info for the instruction |
duke@435 | 2871 | // which we are the delay slot of. |
duke@435 | 2872 | CodeEmitInfo * call_info = op->call_info(); |
duke@435 | 2873 | if (call_info) { |
duke@435 | 2874 | add_call_info(code_offset(), call_info); |
duke@435 | 2875 | } |
duke@435 | 2876 | |
duke@435 | 2877 | if (VerifyStackAtCalls) { |
duke@435 | 2878 | _masm->sub(FP, SP, O7); |
duke@435 | 2879 | _masm->cmp(O7, initial_frame_size_in_bytes()); |
duke@435 | 2880 | _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); |
duke@435 | 2881 | } |
duke@435 | 2882 | } |
duke@435 | 2883 | |
duke@435 | 2884 | |
duke@435 | 2885 | void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { |
duke@435 | 2886 | assert(left->is_register(), "can only handle registers"); |
duke@435 | 2887 | |
duke@435 | 2888 | if (left->is_single_cpu()) { |
duke@435 | 2889 | __ neg(left->as_register(), dest->as_register()); |
duke@435 | 2890 | } else if (left->is_single_fpu()) { |
duke@435 | 2891 | __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); |
duke@435 | 2892 | } else if (left->is_double_fpu()) { |
duke@435 | 2893 | __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); |
duke@435 | 2894 | } else { |
duke@435 | 2895 | assert (left->is_double_cpu(), "Must be a long"); |
duke@435 | 2896 | Register Rlow = left->as_register_lo(); |
duke@435 | 2897 | Register Rhi = left->as_register_hi(); |
duke@435 | 2898 | #ifdef _LP64 |
duke@435 | 2899 | __ sub(G0, Rlow, dest->as_register_lo()); |
duke@435 | 2900 | #else |
duke@435 | 2901 | __ subcc(G0, Rlow, dest->as_register_lo()); |
duke@435 | 2902 | __ subc (G0, Rhi, dest->as_register_hi()); |
duke@435 | 2903 | #endif |
duke@435 | 2904 | } |
duke@435 | 2905 | } |
duke@435 | 2906 | |
duke@435 | 2907 | |
duke@435 | 2908 | void LIR_Assembler::fxch(int i) { |
duke@435 | 2909 | Unimplemented(); |
duke@435 | 2910 | } |
duke@435 | 2911 | |
duke@435 | 2912 | void LIR_Assembler::fld(int i) { |
duke@435 | 2913 | Unimplemented(); |
duke@435 | 2914 | } |
duke@435 | 2915 | |
duke@435 | 2916 | void LIR_Assembler::ffree(int i) { |
duke@435 | 2917 | Unimplemented(); |
duke@435 | 2918 | } |
duke@435 | 2919 | |
duke@435 | 2920 | void LIR_Assembler::rt_call(LIR_Opr result, address dest, |
duke@435 | 2921 | const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { |
duke@435 | 2922 | |
duke@435 | 2923 | // if tmp is invalid, then the function being called doesn't destroy the thread |
duke@435 | 2924 | if (tmp->is_valid()) { |
duke@435 | 2925 | __ save_thread(tmp->as_register()); |
duke@435 | 2926 | } |
duke@435 | 2927 | __ call(dest, relocInfo::runtime_call_type); |
duke@435 | 2928 | __ delayed()->nop(); |
duke@435 | 2929 | if (info != NULL) { |
duke@435 | 2930 | add_call_info_here(info); |
duke@435 | 2931 | } |
duke@435 | 2932 | if (tmp->is_valid()) { |
duke@435 | 2933 | __ restore_thread(tmp->as_register()); |
duke@435 | 2934 | } |
duke@435 | 2935 | |
duke@435 | 2936 | #ifdef ASSERT |
duke@435 | 2937 | __ verify_thread(); |
duke@435 | 2938 | #endif // ASSERT |
duke@435 | 2939 | } |
duke@435 | 2940 | |
duke@435 | 2941 | |
duke@435 | 2942 | void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { |
duke@435 | 2943 | #ifdef _LP64 |
duke@435 | 2944 | ShouldNotReachHere(); |
duke@435 | 2945 | #endif |
duke@435 | 2946 | |
duke@435 | 2947 | NEEDS_CLEANUP; |
duke@435 | 2948 | if (type == T_LONG) { |
duke@435 | 2949 | LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); |
duke@435 | 2950 | |
duke@435 | 2951 | // (extended to allow indexed as well as constant displaced for JSR-166) |
duke@435 | 2952 | Register idx = noreg; // contains either constant offset or index |
duke@435 | 2953 | |
duke@435 | 2954 | int disp = mem_addr->disp(); |
duke@435 | 2955 | if (mem_addr->index() == LIR_OprFact::illegalOpr) { |
duke@435 | 2956 | if (!Assembler::is_simm13(disp)) { |
duke@435 | 2957 | idx = O7; |
duke@435 | 2958 | __ set(disp, idx); |
duke@435 | 2959 | } |
duke@435 | 2960 | } else { |
duke@435 | 2961 | assert(disp == 0, "not both indexed and disp"); |
duke@435 | 2962 | idx = mem_addr->index()->as_register(); |
duke@435 | 2963 | } |
duke@435 | 2964 | |
duke@435 | 2965 | int null_check_offset = -1; |
duke@435 | 2966 | |
duke@435 | 2967 | Register base = mem_addr->base()->as_register(); |
duke@435 | 2968 | if (src->is_register() && dest->is_address()) { |
duke@435 | 2969 | // G4 is high half, G5 is low half |
duke@435 | 2970 | if (VM_Version::v9_instructions_work()) { |
duke@435 | 2971 | // clear the top bits of G5, and scale up G4 |
duke@435 | 2972 | __ srl (src->as_register_lo(), 0, G5); |
duke@435 | 2973 | __ sllx(src->as_register_hi(), 32, G4); |
duke@435 | 2974 | // combine the two halves into the 64 bits of G4 |
duke@435 | 2975 | __ or3(G4, G5, G4); |
duke@435 | 2976 | null_check_offset = __ offset(); |
duke@435 | 2977 | if (idx == noreg) { |
duke@435 | 2978 | __ stx(G4, base, disp); |
duke@435 | 2979 | } else { |
duke@435 | 2980 | __ stx(G4, base, idx); |
duke@435 | 2981 | } |
duke@435 | 2982 | } else { |
duke@435 | 2983 | __ mov (src->as_register_hi(), G4); |
duke@435 | 2984 | __ mov (src->as_register_lo(), G5); |
duke@435 | 2985 | null_check_offset = __ offset(); |
duke@435 | 2986 | if (idx == noreg) { |
duke@435 | 2987 | __ std(G4, base, disp); |
duke@435 | 2988 | } else { |
duke@435 | 2989 | __ std(G4, base, idx); |
duke@435 | 2990 | } |
duke@435 | 2991 | } |
duke@435 | 2992 | } else if (src->is_address() && dest->is_register()) { |
duke@435 | 2993 | null_check_offset = __ offset(); |
duke@435 | 2994 | if (VM_Version::v9_instructions_work()) { |
duke@435 | 2995 | if (idx == noreg) { |
duke@435 | 2996 | __ ldx(base, disp, G5); |
duke@435 | 2997 | } else { |
duke@435 | 2998 | __ ldx(base, idx, G5); |
duke@435 | 2999 | } |
duke@435 | 3000 | __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi |
duke@435 | 3001 | __ mov (G5, dest->as_register_lo()); // copy low half into lo |
duke@435 | 3002 | } else { |
duke@435 | 3003 | if (idx == noreg) { |
duke@435 | 3004 | __ ldd(base, disp, G4); |
duke@435 | 3005 | } else { |
duke@435 | 3006 | __ ldd(base, idx, G4); |
duke@435 | 3007 | } |
duke@435 | 3008 | // G4 is high half, G5 is low half |
duke@435 | 3009 | __ mov (G4, dest->as_register_hi()); |
duke@435 | 3010 | __ mov (G5, dest->as_register_lo()); |
duke@435 | 3011 | } |
duke@435 | 3012 | } else { |
duke@435 | 3013 | Unimplemented(); |
duke@435 | 3014 | } |
duke@435 | 3015 | if (info != NULL) { |
duke@435 | 3016 | add_debug_info_for_null_check(null_check_offset, info); |
duke@435 | 3017 | } |
duke@435 | 3018 | |
duke@435 | 3019 | } else { |
duke@435 | 3020 | // use normal move for all other volatiles since they don't need |
duke@435 | 3021 | // special handling to remain atomic. |
duke@435 | 3022 | move_op(src, dest, type, lir_patch_none, info, false, false); |
duke@435 | 3023 | } |
duke@435 | 3024 | } |
duke@435 | 3025 | |
duke@435 | 3026 | void LIR_Assembler::membar() { |
duke@435 | 3027 | // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode |
duke@435 | 3028 | __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); |
duke@435 | 3029 | } |
duke@435 | 3030 | |
duke@435 | 3031 | void LIR_Assembler::membar_acquire() { |
duke@435 | 3032 | // no-op on TSO |
duke@435 | 3033 | } |
duke@435 | 3034 | |
duke@435 | 3035 | void LIR_Assembler::membar_release() { |
duke@435 | 3036 | // no-op on TSO |
duke@435 | 3037 | } |
duke@435 | 3038 | |
duke@435 | 3039 | // Macro to Pack two sequential registers containing 32 bit values |
duke@435 | 3040 | // into a single 64 bit register. |
duke@435 | 3041 | // rs and rs->successor() are packed into rd |
duke@435 | 3042 | // rd and rs may be the same register. |
duke@435 | 3043 | // Note: rs and rs->successor() are destroyed. |
duke@435 | 3044 | void LIR_Assembler::pack64( Register rs, Register rd ) { |
duke@435 | 3045 | __ sllx(rs, 32, rs); |
duke@435 | 3046 | __ srl(rs->successor(), 0, rs->successor()); |
duke@435 | 3047 | __ or3(rs, rs->successor(), rd); |
duke@435 | 3048 | } |
duke@435 | 3049 | |
duke@435 | 3050 | // Macro to unpack a 64 bit value in a register into |
duke@435 | 3051 | // two sequential registers. |
duke@435 | 3052 | // rd is unpacked into rd and rd->successor() |
duke@435 | 3053 | void LIR_Assembler::unpack64( Register rd ) { |
duke@435 | 3054 | __ mov(rd, rd->successor()); |
duke@435 | 3055 | __ srax(rd, 32, rd); |
duke@435 | 3056 | __ sra(rd->successor(), 0, rd->successor()); |
duke@435 | 3057 | } |
duke@435 | 3058 | |
duke@435 | 3059 | |
duke@435 | 3060 | void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { |
duke@435 | 3061 | LIR_Address* addr = addr_opr->as_address_ptr(); |
duke@435 | 3062 | assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); |
duke@435 | 3063 | __ add(addr->base()->as_register(), addr->disp(), dest->as_register()); |
duke@435 | 3064 | } |
duke@435 | 3065 | |
duke@435 | 3066 | |
duke@435 | 3067 | void LIR_Assembler::get_thread(LIR_Opr result_reg) { |
duke@435 | 3068 | assert(result_reg->is_register(), "check"); |
duke@435 | 3069 | __ mov(G2_thread, result_reg->as_register()); |
duke@435 | 3070 | } |
duke@435 | 3071 | |
duke@435 | 3072 | |
duke@435 | 3073 | void LIR_Assembler::peephole(LIR_List* lir) { |
duke@435 | 3074 | LIR_OpList* inst = lir->instructions_list(); |
duke@435 | 3075 | for (int i = 0; i < inst->length(); i++) { |
duke@435 | 3076 | LIR_Op* op = inst->at(i); |
duke@435 | 3077 | switch (op->code()) { |
duke@435 | 3078 | case lir_cond_float_branch: |
duke@435 | 3079 | case lir_branch: { |
duke@435 | 3080 | LIR_OpBranch* branch = op->as_OpBranch(); |
duke@435 | 3081 | assert(branch->info() == NULL, "shouldn't be state on branches anymore"); |
duke@435 | 3082 | LIR_Op* delay_op = NULL; |
duke@435 | 3083 | // we'd like to be able to pull following instructions into |
duke@435 | 3084 | // this slot but we don't know enough to do it safely yet so |
duke@435 | 3085 | // only optimize block to block control flow. |
duke@435 | 3086 | if (LIRFillDelaySlots && branch->block()) { |
duke@435 | 3087 | LIR_Op* prev = inst->at(i - 1); |
duke@435 | 3088 | if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { |
duke@435 | 3089 | // swap previous instruction into delay slot |
duke@435 | 3090 | inst->at_put(i - 1, op); |
duke@435 | 3091 | inst->at_put(i, new LIR_OpDelay(prev, op->info())); |
duke@435 | 3092 | #ifndef PRODUCT |
duke@435 | 3093 | if (LIRTracePeephole) { |
duke@435 | 3094 | tty->print_cr("delayed"); |
duke@435 | 3095 | inst->at(i - 1)->print(); |
duke@435 | 3096 | inst->at(i)->print(); |
duke@435 | 3097 | } |
duke@435 | 3098 | #endif |
duke@435 | 3099 | continue; |
duke@435 | 3100 | } |
duke@435 | 3101 | } |
duke@435 | 3102 | |
duke@435 | 3103 | if (!delay_op) { |
duke@435 | 3104 | delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); |
duke@435 | 3105 | } |
duke@435 | 3106 | inst->insert_before(i + 1, delay_op); |
duke@435 | 3107 | break; |
duke@435 | 3108 | } |
duke@435 | 3109 | case lir_static_call: |
duke@435 | 3110 | case lir_virtual_call: |
duke@435 | 3111 | case lir_icvirtual_call: |
duke@435 | 3112 | case lir_optvirtual_call: { |
duke@435 | 3113 | LIR_Op* delay_op = NULL; |
duke@435 | 3114 | LIR_Op* prev = inst->at(i - 1); |
duke@435 | 3115 | if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && |
duke@435 | 3116 | (op->code() != lir_virtual_call || |
duke@435 | 3117 | !prev->result_opr()->is_single_cpu() || |
duke@435 | 3118 | prev->result_opr()->as_register() != O0) && |
duke@435 | 3119 | LIR_Assembler::is_single_instruction(prev)) { |
duke@435 | 3120 | // Only moves without info can be put into the delay slot. |
duke@435 | 3121 | // Also don't allow the setup of the receiver in the delay |
duke@435 | 3122 | // slot for vtable calls. |
duke@435 | 3123 | inst->at_put(i - 1, op); |
duke@435 | 3124 | inst->at_put(i, new LIR_OpDelay(prev, op->info())); |
duke@435 | 3125 | #ifndef PRODUCT |
duke@435 | 3126 | if (LIRTracePeephole) { |
duke@435 | 3127 | tty->print_cr("delayed"); |
duke@435 | 3128 | inst->at(i - 1)->print(); |
duke@435 | 3129 | inst->at(i)->print(); |
duke@435 | 3130 | } |
duke@435 | 3131 | #endif |
duke@435 | 3132 | continue; |
duke@435 | 3133 | } |
duke@435 | 3134 | |
duke@435 | 3135 | if (!delay_op) { |
duke@435 | 3136 | delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); |
duke@435 | 3137 | inst->insert_before(i + 1, delay_op); |
duke@435 | 3138 | } |
duke@435 | 3139 | break; |
duke@435 | 3140 | } |
duke@435 | 3141 | } |
duke@435 | 3142 | } |
duke@435 | 3143 | } |
duke@435 | 3144 | |
duke@435 | 3145 | |
duke@435 | 3146 | |
duke@435 | 3147 | |
duke@435 | 3148 | #undef __ |