Tue, 26 Jul 2016 17:06:17 +0800
Add multiply word to GPR instruction (mul) in MIPS assembler.
aoqi@1 | 1 | /* |
aoqi@1 | 2 | * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. |
aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@1 | 5 | * |
aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@1 | 8 | * published by the Free Software Foundation. |
aoqi@1 | 9 | * |
aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@1 | 14 | * accompanied this code). |
aoqi@1 | 15 | * |
aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@1 | 19 | * |
aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
aoqi@1 | 22 | * questions. |
aoqi@1 | 23 | * |
aoqi@1 | 24 | */ |
aoqi@1 | 25 | |
aoqi@1 | 26 | #include "precompiled.hpp" |
aoqi@1 | 27 | #include "asm/assembler.hpp" |
aoqi@1 | 28 | #include "asm/register.hpp" |
aoqi@1 | 29 | #include "register_mips.hpp" |
aoqi@1 | 30 | #ifdef TARGET_ARCH_MODEL_mips_32 |
aoqi@1 | 31 | # include "interp_masm_mips_32.hpp" |
aoqi@1 | 32 | #endif |
aoqi@1 | 33 | #ifdef TARGET_ARCH_MODEL_mips_64 |
aoqi@1 | 34 | # include "interp_masm_mips_64.hpp" |
aoqi@1 | 35 | #endif |
aoqi@1 | 36 | |
aoqi@1 | 37 | |
aoqi@1 | 38 | REGISTER_DEFINITION(Register, noreg); |
aoqi@1 | 39 | REGISTER_DEFINITION(Register, i0); |
aoqi@1 | 40 | REGISTER_DEFINITION(Register, i1); |
aoqi@1 | 41 | REGISTER_DEFINITION(Register, i2); |
aoqi@1 | 42 | REGISTER_DEFINITION(Register, i3); |
aoqi@1 | 43 | REGISTER_DEFINITION(Register, i4); |
aoqi@1 | 44 | REGISTER_DEFINITION(Register, i5); |
aoqi@1 | 45 | REGISTER_DEFINITION(Register, i6); |
aoqi@1 | 46 | REGISTER_DEFINITION(Register, i7); |
aoqi@1 | 47 | REGISTER_DEFINITION(Register, i8); |
aoqi@1 | 48 | REGISTER_DEFINITION(Register, i9); |
aoqi@1 | 49 | REGISTER_DEFINITION(Register, i10); |
aoqi@1 | 50 | REGISTER_DEFINITION(Register, i11); |
aoqi@1 | 51 | REGISTER_DEFINITION(Register, i12); |
aoqi@1 | 52 | REGISTER_DEFINITION(Register, i13); |
aoqi@1 | 53 | REGISTER_DEFINITION(Register, i14); |
aoqi@1 | 54 | REGISTER_DEFINITION(Register, i15); |
aoqi@1 | 55 | REGISTER_DEFINITION(Register, i16); |
aoqi@1 | 56 | REGISTER_DEFINITION(Register, i17); |
aoqi@1 | 57 | REGISTER_DEFINITION(Register, i18); |
aoqi@1 | 58 | REGISTER_DEFINITION(Register, i19); |
aoqi@1 | 59 | REGISTER_DEFINITION(Register, i20); |
aoqi@1 | 60 | REGISTER_DEFINITION(Register, i21); |
aoqi@1 | 61 | REGISTER_DEFINITION(Register, i22); |
aoqi@1 | 62 | REGISTER_DEFINITION(Register, i23); |
aoqi@1 | 63 | REGISTER_DEFINITION(Register, i24); |
aoqi@1 | 64 | REGISTER_DEFINITION(Register, i25); |
aoqi@1 | 65 | REGISTER_DEFINITION(Register, i26); |
aoqi@1 | 66 | REGISTER_DEFINITION(Register, i27); |
aoqi@1 | 67 | REGISTER_DEFINITION(Register, i28); |
aoqi@1 | 68 | REGISTER_DEFINITION(Register, i29); |
aoqi@1 | 69 | REGISTER_DEFINITION(Register, i30); |
aoqi@1 | 70 | REGISTER_DEFINITION(Register, i31); |
aoqi@1 | 71 | |
aoqi@1 | 72 | REGISTER_DEFINITION(FloatRegister, fnoreg); |
aoqi@1 | 73 | REGISTER_DEFINITION(FloatRegister, f0); |
aoqi@1 | 74 | REGISTER_DEFINITION(FloatRegister, f1); |
aoqi@1 | 75 | REGISTER_DEFINITION(FloatRegister, f2); |
aoqi@1 | 76 | REGISTER_DEFINITION(FloatRegister, f3); |
aoqi@1 | 77 | REGISTER_DEFINITION(FloatRegister, f4); |
aoqi@1 | 78 | REGISTER_DEFINITION(FloatRegister, f5); |
aoqi@1 | 79 | REGISTER_DEFINITION(FloatRegister, f6); |
aoqi@1 | 80 | REGISTER_DEFINITION(FloatRegister, f7); |
aoqi@1 | 81 | REGISTER_DEFINITION(FloatRegister, f8); |
aoqi@1 | 82 | REGISTER_DEFINITION(FloatRegister, f9); |
aoqi@1 | 83 | REGISTER_DEFINITION(FloatRegister, f10); |
aoqi@1 | 84 | REGISTER_DEFINITION(FloatRegister, f11); |
aoqi@1 | 85 | REGISTER_DEFINITION(FloatRegister, f12); |
aoqi@1 | 86 | REGISTER_DEFINITION(FloatRegister, f13); |
aoqi@1 | 87 | REGISTER_DEFINITION(FloatRegister, f14); |
aoqi@1 | 88 | REGISTER_DEFINITION(FloatRegister, f15); |
aoqi@1 | 89 | REGISTER_DEFINITION(FloatRegister, f16); |
aoqi@1 | 90 | REGISTER_DEFINITION(FloatRegister, f17); |
aoqi@1 | 91 | REGISTER_DEFINITION(FloatRegister, f18); |
aoqi@1 | 92 | REGISTER_DEFINITION(FloatRegister, f19); |
aoqi@1 | 93 | REGISTER_DEFINITION(FloatRegister, f20); |
aoqi@1 | 94 | REGISTER_DEFINITION(FloatRegister, f21); |
aoqi@1 | 95 | REGISTER_DEFINITION(FloatRegister, f22); |
aoqi@1 | 96 | REGISTER_DEFINITION(FloatRegister, f23); |
aoqi@1 | 97 | REGISTER_DEFINITION(FloatRegister, f24); |
aoqi@1 | 98 | REGISTER_DEFINITION(FloatRegister, f25); |
aoqi@1 | 99 | REGISTER_DEFINITION(FloatRegister, f26); |
aoqi@1 | 100 | REGISTER_DEFINITION(FloatRegister, f27); |
aoqi@1 | 101 | REGISTER_DEFINITION(FloatRegister, f28); |
aoqi@1 | 102 | REGISTER_DEFINITION(FloatRegister, f29); |
aoqi@1 | 103 | REGISTER_DEFINITION(FloatRegister, f30); |
aoqi@1 | 104 | REGISTER_DEFINITION(FloatRegister, f31); |