Mercurial > jdk8-mips64-public > hotspot / annotate
src/cpu/mips/vm/icBuffer_mips.cpp@d885f8d65c58 (annotated)
src/cpu/mips/vm/icBuffer_mips.cpp
Tue, 26 Jul 2016 17:06:17 +0800
- author
- fujie
- date
- Tue, 26 Jul 2016 17:06:17 +0800
- changeset 41
- d885f8d65c58
- parent 1
- 2d8a650513c2
- child 368
- 11ec15adb6c4
- permissions
- -rw-r--r--
Add multiply word to GPR instruction (mul) in MIPS assembler.
| aoqi@1 | 1 | /* |
| aoqi@1 | 2 | * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
| aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@1 | 5 | * |
| aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@1 | 8 | * published by the Free Software Foundation. |
| aoqi@1 | 9 | * |
| aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@1 | 14 | * accompanied this code). |
| aoqi@1 | 15 | * |
| aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@1 | 19 | * |
| aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@1 | 22 | * questions. |
| aoqi@1 | 23 | * |
| aoqi@1 | 24 | */ |
| aoqi@1 | 25 | |
| aoqi@1 | 26 | #include "precompiled.hpp" |
| aoqi@1 | 27 | #include "asm/macroAssembler.hpp" |
| aoqi@1 | 28 | #include "asm/macroAssembler.inline.hpp" |
| aoqi@1 | 29 | #include "code/icBuffer.hpp" |
| aoqi@1 | 30 | #include "gc_interface/collectedHeap.inline.hpp" |
| aoqi@1 | 31 | #include "interpreter/bytecodes.hpp" |
| aoqi@1 | 32 | #include "memory/resourceArea.hpp" |
| aoqi@1 | 33 | #include "nativeInst_mips.hpp" |
| aoqi@1 | 34 | #include "oops/oop.inline.hpp" |
| aoqi@1 | 35 | #include "oops/oop.inline2.hpp" |
| aoqi@1 | 36 | |
| aoqi@1 | 37 | int InlineCacheBuffer::ic_stub_code_size() { |
| aoqi@1 | 38 | return NativeMovConstReg::instruction_size + |
| aoqi@1 | 39 | NativeGeneralJump::instruction_size + |
| aoqi@1 | 40 | 1; |
| aoqi@1 | 41 | // so that code_end can be set in CodeBuffer |
| aoqi@1 | 42 | // 64bit 15 = 6 + 8 bytes + 1 byte |
| aoqi@1 | 43 | // 32bit 7 = 2 + 4 bytes + 1 byte |
| aoqi@1 | 44 | } |
| aoqi@1 | 45 | |
| aoqi@1 | 46 | |
| aoqi@1 | 47 | // we use T1 as cached oop(klass) now. this is the target of virtual call, |
| aoqi@1 | 48 | // when reach here, the receiver in T0 |
| aoqi@1 | 49 | // refer to shareRuntime_mips.cpp,gen_i2c2i_adapters |
| aoqi@1 | 50 | void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, void* cached_value, address entry_point) { |
| aoqi@1 | 51 | ResourceMark rm; |
| aoqi@1 | 52 | CodeBuffer code(code_begin, ic_stub_code_size()); |
| aoqi@1 | 53 | MacroAssembler* masm = new MacroAssembler(&code); |
| aoqi@1 | 54 | // note: even though the code contains an embedded oop, we do not need reloc info |
| aoqi@1 | 55 | // because |
| aoqi@1 | 56 | // (1) the oop is old (i.e., doesn't matter for scavenges) |
| aoqi@1 | 57 | // (2) these ICStubs are removed *before* a GC happens, so the roots disappear |
| aoqi@1 | 58 | // assert(cached_oop == NULL || cached_oop->is_perm(), "must be perm oop"); |
| aoqi@1 | 59 | #define __ masm-> |
| aoqi@1 | 60 | #ifndef _LP64 |
| aoqi@1 | 61 | __ lui(T1, Assembler::split_high((int)cached_value)); |
| aoqi@1 | 62 | __ addiu(T1, T1, Assembler::split_low((int)cached_value)); |
| aoqi@1 | 63 | |
| aoqi@1 | 64 | __ lui(T9, Assembler::split_high((int)entry_point)); |
| aoqi@1 | 65 | __ addiu(T9, T9, Assembler::split_low((int)entry_point)); |
| aoqi@1 | 66 | #else |
| aoqi@1 | 67 | __ li48(T1, (long)cached_value); |
| aoqi@1 | 68 | |
| aoqi@1 | 69 | __ li48(T9, (long)entry_point); |
| aoqi@1 | 70 | #endif |
| aoqi@1 | 71 | __ jr(T9); |
| aoqi@1 | 72 | __ delayed()->nop(); |
| aoqi@1 | 73 | __ flush(); |
| aoqi@1 | 74 | #undef __ |
| aoqi@1 | 75 | } |
| aoqi@1 | 76 | |
| aoqi@1 | 77 | |
| aoqi@1 | 78 | address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) { |
| aoqi@1 | 79 | NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object |
| aoqi@1 | 80 | //NativeJump* jump = nativeJump_at(move->next_instruction_address()); |
| aoqi@1 | 81 | NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); |
| aoqi@1 | 82 | return jump->jump_destination(); |
| aoqi@1 | 83 | } |
| aoqi@1 | 84 | |
| aoqi@1 | 85 | void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) { |
| aoqi@1 | 86 | // creation also verifies the object |
| aoqi@1 | 87 | NativeMovConstReg* move = nativeMovConstReg_at(code_begin); |
| aoqi@1 | 88 | // Verifies the jump |
| aoqi@1 | 89 | //NativeJump* jump = nativeJump_at(move->next_instruction_address()); |
| aoqi@1 | 90 | NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); |
| aoqi@1 | 91 | void* o= (void*)move->data(); |
| aoqi@1 | 92 | return o; |
| aoqi@1 | 93 | } |
