Wed, 18 Sep 2013 14:34:56 -0700
8024342: PPC64 (part 111): Support for C calling conventions that require 64-bit ints.
Summary: Some platforms, as ppc and s390x/zArch require that 32-bit ints are passed as 64-bit values to C functions. This change adds support to adapt the signature and to issue proper casts to c2-compiled stubs. The functions are used in generate_native_wrapper(). Adapt signature used by the compiler as in PhaseIdealLoop::intrinsify_fill().
Reviewed-by: kvn
duke@435 | 1 | /* |
drchase@4585 | 2 | * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #ifndef SHARE_VM_OPTO_REGMASK_HPP |
stefank@2314 | 26 | #define SHARE_VM_OPTO_REGMASK_HPP |
stefank@2314 | 27 | |
stefank@2314 | 28 | #include "code/vmreg.hpp" |
stefank@2314 | 29 | #include "libadt/port.hpp" |
stefank@2314 | 30 | #include "opto/optoreg.hpp" |
stefank@2314 | 31 | #ifdef TARGET_ARCH_MODEL_x86_32 |
stefank@2314 | 32 | # include "adfiles/adGlobals_x86_32.hpp" |
stefank@2314 | 33 | #endif |
stefank@2314 | 34 | #ifdef TARGET_ARCH_MODEL_x86_64 |
stefank@2314 | 35 | # include "adfiles/adGlobals_x86_64.hpp" |
stefank@2314 | 36 | #endif |
stefank@2314 | 37 | #ifdef TARGET_ARCH_MODEL_sparc |
stefank@2314 | 38 | # include "adfiles/adGlobals_sparc.hpp" |
stefank@2314 | 39 | #endif |
stefank@2314 | 40 | #ifdef TARGET_ARCH_MODEL_zero |
stefank@2314 | 41 | # include "adfiles/adGlobals_zero.hpp" |
stefank@2314 | 42 | #endif |
bobv@2508 | 43 | #ifdef TARGET_ARCH_MODEL_arm |
bobv@2508 | 44 | # include "adfiles/adGlobals_arm.hpp" |
bobv@2508 | 45 | #endif |
goetz@6441 | 46 | #ifdef TARGET_ARCH_MODEL_ppc_32 |
goetz@6441 | 47 | # include "adfiles/adGlobals_ppc_32.hpp" |
goetz@6441 | 48 | #endif |
goetz@6441 | 49 | #ifdef TARGET_ARCH_MODEL_ppc_64 |
goetz@6441 | 50 | # include "adfiles/adGlobals_ppc_64.hpp" |
bobv@2508 | 51 | #endif |
stefank@2314 | 52 | |
duke@435 | 53 | // Some fun naming (textual) substitutions: |
duke@435 | 54 | // |
duke@435 | 55 | // RegMask::get_low_elem() ==> RegMask::find_first_elem() |
duke@435 | 56 | // RegMask::Special ==> RegMask::Empty |
duke@435 | 57 | // RegMask::_flags ==> RegMask::is_AllStack() |
duke@435 | 58 | // RegMask::operator<<=() ==> RegMask::Insert() |
duke@435 | 59 | // RegMask::operator>>=() ==> RegMask::Remove() |
duke@435 | 60 | // RegMask::Union() ==> RegMask::OR |
duke@435 | 61 | // RegMask::Inter() ==> RegMask::AND |
duke@435 | 62 | // |
duke@435 | 63 | // OptoRegister::RegName ==> OptoReg::Name |
duke@435 | 64 | // |
duke@435 | 65 | // OptoReg::stack0() ==> _last_Mach_Reg or ZERO in core version |
duke@435 | 66 | // |
duke@435 | 67 | // numregs in chaitin ==> proper degree in chaitin |
duke@435 | 68 | |
duke@435 | 69 | //-------------Non-zero bit search methods used by RegMask--------------------- |
duke@435 | 70 | // Find lowest 1, or return 32 if empty |
duke@435 | 71 | int find_lowest_bit( uint32 mask ); |
duke@435 | 72 | // Find highest 1, or return 32 if empty |
duke@435 | 73 | int find_hihghest_bit( uint32 mask ); |
duke@435 | 74 | |
duke@435 | 75 | //------------------------------RegMask---------------------------------------- |
duke@435 | 76 | // The ADL file describes how to print the machine-specific registers, as well |
duke@435 | 77 | // as any notion of register classes. We provide a register mask, which is |
duke@435 | 78 | // just a collection of Register numbers. |
duke@435 | 79 | |
duke@435 | 80 | // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY. |
duke@435 | 81 | // RM_SIZE is the size of a register mask in words. |
duke@435 | 82 | // FORALL_BODY replicates a BODY macro once per word in the register mask. |
duke@435 | 83 | // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files. |
duke@435 | 84 | // However, it means the ADLC can redefine the unroll macro and all loops |
duke@435 | 85 | // over register masks will be unrolled by the correct amount. |
duke@435 | 86 | |
duke@435 | 87 | class RegMask VALUE_OBJ_CLASS_SPEC { |
duke@435 | 88 | union { |
duke@435 | 89 | double _dummy_force_double_alignment[RM_SIZE>>1]; |
duke@435 | 90 | // Array of Register Mask bits. This array is large enough to cover |
duke@435 | 91 | // all the machine registers and all parameters that need to be passed |
duke@435 | 92 | // on the stack (stack registers) up to some interesting limit. Methods |
duke@435 | 93 | // that need more parameters will NOT be compiled. On Intel, the limit |
duke@435 | 94 | // is something like 90+ parameters. |
duke@435 | 95 | int _A[RM_SIZE]; |
duke@435 | 96 | }; |
duke@435 | 97 | |
duke@435 | 98 | enum { |
duke@435 | 99 | _WordBits = BitsPerInt, |
duke@435 | 100 | _LogWordBits = LogBitsPerInt, |
duke@435 | 101 | _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef |
duke@435 | 102 | }; |
duke@435 | 103 | |
duke@435 | 104 | public: |
duke@435 | 105 | enum { CHUNK_SIZE = RM_SIZE*_WordBits }; |
duke@435 | 106 | |
duke@435 | 107 | // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits. |
duke@435 | 108 | // Also, consider the maximum alignment size for a normally allocated |
duke@435 | 109 | // value. Since we allocate register pairs but not register quads (at |
duke@435 | 110 | // present), this alignment is SlotsPerLong (== 2). A normally |
duke@435 | 111 | // aligned allocated register is either a single register, or a pair |
duke@435 | 112 | // of adjacent registers, the lower-numbered being even. |
duke@435 | 113 | // See also is_aligned_Pairs() below, and the padding added before |
duke@435 | 114 | // Matcher::_new_SP to keep allocated pairs aligned properly. |
duke@435 | 115 | // If we ever go to quad-word allocations, SlotsPerQuad will become |
duke@435 | 116 | // the controlling alignment constraint. Note that this alignment |
duke@435 | 117 | // requirement is internal to the allocator, and independent of any |
duke@435 | 118 | // particular platform. |
kvn@3882 | 119 | enum { SlotsPerLong = 2, |
kvn@3882 | 120 | SlotsPerVecS = 1, |
kvn@3882 | 121 | SlotsPerVecD = 2, |
kvn@3882 | 122 | SlotsPerVecX = 4, |
kvn@3882 | 123 | SlotsPerVecY = 8 }; |
duke@435 | 124 | |
duke@435 | 125 | // A constructor only used by the ADLC output. All mask fields are filled |
duke@435 | 126 | // in directly. Calls to this look something like RM(1,2,3,4); |
duke@435 | 127 | RegMask( |
duke@435 | 128 | # define BODY(I) int a##I, |
duke@435 | 129 | FORALL_BODY |
duke@435 | 130 | # undef BODY |
duke@435 | 131 | int dummy = 0 ) { |
duke@435 | 132 | # define BODY(I) _A[I] = a##I; |
duke@435 | 133 | FORALL_BODY |
duke@435 | 134 | # undef BODY |
duke@435 | 135 | } |
duke@435 | 136 | |
duke@435 | 137 | // Handy copying constructor |
duke@435 | 138 | RegMask( RegMask *rm ) { |
duke@435 | 139 | # define BODY(I) _A[I] = rm->_A[I]; |
duke@435 | 140 | FORALL_BODY |
duke@435 | 141 | # undef BODY |
duke@435 | 142 | } |
duke@435 | 143 | |
duke@435 | 144 | // Construct an empty mask |
duke@435 | 145 | RegMask( ) { Clear(); } |
duke@435 | 146 | |
duke@435 | 147 | // Construct a mask with a single bit |
duke@435 | 148 | RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); } |
duke@435 | 149 | |
duke@435 | 150 | // Check for register being in mask |
duke@435 | 151 | int Member( OptoReg::Name reg ) const { |
duke@435 | 152 | assert( reg < CHUNK_SIZE, "" ); |
duke@435 | 153 | return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1))); |
duke@435 | 154 | } |
duke@435 | 155 | |
duke@435 | 156 | // The last bit in the register mask indicates that the mask should repeat |
duke@435 | 157 | // indefinitely with ONE bits. Returns TRUE if mask is infinite or |
duke@435 | 158 | // unbounded in size. Returns FALSE if mask is finite size. |
duke@435 | 159 | int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); } |
duke@435 | 160 | |
duke@435 | 161 | // Work around an -xO3 optimization problme in WS6U1. The old way: |
duke@435 | 162 | // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); } |
duke@435 | 163 | // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack() |
duke@435 | 164 | // follows an Insert() loop, like the one found in init_spill_mask(). Using |
duke@435 | 165 | // Insert() instead works because the index into _A in computed instead of |
duke@435 | 166 | // constant. See bug 4665841. |
duke@435 | 167 | void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); } |
duke@435 | 168 | |
duke@435 | 169 | // Test for being a not-empty mask. |
duke@435 | 170 | int is_NotEmpty( ) const { |
duke@435 | 171 | int tmp = 0; |
duke@435 | 172 | # define BODY(I) tmp |= _A[I]; |
duke@435 | 173 | FORALL_BODY |
duke@435 | 174 | # undef BODY |
duke@435 | 175 | return tmp; |
duke@435 | 176 | } |
duke@435 | 177 | |
duke@435 | 178 | // Find lowest-numbered register from mask, or BAD if mask is empty. |
duke@435 | 179 | OptoReg::Name find_first_elem() const { |
duke@435 | 180 | int base, bits; |
duke@435 | 181 | # define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else |
duke@435 | 182 | FORALL_BODY |
duke@435 | 183 | # undef BODY |
duke@435 | 184 | { base = OptoReg::Bad; bits = 1<<0; } |
duke@435 | 185 | return OptoReg::Name(base + find_lowest_bit(bits)); |
duke@435 | 186 | } |
duke@435 | 187 | // Get highest-numbered register from mask, or BAD if mask is empty. |
duke@435 | 188 | OptoReg::Name find_last_elem() const { |
duke@435 | 189 | int base, bits; |
duke@435 | 190 | # define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else |
duke@435 | 191 | FORALL_BODY |
duke@435 | 192 | # undef BODY |
duke@435 | 193 | { base = OptoReg::Bad; bits = 1<<0; } |
duke@435 | 194 | return OptoReg::Name(base + find_hihghest_bit(bits)); |
duke@435 | 195 | } |
duke@435 | 196 | |
duke@435 | 197 | // Find the lowest-numbered register pair in the mask. Return the |
duke@435 | 198 | // HIGHEST register number in the pair, or BAD if no pairs. |
duke@435 | 199 | // Assert that the mask contains only bit pairs. |
duke@435 | 200 | OptoReg::Name find_first_pair() const; |
duke@435 | 201 | |
duke@435 | 202 | // Clear out partial bits; leave only aligned adjacent bit pairs. |
kvn@3882 | 203 | void clear_to_pairs(); |
duke@435 | 204 | // Smear out partial bits; leave only aligned adjacent bit pairs. |
kvn@3882 | 205 | void smear_to_pairs(); |
duke@435 | 206 | // Verify that the mask contains only aligned adjacent bit pairs |
kvn@3882 | 207 | void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); } |
duke@435 | 208 | // Test that the mask contains only aligned adjacent bit pairs |
kvn@3882 | 209 | bool is_aligned_pairs() const; |
duke@435 | 210 | |
duke@435 | 211 | // mask is a pair of misaligned registers |
kvn@3882 | 212 | bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); } |
duke@435 | 213 | // Test for single register |
duke@435 | 214 | int is_bound1() const; |
duke@435 | 215 | // Test for a single adjacent pair |
kvn@3882 | 216 | int is_bound_pair() const; |
kvn@3882 | 217 | // Test for a single adjacent set of ideal register's size. |
kvn@3882 | 218 | int is_bound(uint ireg) const { |
kvn@3882 | 219 | if (is_vector(ireg)) { |
kvn@3882 | 220 | if (is_bound_set(num_registers(ireg))) |
kvn@3882 | 221 | return true; |
kvn@3882 | 222 | } else if (is_bound1() || is_bound_pair()) { |
kvn@3882 | 223 | return true; |
kvn@3882 | 224 | } |
kvn@3882 | 225 | return false; |
kvn@3882 | 226 | } |
kvn@3882 | 227 | |
kvn@3882 | 228 | // Find the lowest-numbered register set in the mask. Return the |
kvn@3882 | 229 | // HIGHEST register number in the set, or BAD if no sets. |
kvn@3882 | 230 | // Assert that the mask contains only bit sets. |
drchase@4585 | 231 | OptoReg::Name find_first_set(const int size) const; |
kvn@3882 | 232 | |
kvn@3882 | 233 | // Clear out partial bits; leave only aligned adjacent bit sets of size. |
drchase@4585 | 234 | void clear_to_sets(const int size); |
kvn@3882 | 235 | // Smear out partial bits to aligned adjacent bit sets. |
drchase@4585 | 236 | void smear_to_sets(const int size); |
kvn@3882 | 237 | // Verify that the mask contains only aligned adjacent bit sets |
kvn@3882 | 238 | void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); } |
kvn@3882 | 239 | // Test that the mask contains only aligned adjacent bit sets |
drchase@4585 | 240 | bool is_aligned_sets(const int size) const; |
kvn@3882 | 241 | |
kvn@3882 | 242 | // mask is a set of misaligned registers |
kvn@3882 | 243 | bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);} |
kvn@3882 | 244 | |
kvn@3882 | 245 | // Test for a single adjacent set |
drchase@4585 | 246 | int is_bound_set(const int size) const; |
kvn@3882 | 247 | |
kvn@3882 | 248 | static bool is_vector(uint ireg); |
kvn@3882 | 249 | static int num_registers(uint ireg); |
duke@435 | 250 | |
duke@435 | 251 | // Fast overlap test. Non-zero if any registers in common. |
duke@435 | 252 | int overlap( const RegMask &rm ) const { |
duke@435 | 253 | return |
duke@435 | 254 | # define BODY(I) (_A[I] & rm._A[I]) | |
duke@435 | 255 | FORALL_BODY |
duke@435 | 256 | # undef BODY |
duke@435 | 257 | 0 ; |
duke@435 | 258 | } |
duke@435 | 259 | |
duke@435 | 260 | // Special test for register pressure based splitting |
duke@435 | 261 | // UP means register only, Register plus stack, or stack only is DOWN |
duke@435 | 262 | bool is_UP() const; |
duke@435 | 263 | |
duke@435 | 264 | // Clear a register mask |
duke@435 | 265 | void Clear( ) { |
duke@435 | 266 | # define BODY(I) _A[I] = 0; |
duke@435 | 267 | FORALL_BODY |
duke@435 | 268 | # undef BODY |
duke@435 | 269 | } |
duke@435 | 270 | |
duke@435 | 271 | // Fill a register mask with 1's |
duke@435 | 272 | void Set_All( ) { |
duke@435 | 273 | # define BODY(I) _A[I] = -1; |
duke@435 | 274 | FORALL_BODY |
duke@435 | 275 | # undef BODY |
duke@435 | 276 | } |
duke@435 | 277 | |
duke@435 | 278 | // Insert register into mask |
duke@435 | 279 | void Insert( OptoReg::Name reg ) { |
duke@435 | 280 | assert( reg < CHUNK_SIZE, "" ); |
duke@435 | 281 | _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1))); |
duke@435 | 282 | } |
duke@435 | 283 | |
duke@435 | 284 | // Remove register from mask |
duke@435 | 285 | void Remove( OptoReg::Name reg ) { |
duke@435 | 286 | assert( reg < CHUNK_SIZE, "" ); |
duke@435 | 287 | _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1))); |
duke@435 | 288 | } |
duke@435 | 289 | |
duke@435 | 290 | // OR 'rm' into 'this' |
duke@435 | 291 | void OR( const RegMask &rm ) { |
duke@435 | 292 | # define BODY(I) this->_A[I] |= rm._A[I]; |
duke@435 | 293 | FORALL_BODY |
duke@435 | 294 | # undef BODY |
duke@435 | 295 | } |
duke@435 | 296 | |
duke@435 | 297 | // AND 'rm' into 'this' |
duke@435 | 298 | void AND( const RegMask &rm ) { |
duke@435 | 299 | # define BODY(I) this->_A[I] &= rm._A[I]; |
duke@435 | 300 | FORALL_BODY |
duke@435 | 301 | # undef BODY |
duke@435 | 302 | } |
duke@435 | 303 | |
duke@435 | 304 | // Subtract 'rm' from 'this' |
duke@435 | 305 | void SUBTRACT( const RegMask &rm ) { |
duke@435 | 306 | # define BODY(I) _A[I] &= ~rm._A[I]; |
duke@435 | 307 | FORALL_BODY |
duke@435 | 308 | # undef BODY |
duke@435 | 309 | } |
duke@435 | 310 | |
duke@435 | 311 | // Compute size of register mask: number of bits |
duke@435 | 312 | uint Size() const; |
duke@435 | 313 | |
duke@435 | 314 | #ifndef PRODUCT |
duke@435 | 315 | void print() const { dump(); } |
kvn@4478 | 316 | void dump(outputStream *st = tty) const; // Print a mask |
duke@435 | 317 | #endif |
duke@435 | 318 | |
duke@435 | 319 | static const RegMask Empty; // Common empty mask |
duke@435 | 320 | |
duke@435 | 321 | static bool can_represent(OptoReg::Name reg) { |
duke@435 | 322 | // NOTE: -1 in computation reflects the usage of the last |
kvn@3882 | 323 | // bit of the regmask as an infinite stack flag and |
kvn@3882 | 324 | // -7 is to keep mask aligned for largest value (VecY). |
duke@435 | 325 | return (int)reg < (int)(CHUNK_SIZE-1); |
duke@435 | 326 | } |
kvn@3882 | 327 | static bool can_represent_arg(OptoReg::Name reg) { |
kvn@3882 | 328 | // NOTE: -SlotsPerVecY in computation reflects the need |
kvn@3882 | 329 | // to keep mask aligned for largest value (VecY). |
kvn@3882 | 330 | return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecY); |
kvn@3882 | 331 | } |
duke@435 | 332 | }; |
duke@435 | 333 | |
duke@435 | 334 | // Do not use this constant directly in client code! |
duke@435 | 335 | #undef RM_SIZE |
stefank@2314 | 336 | |
stefank@2314 | 337 | #endif // SHARE_VM_OPTO_REGMASK_HPP |