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src/share/vm/c1/c1_LIRAssembler.hpp@ac27a9c85bea (annotated)

src/share/vm/c1/c1_LIRAssembler.hpp

Thu, 24 May 2018 18:41:44 +0800

author

aoqi

date

Thu, 24 May 2018 18:41:44 +0800

changeset 8856

ac27a9c85bea

parent 6876

710a3c8b516e

child 9138

b56ab8e56604

permissions

-rw-r--r--

Merge

aoqi@0	1	/*
aoqi@0	2	* Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
aoqi@0	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
aoqi@0	4	*
aoqi@0	5	* This code is free software; you can redistribute it and/or modify it
aoqi@0	6	* under the terms of the GNU General Public License version 2 only, as
aoqi@0	7	* published by the Free Software Foundation.
aoqi@0	8	*
aoqi@0	9	* This code is distributed in the hope that it will be useful, but WITHOUT
aoqi@0	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
aoqi@0	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
aoqi@0	12	* version 2 for more details (a copy is included in the LICENSE file that
aoqi@0	13	* accompanied this code).
aoqi@0	14	*
aoqi@0	15	* You should have received a copy of the GNU General Public License version
aoqi@0	16	* 2 along with this work; if not, write to the Free Software Foundation,
aoqi@0	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
aoqi@0	18	*
aoqi@0	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
aoqi@0	20	* or visit www.oracle.com if you need additional information or have any
aoqi@0	21	* questions.
aoqi@0	22	*
aoqi@0	23	*/
aoqi@0	24
aoqi@1	25	/*
aoqi@1	26	* This file has been modified by Loongson Technology in 2015. These
aoqi@1	27	* modifications are Copyright (c) 2015 Loongson Technology, and are made
aoqi@1	28	* available on the same license terms set forth above.
aoqi@1	29	*/
aoqi@1	30
aoqi@0	31	#ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP
aoqi@0	32	#define SHARE_VM_C1_C1_LIRASSEMBLER_HPP
aoqi@0	33
aoqi@0	34	#include "c1/c1_CodeStubs.hpp"
aoqi@0	35	#include "ci/ciMethodData.hpp"
aoqi@0	36	#include "oops/methodData.hpp"
aoqi@0	37	#include "utilities/top.hpp"
aoqi@0	38
aoqi@0	39	class Compilation;
aoqi@0	40	class ScopeValue;
aoqi@0	41	class BarrierSet;
aoqi@0	42
aoqi@0	43	class LIR_Assembler: public CompilationResourceObj {
aoqi@0	44	private:
aoqi@0	45	C1_MacroAssembler* _masm;
aoqi@0	46	CodeStubList* _slow_case_stubs;
aoqi@0	47	BarrierSet* _bs;
aoqi@0	48
aoqi@0	49	Compilation* _compilation;
aoqi@0	50	FrameMap* _frame_map;
aoqi@0	51	BlockBegin* _current_block;
aoqi@0	52
aoqi@0	53	Instruction* _pending_non_safepoint;
aoqi@0	54	int _pending_non_safepoint_offset;
aoqi@0	55
aoqi@0	56	Label _unwind_handler_entry;
aoqi@0	57
aoqi@0	58	#ifdef ASSERT
aoqi@0	59	BlockList _branch_target_blocks;
aoqi@0	60	void check_no_unbound_labels();
aoqi@0	61	#endif
aoqi@0	62
aoqi@0	63	FrameMap* frame_map() const { return _frame_map; }
aoqi@0	64
aoqi@0	65	void set_current_block(BlockBegin* b) { _current_block = b; }
aoqi@0	66	BlockBegin* current_block() const { return _current_block; }
aoqi@0	67
aoqi@0	68	// non-safepoint debug info management
aoqi@0	69	void flush_debug_info(int before_pc_offset) {
aoqi@0	70	if (_pending_non_safepoint != NULL) {
aoqi@0	71	if (_pending_non_safepoint_offset < before_pc_offset)
aoqi@0	72	record_non_safepoint_debug_info();
aoqi@0	73	_pending_non_safepoint = NULL;
aoqi@0	74	}
aoqi@0	75	}
aoqi@0	76	void process_debug_info(LIR_Op* op);
aoqi@0	77	void record_non_safepoint_debug_info();
aoqi@0	78
aoqi@0	79	// unified bailout support
aoqi@0	80	void bailout(const char* msg) const { compilation()->bailout(msg); }
aoqi@0	81	bool bailed_out() const { return compilation()->bailed_out(); }
aoqi@0	82
aoqi@0	83	// code emission patterns and accessors
aoqi@0	84	void check_codespace();
aoqi@0	85	bool needs_icache(ciMethod* method) const;
aoqi@0	86
aoqi@0	87	// returns offset of icache check
aoqi@0	88	int check_icache();
aoqi@0	89
aoqi@0	90	void jobject2reg(jobject o, Register reg);
aoqi@0	91	void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);
aoqi@0	92
aoqi@0	93	void metadata2reg(Metadata* o, Register reg);
aoqi@0	94	void klass2reg_with_patching(Register reg, CodeEmitInfo* info);
aoqi@0	95
aoqi@0	96	void emit_stubs(CodeStubList* stub_list);
aoqi@0	97
aoqi@0	98	// addresses
aoqi@0	99	Address as_Address(LIR_Address* addr);
aoqi@0	100	Address as_Address_lo(LIR_Address* addr);
aoqi@0	101	Address as_Address_hi(LIR_Address* addr);
aoqi@0	102
aoqi@0	103	// debug information
aoqi@0	104	void add_call_info(int pc_offset, CodeEmitInfo* cinfo);
aoqi@0	105	void add_debug_info_for_branch(CodeEmitInfo* info);
aoqi@0	106	void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
aoqi@0	107	void add_debug_info_for_div0_here(CodeEmitInfo* info);
aoqi@0	108	void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
aoqi@0	109	void add_debug_info_for_null_check_here(CodeEmitInfo* info);
aoqi@0	110
aoqi@0	111	void set_24bit_FPU();
aoqi@0	112	void reset_FPU();
aoqi@0	113	void fpop();
aoqi@0	114	void fxch(int i);
aoqi@0	115	void fld(int i);
aoqi@0	116	void ffree(int i);
aoqi@0	117
aoqi@0	118	void breakpoint();
aoqi@0	119	void push(LIR_Opr opr);
aoqi@0	120	void pop(LIR_Opr opr);
aoqi@0	121
aoqi@0	122	// patching
aoqi@0	123	void append_patching_stub(PatchingStub* stub);
aoqi@0	124	void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);
aoqi@0	125
aoqi@0	126	void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);
aoqi@0	127
aoqi@0	128	PatchingStub::PatchID patching_id(CodeEmitInfo* info);
aoqi@0	129
aoqi@0	130	public:
aoqi@0	131	LIR_Assembler(Compilation* c);
aoqi@0	132	~LIR_Assembler();
aoqi@0	133	C1_MacroAssembler* masm() const { return _masm; }
aoqi@0	134	Compilation* compilation() const { return _compilation; }
aoqi@0	135	ciMethod* method() const { return compilation()->method(); }
aoqi@0	136
aoqi@0	137	CodeOffsets* offsets() const { return _compilation->offsets(); }
aoqi@0	138	int code_offset() const;
aoqi@0	139	address pc() const;
aoqi@0	140
aoqi@0	141	int initial_frame_size_in_bytes() const;
aoqi@0	142	int bang_size_in_bytes() const;
aoqi@0	143
aoqi@0	144	// test for constants which can be encoded directly in instructions
aoqi@0	145	static bool is_small_constant(LIR_Opr opr);
aoqi@0	146
aoqi@0	147	static LIR_Opr receiverOpr();
aoqi@0	148	static LIR_Opr osrBufferPointer();
aoqi@0	149
aoqi@0	150	// stubs
aoqi@0	151	void emit_slow_case_stubs();
aoqi@0	152	void emit_static_call_stub();
aoqi@0	153	void append_code_stub(CodeStub* op);
aoqi@0	154	void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); }
aoqi@0	155
aoqi@0	156	// code patterns
aoqi@0	157	int emit_exception_handler();
aoqi@0	158	int emit_unwind_handler();
aoqi@0	159	void emit_exception_entries(ExceptionInfoList* info_list);
aoqi@0	160	int emit_deopt_handler();
aoqi@0	161
aoqi@0	162	void emit_code(BlockList* hir);
aoqi@0	163	void emit_block(BlockBegin* block);
aoqi@0	164	void emit_lir_list(LIR_List* list);
aoqi@0	165
aoqi@0	166	// any last minute peephole optimizations are performed here. In
aoqi@0	167	// particular sparc uses this for delay slot filling.
aoqi@0	168	void peephole(LIR_List* list);
aoqi@0	169
aoqi@0	170	void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info);
aoqi@0	171
aoqi@0	172	void return_op(LIR_Opr result);
aoqi@0	173
aoqi@0	174	// returns offset of poll instruction
aoqi@0	175	int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);
aoqi@0	176
aoqi@0	177	void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);
aoqi@0	178	void const2stack(LIR_Opr src, LIR_Opr dest);
aoqi@0	179	void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide);
aoqi@0	180	void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);
aoqi@0	181	void reg2reg (LIR_Opr src, LIR_Opr dest);
aoqi@0	182	void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type,
aoqi@0	183	LIR_PatchCode patch_code, CodeEmitInfo* info,
aoqi@0	184	bool pop_fpu_stack, bool wide, bool unaligned);
aoqi@0	185	void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type);
aoqi@0	186	void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);
aoqi@0	187	void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type,
aoqi@0	188	LIR_PatchCode patch_code,
aoqi@0	189	CodeEmitInfo* info, bool wide, bool unaligned);
aoqi@0	190
aoqi@0	191	void prefetchr (LIR_Opr src);
aoqi@0	192	void prefetchw (LIR_Opr src);
aoqi@0	193
aoqi@0	194	void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);
aoqi@0	195	void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest);
aoqi@0	196
aoqi@0	197	void move_regs(Register from_reg, Register to_reg);
aoqi@0	198	void swap_reg(Register a, Register b);
aoqi@0	199
aoqi@0	200	void emit_op0(LIR_Op0* op);
aoqi@0	201	void emit_op1(LIR_Op1* op);
aoqi@0	202	void emit_op2(LIR_Op2* op);
aoqi@0	203	void emit_op3(LIR_Op3* op);
aoqi@0	204	void emit_opBranch(LIR_OpBranch* op);
aoqi@0	205	void emit_opLabel(LIR_OpLabel* op);
aoqi@0	206	void emit_arraycopy(LIR_OpArrayCopy* op);
aoqi@0	207	void emit_updatecrc32(LIR_OpUpdateCRC32* op);
aoqi@0	208	void emit_opConvert(LIR_OpConvert* op);
aoqi@0	209	void emit_alloc_obj(LIR_OpAllocObj* op);
aoqi@0	210	void emit_alloc_array(LIR_OpAllocArray* op);
aoqi@0	211	void emit_opTypeCheck(LIR_OpTypeCheck* op);
aoqi@0	212	void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null);
aoqi@0	213	void emit_compare_and_swap(LIR_OpCompareAndSwap* op);
aoqi@0	214	void emit_lock(LIR_OpLock* op);
aoqi@0	215	void emit_call(LIR_OpJavaCall* op);
aoqi@0	216	void emit_rtcall(LIR_OpRTCall* op);
aoqi@0	217	void emit_profile_call(LIR_OpProfileCall* op);
aoqi@0	218	void emit_profile_type(LIR_OpProfileType* op);
aoqi@0	219	void emit_delay(LIR_OpDelay* op);
aoqi@0	220
aoqi@0	221	void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
aoqi@1	222	#ifdef MIPS64
aoqi@1	223	void arithmetic_frem(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info = NULL);
aoqi@1	224	#endif
aoqi@0	225	void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);
aoqi@0	226	void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);
aoqi@0	227	#ifdef ASSERT
aoqi@0	228	void emit_assert(LIR_OpAssert* op);
aoqi@0	229	#endif
aoqi@0	230
aoqi@0	231	void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
aoqi@0	232
aoqi@0	233	void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);
aoqi@0	234	void move_op(LIR_Opr src, LIR_Opr result, BasicType type,
aoqi@0	235	LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide);
aoqi@0	236	void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);
aoqi@0	237	void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions
aoqi@0	238	void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);
aoqi@0	239	void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type);
aoqi@0	240
aoqi@0	241	void call( LIR_OpJavaCall* op, relocInfo::relocType rtype);
aoqi@0	242	void ic_call( LIR_OpJavaCall* op);
aoqi@0	243	void vtable_call( LIR_OpJavaCall* op);
aoqi@0	244
aoqi@0	245	void osr_entry();
aoqi@0	246
aoqi@0	247	void build_frame();
aoqi@0	248
aoqi@0	249	void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info);
aoqi@0	250	void unwind_op(LIR_Opr exceptionOop);
aoqi@0	251	void monitor_address(int monitor_ix, LIR_Opr dst);
aoqi@0	252
aoqi@0	253	void align_backward_branch_target();
aoqi@0	254	void align_call(LIR_Code code);
aoqi@0	255
aoqi@0	256	void negate(LIR_Opr left, LIR_Opr dest);
aoqi@0	257	void leal(LIR_Opr left, LIR_Opr dest);
aoqi@0	258
aoqi@0	259	void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);
aoqi@0	260
aoqi@0	261	void membar();
aoqi@0	262	void membar_acquire();
aoqi@0	263	void membar_release();
aoqi@0	264	void membar_loadload();
aoqi@0	265	void membar_storestore();
aoqi@0	266	void membar_loadstore();
aoqi@0	267	void membar_storeload();
aoqi@0	268	void get_thread(LIR_Opr result);
aoqi@0	269
aoqi@0	270	void verify_oop_map(CodeEmitInfo* info);
aoqi@0	271
aoqi@0	272	void atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp);
aoqi@0	273
aoqi@0	274	#ifdef TARGET_ARCH_x86
aoqi@0	275	# include "c1_LIRAssembler_x86.hpp"
aoqi@0	276	#endif
aoqi@1	277	#ifdef TARGET_ARCH_mips
aoqi@1	278	# include "c1_LIRAssembler_mips.hpp"
aoqi@1	279	#endif
aoqi@0	280	#ifdef TARGET_ARCH_sparc
aoqi@0	281	# include "c1_LIRAssembler_sparc.hpp"
aoqi@0	282	#endif
aoqi@0	283	#ifdef TARGET_ARCH_arm
aoqi@0	284	# include "c1_LIRAssembler_arm.hpp"
aoqi@0	285	#endif
aoqi@0	286	#ifdef TARGET_ARCH_ppc
aoqi@0	287	# include "c1_LIRAssembler_ppc.hpp"
aoqi@0	288	#endif
aoqi@0	289
aoqi@0	290	};
aoqi@0	291
aoqi@0	292	#endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP