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src/cpu/sparc/vm/assembler_sparc.hpp@a6e09d6dd8e5 (annotated)

src/cpu/sparc/vm/assembler_sparc.hpp

Wed, 24 Apr 2013 20:55:28 -0400

author

dlong

date

Wed, 24 Apr 2013 20:55:28 -0400

changeset 5000

a6e09d6dd8e5

parent 4412

ffa87474d7a4

child 5283

46c544b8fbfc

permissions

-rw-r--r--

8003853: specify offset of IC load in java_to_interp stub
Summary: refactored code to allow platform-specific differences
Reviewed-by: dlong, twisti
Contributed-by: Goetz Lindenmaier <goetz.lindenmaier@sap.com>

duke@435	1	/*
never@3500	2	* Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
duke@435	3	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	*
duke@435	5	* This code is free software; you can redistribute it and/or modify it
duke@435	6	* under the terms of the GNU General Public License version 2 only, as
duke@435	7	* published by the Free Software Foundation.
duke@435	8	*
duke@435	9	* This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	* version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	* accompanied this code).
duke@435	14	*
duke@435	15	* You should have received a copy of the GNU General Public License version
duke@435	16	* 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	*
trims@1907	19	* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907	20	* or visit www.oracle.com if you need additional information or have any
trims@1907	21	* questions.
duke@435	22	*
duke@435	23	*/
duke@435	24
stefank@2314	25	#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
stefank@2314	26	#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
stefank@2314	27
twisti@4323	28	#include "asm/register.hpp"
duke@435	29
duke@435	30	// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
duke@435	31	// level; i.e., what you write
duke@435	32	// is what you get. The Assembler is generating code into a CodeBuffer.
duke@435	33
duke@435	34	class Assembler : public AbstractAssembler {
duke@435	35	friend class AbstractAssembler;
twisti@1162	36	friend class AddressLiteral;
duke@435	37
duke@435	38	// code patchers need various routines like inv_wdisp()
duke@435	39	friend class NativeInstruction;
duke@435	40	friend class NativeGeneralJump;
duke@435	41	friend class Relocation;
duke@435	42	friend class Label;
duke@435	43
duke@435	44	public:
duke@435	45	// op carries format info; see page 62 & 267
duke@435	46
duke@435	47	enum ops {
duke@435	48	call_op = 1, // fmt 1
duke@435	49	branch_op = 0, // also sethi (fmt2)
duke@435	50	arith_op = 2, // fmt 3, arith & misc
duke@435	51	ldst_op = 3 // fmt 3, load/store
duke@435	52	};
duke@435	53
duke@435	54	enum op2s {
duke@435	55	bpr_op2 = 3,
duke@435	56	fb_op2 = 6,
duke@435	57	fbp_op2 = 5,
duke@435	58	br_op2 = 2,
duke@435	59	bp_op2 = 1,
duke@435	60	cb_op2 = 7, // V8
duke@435	61	sethi_op2 = 4
duke@435	62	};
duke@435	63
duke@435	64	enum op3s {
duke@435	65	// selected op3s
duke@435	66	add_op3 = 0x00,
duke@435	67	and_op3 = 0x01,
duke@435	68	or_op3 = 0x02,
duke@435	69	xor_op3 = 0x03,
duke@435	70	sub_op3 = 0x04,
duke@435	71	andn_op3 = 0x05,
duke@435	72	orn_op3 = 0x06,
duke@435	73	xnor_op3 = 0x07,
duke@435	74	addc_op3 = 0x08,
duke@435	75	mulx_op3 = 0x09,
duke@435	76	umul_op3 = 0x0a,
duke@435	77	smul_op3 = 0x0b,
duke@435	78	subc_op3 = 0x0c,
duke@435	79	udivx_op3 = 0x0d,
duke@435	80	udiv_op3 = 0x0e,
duke@435	81	sdiv_op3 = 0x0f,
duke@435	82
duke@435	83	addcc_op3 = 0x10,
duke@435	84	andcc_op3 = 0x11,
duke@435	85	orcc_op3 = 0x12,
duke@435	86	xorcc_op3 = 0x13,
duke@435	87	subcc_op3 = 0x14,
duke@435	88	andncc_op3 = 0x15,
duke@435	89	orncc_op3 = 0x16,
duke@435	90	xnorcc_op3 = 0x17,
duke@435	91	addccc_op3 = 0x18,
duke@435	92	umulcc_op3 = 0x1a,
duke@435	93	smulcc_op3 = 0x1b,
duke@435	94	subccc_op3 = 0x1c,
duke@435	95	udivcc_op3 = 0x1e,
duke@435	96	sdivcc_op3 = 0x1f,
duke@435	97
duke@435	98	taddcc_op3 = 0x20,
duke@435	99	tsubcc_op3 = 0x21,
duke@435	100	taddcctv_op3 = 0x22,
duke@435	101	tsubcctv_op3 = 0x23,
duke@435	102	mulscc_op3 = 0x24,
duke@435	103	sll_op3 = 0x25,
duke@435	104	sllx_op3 = 0x25,
duke@435	105	srl_op3 = 0x26,
duke@435	106	srlx_op3 = 0x26,
duke@435	107	sra_op3 = 0x27,
duke@435	108	srax_op3 = 0x27,
duke@435	109	rdreg_op3 = 0x28,
duke@435	110	membar_op3 = 0x28,
duke@435	111
duke@435	112	flushw_op3 = 0x2b,
duke@435	113	movcc_op3 = 0x2c,
duke@435	114	sdivx_op3 = 0x2d,
duke@435	115	popc_op3 = 0x2e,
duke@435	116	movr_op3 = 0x2f,
duke@435	117
duke@435	118	sir_op3 = 0x30,
duke@435	119	wrreg_op3 = 0x30,
duke@435	120	saved_op3 = 0x31,
duke@435	121
duke@435	122	fpop1_op3 = 0x34,
duke@435	123	fpop2_op3 = 0x35,
duke@435	124	impdep1_op3 = 0x36,
duke@435	125	impdep2_op3 = 0x37,
duke@435	126	jmpl_op3 = 0x38,
duke@435	127	rett_op3 = 0x39,
duke@435	128	trap_op3 = 0x3a,
duke@435	129	flush_op3 = 0x3b,
duke@435	130	save_op3 = 0x3c,
duke@435	131	restore_op3 = 0x3d,
duke@435	132	done_op3 = 0x3e,
duke@435	133	retry_op3 = 0x3e,
duke@435	134
duke@435	135	lduw_op3 = 0x00,
duke@435	136	ldub_op3 = 0x01,
duke@435	137	lduh_op3 = 0x02,
duke@435	138	ldd_op3 = 0x03,
duke@435	139	stw_op3 = 0x04,
duke@435	140	stb_op3 = 0x05,
duke@435	141	sth_op3 = 0x06,
duke@435	142	std_op3 = 0x07,
duke@435	143	ldsw_op3 = 0x08,
duke@435	144	ldsb_op3 = 0x09,
duke@435	145	ldsh_op3 = 0x0a,
duke@435	146	ldx_op3 = 0x0b,
duke@435	147
duke@435	148	ldstub_op3 = 0x0d,
duke@435	149	stx_op3 = 0x0e,
duke@435	150	swap_op3 = 0x0f,
duke@435	151
duke@435	152	stwa_op3 = 0x14,
duke@435	153	stxa_op3 = 0x1e,
duke@435	154
duke@435	155	ldf_op3 = 0x20,
duke@435	156	ldfsr_op3 = 0x21,
duke@435	157	ldqf_op3 = 0x22,
duke@435	158	lddf_op3 = 0x23,
duke@435	159	stf_op3 = 0x24,
duke@435	160	stfsr_op3 = 0x25,
duke@435	161	stqf_op3 = 0x26,
duke@435	162	stdf_op3 = 0x27,
duke@435	163
duke@435	164	prefetch_op3 = 0x2d,
duke@435	165
duke@435	166
duke@435	167	ldc_op3 = 0x30,
duke@435	168	ldcsr_op3 = 0x31,
duke@435	169	lddc_op3 = 0x33,
duke@435	170	stc_op3 = 0x34,
duke@435	171	stcsr_op3 = 0x35,
duke@435	172	stdcq_op3 = 0x36,
duke@435	173	stdc_op3 = 0x37,
duke@435	174
duke@435	175	casa_op3 = 0x3c,
duke@435	176	casxa_op3 = 0x3e,
duke@435	177
kvn@3001	178	mftoi_op3 = 0x36,
kvn@3001	179
duke@435	180	alt_bit_op3 = 0x10,
duke@435	181	cc_bit_op3 = 0x10
duke@435	182	};
duke@435	183
duke@435	184	enum opfs {
duke@435	185	// selected opfs
duke@435	186	fmovs_opf = 0x01,
duke@435	187	fmovd_opf = 0x02,
duke@435	188
duke@435	189	fnegs_opf = 0x05,
duke@435	190	fnegd_opf = 0x06,
duke@435	191
duke@435	192	fadds_opf = 0x41,
duke@435	193	faddd_opf = 0x42,
duke@435	194	fsubs_opf = 0x45,
duke@435	195	fsubd_opf = 0x46,
duke@435	196
duke@435	197	fmuls_opf = 0x49,
duke@435	198	fmuld_opf = 0x4a,
duke@435	199	fdivs_opf = 0x4d,
duke@435	200	fdivd_opf = 0x4e,
duke@435	201
duke@435	202	fcmps_opf = 0x51,
duke@435	203	fcmpd_opf = 0x52,
duke@435	204
duke@435	205	fstox_opf = 0x81,
duke@435	206	fdtox_opf = 0x82,
duke@435	207	fxtos_opf = 0x84,
duke@435	208	fxtod_opf = 0x88,
duke@435	209	fitos_opf = 0xc4,
duke@435	210	fdtos_opf = 0xc6,
duke@435	211	fitod_opf = 0xc8,
duke@435	212	fstod_opf = 0xc9,
duke@435	213	fstoi_opf = 0xd1,
kvn@3001	214	fdtoi_opf = 0xd2,
kvn@3001	215
kvn@3001	216	mdtox_opf = 0x110,
kvn@3001	217	mstouw_opf = 0x111,
kvn@3001	218	mstosw_opf = 0x113,
kvn@3001	219	mxtod_opf = 0x118,
kvn@3001	220	mwtos_opf = 0x119
duke@435	221	};
duke@435	222
kvn@3037	223	enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
duke@435	224
duke@435	225	enum Condition {
duke@435	226	// for FBfcc & FBPfcc instruction
duke@435	227	f_never = 0,
duke@435	228	f_notEqual = 1,
duke@435	229	f_notZero = 1,
duke@435	230	f_lessOrGreater = 2,
duke@435	231	f_unorderedOrLess = 3,
duke@435	232	f_less = 4,
duke@435	233	f_unorderedOrGreater = 5,
duke@435	234	f_greater = 6,
duke@435	235	f_unordered = 7,
duke@435	236	f_always = 8,
duke@435	237	f_equal = 9,
duke@435	238	f_zero = 9,
duke@435	239	f_unorderedOrEqual = 10,
duke@435	240	f_greaterOrEqual = 11,
duke@435	241	f_unorderedOrGreaterOrEqual = 12,
duke@435	242	f_lessOrEqual = 13,
duke@435	243	f_unorderedOrLessOrEqual = 14,
duke@435	244	f_ordered = 15,
duke@435	245
duke@435	246	// V8 coproc, pp 123 v8 manual
duke@435	247
duke@435	248	cp_always = 8,
duke@435	249	cp_never = 0,
duke@435	250	cp_3 = 7,
duke@435	251	cp_2 = 6,
duke@435	252	cp_2or3 = 5,
duke@435	253	cp_1 = 4,
duke@435	254	cp_1or3 = 3,
duke@435	255	cp_1or2 = 2,
duke@435	256	cp_1or2or3 = 1,
duke@435	257	cp_0 = 9,
duke@435	258	cp_0or3 = 10,
duke@435	259	cp_0or2 = 11,
duke@435	260	cp_0or2or3 = 12,
duke@435	261	cp_0or1 = 13,
duke@435	262	cp_0or1or3 = 14,
duke@435	263	cp_0or1or2 = 15,
duke@435	264
duke@435	265
duke@435	266	// for integers
duke@435	267
duke@435	268	never = 0,
duke@435	269	equal = 1,
duke@435	270	zero = 1,
duke@435	271	lessEqual = 2,
duke@435	272	less = 3,
duke@435	273	lessEqualUnsigned = 4,
duke@435	274	lessUnsigned = 5,
duke@435	275	carrySet = 5,
duke@435	276	negative = 6,
duke@435	277	overflowSet = 7,
duke@435	278	always = 8,
duke@435	279	notEqual = 9,
duke@435	280	notZero = 9,
duke@435	281	greater = 10,
duke@435	282	greaterEqual = 11,
duke@435	283	greaterUnsigned = 12,
duke@435	284	greaterEqualUnsigned = 13,
duke@435	285	carryClear = 13,
duke@435	286	positive = 14,
duke@435	287	overflowClear = 15
duke@435	288	};
duke@435	289
duke@435	290	enum CC {
duke@435	291	icc = 0, xcc = 2,
duke@435	292	// ptr_cc is the correct condition code for a pointer or intptr_t:
duke@435	293	ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
duke@435	294	fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
duke@435	295	};
duke@435	296
duke@435	297	enum PrefetchFcn {
duke@435	298	severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
duke@435	299	};
duke@435	300
duke@435	301	public:
duke@435	302	// Helper functions for groups of instructions
duke@435	303
duke@435	304	enum Predict { pt = 1, pn = 0 }; // pt = predict taken
duke@435	305
duke@435	306	enum Membar_mask_bits { // page 184, v9
duke@435	307	StoreStore = 1 << 3,
duke@435	308	LoadStore = 1 << 2,
duke@435	309	StoreLoad = 1 << 1,
duke@435	310	LoadLoad = 1 << 0,
duke@435	311
duke@435	312	Sync = 1 << 6,
duke@435	313	MemIssue = 1 << 5,
duke@435	314	Lookaside = 1 << 4
duke@435	315	};
duke@435	316
iveresov@2441	317	static bool is_in_wdisp_range(address a, address b, int nbits) {
iveresov@2441	318	intptr_t d = intptr_t(b) - intptr_t(a);
iveresov@2441	319	return is_simm(d, nbits + 2);
iveresov@2441	320	}
duke@435	321
kvn@3037	322	address target_distance(Label& L) {
kvn@3037	323	// Assembler::target(L) should be called only when
kvn@3037	324	// a branch instruction is emitted since non-bound
kvn@3037	325	// labels record current pc() as a branch address.
kvn@3037	326	if (L.is_bound()) return target(L);
kvn@3037	327	// Return current address for non-bound labels.
kvn@3037	328	return pc();
kvn@3037	329	}
kvn@3037	330
iveresov@2203	331	// test if label is in simm16 range in words (wdisp16).
iveresov@2203	332	bool is_in_wdisp16_range(Label& L) {
kvn@3037	333	return is_in_wdisp_range(target_distance(L), pc(), 16);
iveresov@2441	334	}
iveresov@2441	335	// test if the distance between two addresses fits in simm30 range in words
iveresov@2441	336	static bool is_in_wdisp30_range(address a, address b) {
iveresov@2441	337	return is_in_wdisp_range(a, b, 30);
iveresov@2203	338	}
iveresov@2203	339
duke@435	340	enum ASIs { // page 72, v9
kvn@3092	341	ASI_PRIMARY = 0x80,
kvn@3092	342	ASI_PRIMARY_NOFAULT = 0x82,
kvn@3092	343	ASI_PRIMARY_LITTLE = 0x88,
kvn@3052	344	// Block initializing store
kvn@3052	345	ASI_ST_BLKINIT_PRIMARY = 0xE2,
kvn@3052	346	// Most-Recently-Used (MRU) BIS variant
kvn@3052	347	ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
duke@435	348	// add more from book as needed
duke@435	349	};
duke@435	350
duke@435	351	protected:
duke@435	352	// helpers
duke@435	353
duke@435	354	// x is supposed to fit in a field "nbits" wide
duke@435	355	// and be sign-extended. Check the range.
duke@435	356
duke@435	357	static void assert_signed_range(intptr_t x, int nbits) {
never@2950	358	assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
never@2950	359	err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
duke@435	360	}
duke@435	361
duke@435	362	static void assert_signed_word_disp_range(intptr_t x, int nbits) {
duke@435	363	assert( (x & 3) == 0, "not word aligned");
duke@435	364	assert_signed_range(x, nbits + 2);
duke@435	365	}
duke@435	366
duke@435	367	static void assert_unsigned_const(int x, int nbits) {
duke@435	368	assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
duke@435	369	}
duke@435	370
duke@435	371	// fields: note bits numbered from LSB = 0,
duke@435	372	// fields known by inclusive bit range
duke@435	373
duke@435	374	static int fmask(juint hi_bit, juint lo_bit) {
duke@435	375	assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
duke@435	376	return (1 << ( hi_bit-lo_bit + 1 )) - 1;
duke@435	377	}
duke@435	378
duke@435	379	// inverse of u_field
duke@435	380
duke@435	381	static int inv_u_field(int x, int hi_bit, int lo_bit) {
duke@435	382	juint r = juint(x) >> lo_bit;
duke@435	383	r &= fmask( hi_bit, lo_bit);
duke@435	384	return int(r);
duke@435	385	}
duke@435	386
duke@435	387
duke@435	388	// signed version: extract from field and sign-extend
duke@435	389
duke@435	390	static int inv_s_field(int x, int hi_bit, int lo_bit) {
duke@435	391	int sign_shift = 31 - hi_bit;
duke@435	392	return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
duke@435	393	}
duke@435	394
duke@435	395	// given a field that ranges from hi_bit to lo_bit (inclusive,
duke@435	396	// LSB = 0), and an unsigned value for the field,
duke@435	397	// shift it into the field
duke@435	398
duke@435	399	#ifdef ASSERT
duke@435	400	static int u_field(int x, int hi_bit, int lo_bit) {
duke@435	401	assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
duke@435	402	"value out of range");
duke@435	403	int r = x << lo_bit;
duke@435	404	assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
duke@435	405	return r;
duke@435	406	}
duke@435	407	#else
duke@435	408	// make sure this is inlined as it will reduce code size significantly
duke@435	409	#define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
duke@435	410	#endif
duke@435	411
duke@435	412	static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
duke@435	413	static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
duke@435	414	static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
duke@435	415	static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
duke@435	416
duke@435	417	static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
duke@435	418
duke@435	419	static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
duke@435	420	static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
duke@435	421	static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
duke@435	422
duke@435	423	static int op( int x) { return u_field(x, 31, 30); }
duke@435	424	static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
duke@435	425	static int fcn( int x) { return u_field(x, 29, 25); }
duke@435	426	static int op3( int x) { return u_field(x, 24, 19); }
duke@435	427	static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
duke@435	428	static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
duke@435	429	static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
duke@435	430	static int cond( int x) { return u_field(x, 28, 25); }
duke@435	431	static int cond_mov( int x) { return u_field(x, 17, 14); }
duke@435	432	static int rcond( RCondition x) { return u_field(x, 12, 10); }
duke@435	433	static int op2( int x) { return u_field(x, 24, 22); }
duke@435	434	static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
duke@435	435	static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
duke@435	436	static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
duke@435	437	static int imm_asi( int x) { return u_field(x, 12, 5); }
duke@435	438	static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
duke@435	439	static int opf_low6( int w) { return u_field(w, 10, 5); }
duke@435	440	static int opf_low5( int w) { return u_field(w, 9, 5); }
duke@435	441	static int trapcc( CC cc) { return u_field(cc, 12, 11); }
duke@435	442	static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
duke@435	443	static int opf( int x) { return u_field(x, 13, 5); }
duke@435	444
kvn@3037	445	static bool is_cbcond( int x ) {
kvn@3037	446	return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
kvn@3037	447	inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
kvn@3037	448	}
kvn@3037	449	static bool is_cxb( int x ) {
kvn@3037	450	assert(is_cbcond(x), "wrong instruction");
kvn@3037	451	return (x & (1<<21)) != 0;
kvn@3037	452	}
kvn@3037	453	static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
kvn@3037	454	static int inv_cond_cbcond(int x) {
kvn@3037	455	assert(is_cbcond(x), "wrong instruction");
kvn@3037	456	return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
kvn@3037	457	}
kvn@3037	458
duke@435	459	static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
duke@435	460	static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
duke@435	461
duke@435	462	static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
duke@435	463	static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
duke@435	464	static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
duke@435	465
duke@435	466	// some float instructions use this encoding on the op3 field
duke@435	467	static int alt_op3(int op, FloatRegisterImpl::Width w) {
duke@435	468	int r;
duke@435	469	switch(w) {
duke@435	470	case FloatRegisterImpl::S: r = op + 0; break;
duke@435	471	case FloatRegisterImpl::D: r = op + 3; break;
duke@435	472	case FloatRegisterImpl::Q: r = op + 2; break;
duke@435	473	default: ShouldNotReachHere(); break;
duke@435	474	}
duke@435	475	return op3(r);
duke@435	476	}
duke@435	477
duke@435	478
duke@435	479	// compute inverse of simm
duke@435	480	static int inv_simm(int x, int nbits) {
duke@435	481	return (int)(x << (32 - nbits)) >> (32 - nbits);
duke@435	482	}
duke@435	483
duke@435	484	static int inv_simm13( int x ) { return inv_simm(x, 13); }
duke@435	485
duke@435	486	// signed immediate, in low bits, nbits long
duke@435	487	static int simm(int x, int nbits) {
duke@435	488	assert_signed_range(x, nbits);
duke@435	489	return x & (( 1 << nbits ) - 1);
duke@435	490	}
duke@435	491
duke@435	492	// compute inverse of wdisp16
duke@435	493	static intptr_t inv_wdisp16(int x, intptr_t pos) {
duke@435	494	int lo = x & (( 1 << 14 ) - 1);
duke@435	495	int hi = (x >> 20) & 3;
duke@435	496	if (hi >= 2) hi |= ~1;
duke@435	497	return (((hi << 14) | lo) << 2) + pos;
duke@435	498	}
duke@435	499
duke@435	500	// word offset, 14 bits at LSend, 2 bits at B21, B20
duke@435	501	static int wdisp16(intptr_t x, intptr_t off) {
duke@435	502	intptr_t xx = x - off;
duke@435	503	assert_signed_word_disp_range(xx, 16);
duke@435	504	int r = (xx >> 2) & ((1 << 14) - 1)
duke@435	505	| ( ( (xx>>(2+14)) & 3 ) << 20 );
duke@435	506	assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
duke@435	507	return r;
duke@435	508	}
duke@435	509
kvn@3037	510	// compute inverse of wdisp10
kvn@3037	511	static intptr_t inv_wdisp10(int x, intptr_t pos) {
kvn@3037	512	assert(is_cbcond(x), "wrong instruction");
kvn@3037	513	int lo = inv_u_field(x, 12, 5);
kvn@3037	514	int hi = (x >> 19) & 3;
kvn@3037	515	if (hi >= 2) hi |= ~1;
kvn@3037	516	return (((hi << 8) | lo) << 2) + pos;
kvn@3037	517	}
kvn@3037	518
kvn@3037	519	// word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
kvn@3037	520	static int wdisp10(intptr_t x, intptr_t off) {
kvn@3037	521	assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
kvn@3037	522	intptr_t xx = x - off;
kvn@3037	523	assert_signed_word_disp_range(xx, 10);
kvn@3037	524	int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
kvn@3037	525	| ( ( (xx >> (2+8)) & 3 ) << 19 );
kvn@3037	526	// Have to fake cbcond instruction to pass assert in inv_wdisp10()
kvn@3037	527	assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
kvn@3037	528	return r;
kvn@3037	529	}
duke@435	530
duke@435	531	// word displacement in low-order nbits bits
duke@435	532
duke@435	533	static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
duke@435	534	int pre_sign_extend = x & (( 1 << nbits ) - 1);
duke@435	535	int r = pre_sign_extend >= ( 1 << (nbits-1) )
duke@435	536	? pre_sign_extend | ~(( 1 << nbits ) - 1)
duke@435	537	: pre_sign_extend;
duke@435	538	return (r << 2) + pos;
duke@435	539	}
duke@435	540
duke@435	541	static int wdisp( intptr_t x, intptr_t off, int nbits ) {
duke@435	542	intptr_t xx = x - off;
duke@435	543	assert_signed_word_disp_range(xx, nbits);
duke@435	544	int r = (xx >> 2) & (( 1 << nbits ) - 1);
duke@435	545	assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
duke@435	546	return r;
duke@435	547	}
duke@435	548
duke@435	549
duke@435	550	// Extract the top 32 bits in a 64 bit word
duke@435	551	static int32_t hi32( int64_t x ) {
duke@435	552	int32_t r = int32_t( (uint64_t)x >> 32 );
duke@435	553	return r;
duke@435	554	}
duke@435	555
duke@435	556	// given a sethi instruction, extract the constant, left-justified
duke@435	557	static int inv_hi22( int x ) {
duke@435	558	return x << 10;
duke@435	559	}
duke@435	560
duke@435	561	// create an imm22 field, given a 32-bit left-justified constant
duke@435	562	static int hi22( int x ) {
duke@435	563	int r = int( juint(x) >> 10 );
duke@435	564	assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
duke@435	565	return r;
duke@435	566	}
duke@435	567
duke@435	568	// create a low10 __value__ (not a field) for a given a 32-bit constant
duke@435	569	static int low10( int x ) {
duke@435	570	return x & ((1 << 10) - 1);
duke@435	571	}
duke@435	572
kvn@3001	573	// instruction only in VIS3
kvn@3001	574	static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
kvn@3001	575
duke@435	576	// instruction only in v9
duke@435	577	static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
duke@435	578
duke@435	579	// instruction only in v8
duke@435	580	static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
duke@435	581
duke@435	582	// instruction deprecated in v9
duke@435	583	static void v9_dep() { } // do nothing for now
duke@435	584
duke@435	585	// some float instructions only exist for single prec. on v8
duke@435	586	static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); }
duke@435	587
duke@435	588	// v8 has no CC field
duke@435	589	static void v8_no_cc(CC cc) { if (cc) v9_only(); }
duke@435	590
duke@435	591	protected:
duke@435	592	// Simple delay-slot scheme:
duke@435	593	// In order to check the programmer, the assembler keeps track of deley slots.
duke@435	594	// It forbids CTIs in delay slots (conservative, but should be OK).
duke@435	595	// Also, when putting an instruction into a delay slot, you must say
duke@435	596	// asm->delayed()->add(...), in order to check that you don't omit
duke@435	597	// delay-slot instructions.
duke@435	598	// To implement this, we use a simple FSA
duke@435	599
duke@435	600	#ifdef ASSERT
duke@435	601	#define CHECK_DELAY
duke@435	602	#endif
duke@435	603	#ifdef CHECK_DELAY
duke@435	604	enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
duke@435	605	#endif
duke@435	606
duke@435	607	public:
duke@435	608	// Tells assembler next instruction must NOT be in delay slot.
duke@435	609	// Use at start of multinstruction macros.
duke@435	610	void assert_not_delayed() {
duke@435	611	// This is a separate overloading to avoid creation of string constants
duke@435	612	// in non-asserted code--with some compilers this pollutes the object code.
duke@435	613	#ifdef CHECK_DELAY
duke@435	614	assert_not_delayed("next instruction should not be a delay slot");
duke@435	615	#endif
duke@435	616	}
duke@435	617	void assert_not_delayed(const char* msg) {
duke@435	618	#ifdef CHECK_DELAY
jcoomes@1845	619	assert(delay_state == no_delay, msg);
duke@435	620	#endif
duke@435	621	}
duke@435	622
duke@435	623	protected:
duke@435	624	// Delay slot helpers
duke@435	625	// cti is called when emitting control-transfer instruction,
duke@435	626	// BEFORE doing the emitting.
duke@435	627	// Only effective when assertion-checking is enabled.
duke@435	628	void cti() {
duke@435	629	#ifdef CHECK_DELAY
duke@435	630	assert_not_delayed("cti should not be in delay slot");
duke@435	631	#endif
duke@435	632	}
duke@435	633
duke@435	634	// called when emitting cti with a delay slot, AFTER emitting
duke@435	635	void has_delay_slot() {
duke@435	636	#ifdef CHECK_DELAY
duke@435	637	assert_not_delayed("just checking");
duke@435	638	delay_state = at_delay_slot;
duke@435	639	#endif
duke@435	640	}
duke@435	641
kvn@3037	642	// cbcond instruction should not be generated one after an other
kvn@3037	643	bool cbcond_before() {
kvn@3037	644	if (offset() == 0) return false; // it is first instruction
kvn@3037	645	int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
kvn@3037	646	return is_cbcond(x);
kvn@3037	647	}
kvn@3037	648
kvn@3037	649	void no_cbcond_before() {
kvn@3037	650	assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
kvn@3037	651	}
kvn@3037	652
kvn@3049	653	public:
kvn@3049	654
kvn@3037	655	bool use_cbcond(Label& L) {
kvn@3037	656	if (!UseCBCond || cbcond_before()) return false;
kvn@3037	657	intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
kvn@3037	658	assert( (x & 3) == 0, "not word aligned");
twisti@3310	659	return is_simm12(x);
kvn@3037	660	}
kvn@3037	661
duke@435	662	// Tells assembler you know that next instruction is delayed
duke@435	663	Assembler* delayed() {
duke@435	664	#ifdef CHECK_DELAY
duke@435	665	assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
duke@435	666	delay_state = filling_delay_slot;
duke@435	667	#endif
duke@435	668	return this;
duke@435	669	}
duke@435	670
duke@435	671	void flush() {
duke@435	672	#ifdef CHECK_DELAY
duke@435	673	assert ( delay_state == no_delay, "ending code with a delay slot");
duke@435	674	#endif
duke@435	675	AbstractAssembler::flush();
duke@435	676	}
duke@435	677
twisti@4412	678	inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
twisti@4412	679	inline void emit_data(int x) { emit_int32(x); }
duke@435	680	inline void emit_data(int, RelocationHolder const&);
duke@435	681	inline void emit_data(int, relocInfo::relocType rtype);
duke@435	682	// helper for above fcns
duke@435	683	inline void check_delay();
duke@435	684
duke@435	685
duke@435	686	public:
duke@435	687	// instructions, refer to page numbers in the SPARC Architecture Manual, V9
duke@435	688
duke@435	689	// pp 135 (addc was addx in v8)
duke@435	690
twisti@1162	691	inline void add(Register s1, Register s2, Register d );
twisti@4323	692	inline void add(Register s1, int simm13a, Register d );
duke@435	693
twisti@4412	694	void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	695	void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	696	void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	697	void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	698	void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	699	void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	700
kvn@3037	701
duke@435	702	// pp 136
duke@435	703
kvn@3037	704	inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
kvn@3037	705	inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
duke@435	706
kvn@3037	707	// compare and branch
kvn@3037	708	inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
kvn@3037	709	inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
kvn@3037	710
kvn@3049	711	protected: // use MacroAssembler::br instead
kvn@3049	712
kvn@3049	713	// pp 138
kvn@3049	714
kvn@3049	715	inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	716	inline void fb( Condition c, bool a, Label& L );
kvn@3049	717
kvn@3049	718	// pp 141
kvn@3049	719
kvn@3049	720	inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	721	inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
kvn@3049	722
kvn@3049	723	// pp 144
kvn@3049	724
kvn@3049	725	inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	726	inline void br( Condition c, bool a, Label& L );
kvn@3049	727
kvn@3049	728	// pp 146
kvn@3049	729
kvn@3049	730	inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	731	inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
kvn@3049	732
kvn@3049	733	// pp 121 (V8)
kvn@3049	734
kvn@3049	735	inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
kvn@3049	736	inline void cb( Condition c, bool a, Label& L );
kvn@3049	737
duke@435	738	// pp 149
duke@435	739
duke@435	740	inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
duke@435	741	inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
duke@435	742
kvn@3037	743	public:
kvn@3037	744
duke@435	745	// pp 150
duke@435	746
duke@435	747	// These instructions compare the contents of s2 with the contents of
duke@435	748	// memory at address in s1. If the values are equal, the contents of memory
duke@435	749	// at address s1 is swapped with the data in d. If the values are not equal,
duke@435	750	// the the contents of memory at s1 is loaded into d, without the swap.
duke@435	751
twisti@4412	752	void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
twisti@4412	753	void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
duke@435	754
duke@435	755	// pp 152
duke@435	756
twisti@4412	757	void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
twisti@4412	758	void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	759	void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
twisti@4412	760	void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	761	void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
twisti@4412	762	void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	763	void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
twisti@4412	764	void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	765
duke@435	766	// pp 155
duke@435	767
twisti@4412	768	void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
twisti@4412	769	void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
duke@435	770
duke@435	771	// pp 156
duke@435	772
twisti@4412	773	void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
twisti@4412	774	void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
duke@435	775
duke@435	776	// pp 157
duke@435	777
twisti@4412	778	void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
twisti@4412	779	void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
duke@435	780
duke@435	781	// pp 159
duke@435	782
twisti@4412	783	void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
twisti@4412	784	void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
duke@435	785
duke@435	786	// pp 160
duke@435	787
twisti@4412	788	void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
duke@435	789
duke@435	790	// pp 161
duke@435	791
twisti@4412	792	void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
twisti@4412	793	void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
duke@435	794
duke@435	795	// pp 162
duke@435	796
twisti@4412	797	void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
duke@435	798
twisti@4412	799	void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
duke@435	800
duke@435	801	// page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
duke@435	802	// on v8 to do negation of single, double and quad precision floats.
duke@435	803
twisti@4412	804	void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); }
duke@435	805
twisti@4412	806	void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
duke@435	807
duke@435	808	// page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
duke@435	809	// on v8 to do abs operation on single/double/quad precision floats.
duke@435	810
twisti@4412	811	void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
duke@435	812
duke@435	813	// pp 163
duke@435	814
twisti@4412	815	void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
twisti@4412	816	void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
twisti@4412	817	void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
duke@435	818
duke@435	819	// pp 164
duke@435	820
twisti@4412	821	void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
duke@435	822
duke@435	823	// pp 165
duke@435	824
duke@435	825	inline void flush( Register s1, Register s2 );
duke@435	826	inline void flush( Register s1, int simm13a);
duke@435	827
duke@435	828	// pp 167
duke@435	829
twisti@4412	830	void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); }
duke@435	831
duke@435	832	// pp 168
duke@435	833
twisti@4412	834	void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
duke@435	835	// v8 unimp == illtrap(0)
duke@435	836
duke@435	837	// pp 169
duke@435	838
twisti@4412	839	void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
twisti@4412	840	void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
duke@435	841
duke@435	842	// pp 149 (v8)
duke@435	843
twisti@4412	844	void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_int32( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
twisti@4412	845	void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_int32( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
duke@435	846
duke@435	847	// pp 170
duke@435	848
duke@435	849	void jmpl( Register s1, Register s2, Register d );
duke@435	850	void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
duke@435	851
duke@435	852	// 171
duke@435	853
twisti@1162	854	inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
twisti@1162	855	inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
twisti@1162	856
duke@435	857
duke@435	858	inline void ldfsr( Register s1, Register s2 );
duke@435	859	inline void ldfsr( Register s1, int simm13a);
duke@435	860	inline void ldxfsr( Register s1, Register s2 );
duke@435	861	inline void ldxfsr( Register s1, int simm13a);
duke@435	862
duke@435	863	// pp 94 (v8)
duke@435	864
duke@435	865	inline void ldc( Register s1, Register s2, int crd );
duke@435	866	inline void ldc( Register s1, int simm13a, int crd);
duke@435	867	inline void lddc( Register s1, Register s2, int crd );
duke@435	868	inline void lddc( Register s1, int simm13a, int crd);
duke@435	869	inline void ldcsr( Register s1, Register s2, int crd );
duke@435	870	inline void ldcsr( Register s1, int simm13a, int crd);
duke@435	871
duke@435	872
duke@435	873	// 173
duke@435	874
twisti@4412	875	void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	876	void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	877
duke@435	878	// pp 175, lduw is ld on v8
duke@435	879
duke@435	880	inline void ldsb( Register s1, Register s2, Register d );
duke@435	881	inline void ldsb( Register s1, int simm13a, Register d);
duke@435	882	inline void ldsh( Register s1, Register s2, Register d );
duke@435	883	inline void ldsh( Register s1, int simm13a, Register d);
duke@435	884	inline void ldsw( Register s1, Register s2, Register d );
duke@435	885	inline void ldsw( Register s1, int simm13a, Register d);
duke@435	886	inline void ldub( Register s1, Register s2, Register d );
duke@435	887	inline void ldub( Register s1, int simm13a, Register d);
duke@435	888	inline void lduh( Register s1, Register s2, Register d );
duke@435	889	inline void lduh( Register s1, int simm13a, Register d);
duke@435	890	inline void lduw( Register s1, Register s2, Register d );
duke@435	891	inline void lduw( Register s1, int simm13a, Register d);
duke@435	892	inline void ldx( Register s1, Register s2, Register d );
duke@435	893	inline void ldx( Register s1, int simm13a, Register d);
duke@435	894	inline void ldd( Register s1, Register s2, Register d );
duke@435	895	inline void ldd( Register s1, int simm13a, Register d);
duke@435	896
duke@435	897	// pp 177
duke@435	898
twisti@4412	899	void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	900	void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	901	void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	902	void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	903	void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	904	void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	905	void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	906	void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	907	void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	908	void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	909	void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	910	void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	911	void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	912	void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	913	void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	914	void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	915
duke@435	916	// pp 179
duke@435	917
duke@435	918	inline void ldstub( Register s1, Register s2, Register d );
duke@435	919	inline void ldstub( Register s1, int simm13a, Register d);
duke@435	920
duke@435	921	// pp 180
duke@435	922
twisti@4412	923	void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	924	void ldstuba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	925
duke@435	926	// pp 181
duke@435	927
twisti@4412	928	void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	929	void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	930	void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	931	void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	932	void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	933	void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	934	void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	935	void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	936	void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	937	void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	938	void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	939	void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	940	void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	941	void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	942	void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	943	void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	944	void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	945	void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	946	void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	947	void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	948	void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	949	void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	950	void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	951	void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	952
duke@435	953	// pp 183
duke@435	954
twisti@4412	955	void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
duke@435	956
duke@435	957	// pp 185
duke@435	958
twisti@4412	959	void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
duke@435	960
duke@435	961	// pp 189
duke@435	962
twisti@4412	963	void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
duke@435	964
duke@435	965	// pp 191
duke@435	966
twisti@4412	967	void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
twisti@4412	968	void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
duke@435	969
duke@435	970	// pp 195
duke@435	971
twisti@4412	972	void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
twisti@4412	973	void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
duke@435	974
duke@435	975	// pp 196
duke@435	976
twisti@4412	977	void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	978	void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	979	void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	980	void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	981	void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	982	void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	983
duke@435	984	// pp 197
duke@435	985
twisti@4412	986	void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	987	void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	988	void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	989	void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	990	void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	991	void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	992	void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	993	void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	994
duke@435	995	// pp 199
duke@435	996
twisti@4412	997	void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	998	void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	999
duke@435	1000	// pp 201
duke@435	1001
twisti@4412	1002	void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
duke@435	1003
duke@435	1004
duke@435	1005	// pp 202
duke@435	1006
twisti@4412	1007	void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
twisti@4412	1008	void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
duke@435	1009
duke@435	1010	// pp 203
duke@435	1011
twisti@4412	1012	void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
twisti@4323	1013	void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
twisti@4323	1014
twisti@4412	1015	void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1016	void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1017
duke@435	1018	// pp 208
duke@435	1019
duke@435	1020	// not implementing read privileged register
duke@435	1021
twisti@4412	1022	inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
twisti@4412	1023	inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
twisti@4412	1024	inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
twisti@4412	1025	inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
twisti@4412	1026	inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
twisti@4412	1027	inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
duke@435	1028
duke@435	1029	// pp 213
duke@435	1030
duke@435	1031	inline void rett( Register s1, Register s2);
duke@435	1032	inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
duke@435	1033
duke@435	1034	// pp 214
duke@435	1035
twisti@4412	1036	void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
ysr@777	1037	void save( Register s1, int simm13a, Register d ) {
ysr@777	1038	// make sure frame is at least large enough for the register save area
ysr@777	1039	assert(-simm13a >= 16 * wordSize, "frame too small");
twisti@4412	1040	emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
ysr@777	1041	}
duke@435	1042
twisti@4412	1043	void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	1044	void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1045
duke@435	1046	// pp 216
duke@435	1047
twisti@4412	1048	void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
twisti@4412	1049	void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
duke@435	1050
duke@435	1051	// pp 217
duke@435	1052
duke@435	1053	inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
duke@435	1054	// pp 218
duke@435	1055
twisti@4412	1056	void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
twisti@4412	1057	void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
twisti@4412	1058	void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
twisti@4412	1059	void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
twisti@4412	1060	void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
twisti@4412	1061	void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
duke@435	1062
twisti@4412	1063	void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
twisti@4412	1064	void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
twisti@4412	1065	void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
twisti@4412	1066	void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
twisti@4412	1067	void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
twisti@4412	1068	void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
duke@435	1069
duke@435	1070	// pp 220
duke@435	1071
twisti@4412	1072	void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
duke@435	1073
duke@435	1074	// pp 221
duke@435	1075
twisti@4412	1076	void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
duke@435	1077
duke@435	1078	// pp 222
duke@435	1079
twisti@1441	1080	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
duke@435	1081	inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
duke@435	1082
duke@435	1083	inline void stfsr( Register s1, Register s2 );
duke@435	1084	inline void stfsr( Register s1, int simm13a);
duke@435	1085	inline void stxfsr( Register s1, Register s2 );
duke@435	1086	inline void stxfsr( Register s1, int simm13a);
duke@435	1087
duke@435	1088	// pp 224
duke@435	1089
twisti@4412	1090	void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1091	void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1092
duke@435	1093	// p 226
duke@435	1094
duke@435	1095	inline void stb( Register d, Register s1, Register s2 );
duke@435	1096	inline void stb( Register d, Register s1, int simm13a);
duke@435	1097	inline void sth( Register d, Register s1, Register s2 );
duke@435	1098	inline void sth( Register d, Register s1, int simm13a);
duke@435	1099	inline void stw( Register d, Register s1, Register s2 );
duke@435	1100	inline void stw( Register d, Register s1, int simm13a);
duke@435	1101	inline void stx( Register d, Register s1, Register s2 );
duke@435	1102	inline void stx( Register d, Register s1, int simm13a);
duke@435	1103	inline void std( Register d, Register s1, Register s2 );
duke@435	1104	inline void std( Register d, Register s1, int simm13a);
duke@435	1105
duke@435	1106	// pp 177
duke@435	1107
twisti@4412	1108	void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1109	void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1110	void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1111	void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1112	void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1113	void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1114	void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1115	void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1116	void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1117	void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1118
duke@435	1119	// pp 97 (v8)
duke@435	1120
duke@435	1121	inline void stc( int crd, Register s1, Register s2 );
duke@435	1122	inline void stc( int crd, Register s1, int simm13a);
duke@435	1123	inline void stdc( int crd, Register s1, Register s2 );
duke@435	1124	inline void stdc( int crd, Register s1, int simm13a);
duke@435	1125	inline void stcsr( int crd, Register s1, Register s2 );
duke@435	1126	inline void stcsr( int crd, Register s1, int simm13a);
duke@435	1127	inline void stdcq( int crd, Register s1, Register s2 );
duke@435	1128	inline void stdcq( int crd, Register s1, int simm13a);
duke@435	1129
duke@435	1130	// pp 230
duke@435	1131
twisti@4412	1132	void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1133	void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@2350	1134
twisti@4412	1135	void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1136	void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1137	void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1138	void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1139	void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	1140	void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1141
duke@435	1142	// pp 231
duke@435	1143
duke@435	1144	inline void swap( Register s1, Register s2, Register d );
duke@435	1145	inline void swap( Register s1, int simm13a, Register d);
duke@435	1146
duke@435	1147	// pp 232
duke@435	1148
twisti@4412	1149	void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
twisti@4412	1150	void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1151
duke@435	1152	// pp 234, note op in book is wrong, see pp 268
duke@435	1153
twisti@4412	1154	void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1155	void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1156	void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	1157	void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1158
duke@435	1159	// pp 235
duke@435	1160
twisti@4412	1161	void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
twisti@4412	1162	void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
twisti@4412	1163	void tsubcctv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
twisti@4412	1164	void tsubcctv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
duke@435	1165
duke@435	1166	// pp 237
duke@435	1167
twisti@4412	1168	void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
twisti@4412	1169	void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
duke@435	1170	// simple uncond. trap
duke@435	1171	void trap( int trapa ) { trap( always, icc, G0, trapa ); }
duke@435	1172
duke@435	1173	// pp 239 omit write priv register for now
duke@435	1174
twisti@4412	1175	inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
twisti@4412	1176	inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
twisti@4412	1177	inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
duke@435	1178	rs1(s) |
duke@435	1179	op3(wrreg_op3) |
duke@435	1180	u_field(2, 29, 25) |
kvn@3092	1181	immed(true) |
duke@435	1182	simm(simm13a, 13)); }
twisti@4412	1183	inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
kvn@3092	1184	// wrasi(d, imm) stores (d xor imm) to asi
twisti@4412	1185	inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
kvn@3092	1186	u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
twisti@4412	1187	inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
duke@435	1188
kvn@3001	1189
kvn@3001	1190	// VIS3 instructions
kvn@3001	1191
twisti@4412	1192	void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
twisti@4412	1193	void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
twisti@4412	1194	void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
kvn@3001	1195
twisti@4412	1196	void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
twisti@4412	1197	void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
kvn@3001	1198
duke@435	1199	// Creation
duke@435	1200	Assembler(CodeBuffer* code) : AbstractAssembler(code) {
duke@435	1201	#ifdef CHECK_DELAY
duke@435	1202	delay_state = no_delay;
duke@435	1203	#endif
duke@435	1204	}
duke@435	1205	};
duke@435	1206
stefank@2314	1207	#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP