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duke@435 | 1 | /* |
duke@435 | 2 | * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | // We have interfaces for the following instructions: |
duke@435 | 26 | // - NativeInstruction |
duke@435 | 27 | // - - NativeCall |
duke@435 | 28 | // - - NativeMovConstReg |
duke@435 | 29 | // - - NativeMovConstRegPatching |
duke@435 | 30 | // - - NativeMovRegMem |
duke@435 | 31 | // - - NativeMovRegMemPatching |
duke@435 | 32 | // - - NativeJump |
duke@435 | 33 | // - - NativeIllegalOpCode |
duke@435 | 34 | // - - NativeGeneralJump |
duke@435 | 35 | // - - NativeReturn |
duke@435 | 36 | // - - NativeReturnX (return with argument) |
duke@435 | 37 | // - - NativePushConst |
duke@435 | 38 | // - - NativeTstRegMem |
duke@435 | 39 | |
duke@435 | 40 | // The base class for different kinds of native instruction abstractions. |
duke@435 | 41 | // Provides the primitive operations to manipulate code relative to this. |
duke@435 | 42 | |
duke@435 | 43 | class NativeInstruction VALUE_OBJ_CLASS_SPEC { |
duke@435 | 44 | friend class Relocation; |
duke@435 | 45 | |
duke@435 | 46 | public: |
duke@435 | 47 | enum Intel_specific_constants { |
duke@435 | 48 | nop_instruction_code = 0x90, |
duke@435 | 49 | nop_instruction_size = 1 |
duke@435 | 50 | }; |
duke@435 | 51 | |
duke@435 | 52 | bool is_nop() { return ubyte_at(0) == nop_instruction_code; } |
duke@435 | 53 | inline bool is_call(); |
duke@435 | 54 | inline bool is_illegal(); |
duke@435 | 55 | inline bool is_return(); |
duke@435 | 56 | inline bool is_jump(); |
duke@435 | 57 | inline bool is_cond_jump(); |
duke@435 | 58 | inline bool is_safepoint_poll(); |
duke@435 | 59 | inline bool is_mov_literal64(); |
duke@435 | 60 | |
duke@435 | 61 | protected: |
duke@435 | 62 | address addr_at(int offset) const { return address(this) + offset; } |
duke@435 | 63 | |
duke@435 | 64 | s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } |
duke@435 | 65 | u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } |
duke@435 | 66 | |
duke@435 | 67 | jint int_at(int offset) const { return *(jint*) addr_at(offset); } |
duke@435 | 68 | |
duke@435 | 69 | intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } |
duke@435 | 70 | |
duke@435 | 71 | oop oop_at (int offset) const { return *(oop*) addr_at(offset); } |
duke@435 | 72 | |
duke@435 | 73 | |
duke@435 | 74 | void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } |
duke@435 | 75 | void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); } |
duke@435 | 76 | void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } |
duke@435 | 77 | void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } |
duke@435 | 78 | |
duke@435 | 79 | // This doesn't really do anything on Intel, but it is the place where |
duke@435 | 80 | // cache invalidation belongs, generically: |
duke@435 | 81 | void wrote(int offset); |
duke@435 | 82 | |
duke@435 | 83 | public: |
duke@435 | 84 | |
duke@435 | 85 | // unit test stuff |
duke@435 | 86 | static void test() {} // override for testing |
duke@435 | 87 | |
duke@435 | 88 | inline friend NativeInstruction* nativeInstruction_at(address address); |
duke@435 | 89 | }; |
duke@435 | 90 | |
duke@435 | 91 | inline NativeInstruction* nativeInstruction_at(address address) { |
duke@435 | 92 | NativeInstruction* inst = (NativeInstruction*)address; |
duke@435 | 93 | #ifdef ASSERT |
duke@435 | 94 | //inst->verify(); |
duke@435 | 95 | #endif |
duke@435 | 96 | return inst; |
duke@435 | 97 | } |
duke@435 | 98 | |
duke@435 | 99 | inline NativeCall* nativeCall_at(address address); |
duke@435 | 100 | // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off |
duke@435 | 101 | // instructions (used to manipulate inline caches, primitive & dll calls, etc.). |
duke@435 | 102 | |
duke@435 | 103 | class NativeCall: public NativeInstruction { |
duke@435 | 104 | public: |
duke@435 | 105 | enum Intel_specific_constants { |
duke@435 | 106 | instruction_code = 0xE8, |
duke@435 | 107 | instruction_size = 5, |
duke@435 | 108 | instruction_offset = 0, |
duke@435 | 109 | displacement_offset = 1, |
duke@435 | 110 | return_address_offset = 5 |
duke@435 | 111 | }; |
duke@435 | 112 | |
duke@435 | 113 | enum { cache_line_size = BytesPerWord }; // conservative estimate! |
duke@435 | 114 | |
duke@435 | 115 | address instruction_address() const { return addr_at(instruction_offset); } |
duke@435 | 116 | address next_instruction_address() const { return addr_at(return_address_offset); } |
duke@435 | 117 | int displacement() const { return (jint) int_at(displacement_offset); } |
duke@435 | 118 | address displacement_address() const { return addr_at(displacement_offset); } |
duke@435 | 119 | address return_address() const { return addr_at(return_address_offset); } |
duke@435 | 120 | address destination() const; |
duke@435 | 121 | void set_destination(address dest) { |
duke@435 | 122 | #ifdef AMD64 |
duke@435 | 123 | assert((labs((intptr_t) dest - (intptr_t) return_address()) & |
duke@435 | 124 | 0xFFFFFFFF00000000) == 0, |
duke@435 | 125 | "must be 32bit offset"); |
duke@435 | 126 | #endif // AMD64 |
duke@435 | 127 | set_int_at(displacement_offset, dest - return_address()); |
duke@435 | 128 | } |
duke@435 | 129 | void set_destination_mt_safe(address dest); |
duke@435 | 130 | |
duke@435 | 131 | void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); } |
duke@435 | 132 | void verify(); |
duke@435 | 133 | void print(); |
duke@435 | 134 | |
duke@435 | 135 | // Creation |
duke@435 | 136 | inline friend NativeCall* nativeCall_at(address address); |
duke@435 | 137 | inline friend NativeCall* nativeCall_before(address return_address); |
duke@435 | 138 | |
duke@435 | 139 | static bool is_call_at(address instr) { |
duke@435 | 140 | return ((*instr) & 0xFF) == NativeCall::instruction_code; |
duke@435 | 141 | } |
duke@435 | 142 | |
duke@435 | 143 | static bool is_call_before(address return_address) { |
duke@435 | 144 | return is_call_at(return_address - NativeCall::return_address_offset); |
duke@435 | 145 | } |
duke@435 | 146 | |
duke@435 | 147 | static bool is_call_to(address instr, address target) { |
duke@435 | 148 | return nativeInstruction_at(instr)->is_call() && |
duke@435 | 149 | nativeCall_at(instr)->destination() == target; |
duke@435 | 150 | } |
duke@435 | 151 | |
duke@435 | 152 | // MT-safe patching of a call instruction. |
duke@435 | 153 | static void insert(address code_pos, address entry); |
duke@435 | 154 | |
duke@435 | 155 | static void replace_mt_safe(address instr_addr, address code_buffer); |
duke@435 | 156 | }; |
duke@435 | 157 | |
duke@435 | 158 | inline NativeCall* nativeCall_at(address address) { |
duke@435 | 159 | NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); |
duke@435 | 160 | #ifdef ASSERT |
duke@435 | 161 | call->verify(); |
duke@435 | 162 | #endif |
duke@435 | 163 | return call; |
duke@435 | 164 | } |
duke@435 | 165 | |
duke@435 | 166 | inline NativeCall* nativeCall_before(address return_address) { |
duke@435 | 167 | NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); |
duke@435 | 168 | #ifdef ASSERT |
duke@435 | 169 | call->verify(); |
duke@435 | 170 | #endif |
duke@435 | 171 | return call; |
duke@435 | 172 | } |
duke@435 | 173 | |
duke@435 | 174 | // An interface for accessing/manipulating native mov reg, imm32 instructions. |
duke@435 | 175 | // (used to manipulate inlined 32bit data dll calls, etc.) |
duke@435 | 176 | class NativeMovConstReg: public NativeInstruction { |
duke@435 | 177 | #ifdef AMD64 |
duke@435 | 178 | static const bool has_rex = true; |
duke@435 | 179 | static const int rex_size = 1; |
duke@435 | 180 | #else |
duke@435 | 181 | static const bool has_rex = false; |
duke@435 | 182 | static const int rex_size = 0; |
duke@435 | 183 | #endif // AMD64 |
duke@435 | 184 | public: |
duke@435 | 185 | enum Intel_specific_constants { |
duke@435 | 186 | instruction_code = 0xB8, |
duke@435 | 187 | instruction_size = 1 + rex_size + wordSize, |
duke@435 | 188 | instruction_offset = 0, |
duke@435 | 189 | data_offset = 1 + rex_size, |
duke@435 | 190 | next_instruction_offset = instruction_size, |
duke@435 | 191 | register_mask = 0x07 |
duke@435 | 192 | }; |
duke@435 | 193 | |
duke@435 | 194 | address instruction_address() const { return addr_at(instruction_offset); } |
duke@435 | 195 | address next_instruction_address() const { return addr_at(next_instruction_offset); } |
duke@435 | 196 | intptr_t data() const { return ptr_at(data_offset); } |
duke@435 | 197 | void set_data(intptr_t x) { set_ptr_at(data_offset, x); } |
duke@435 | 198 | |
duke@435 | 199 | void verify(); |
duke@435 | 200 | void print(); |
duke@435 | 201 | |
duke@435 | 202 | // unit test stuff |
duke@435 | 203 | static void test() {} |
duke@435 | 204 | |
duke@435 | 205 | // Creation |
duke@435 | 206 | inline friend NativeMovConstReg* nativeMovConstReg_at(address address); |
duke@435 | 207 | inline friend NativeMovConstReg* nativeMovConstReg_before(address address); |
duke@435 | 208 | }; |
duke@435 | 209 | |
duke@435 | 210 | inline NativeMovConstReg* nativeMovConstReg_at(address address) { |
duke@435 | 211 | NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); |
duke@435 | 212 | #ifdef ASSERT |
duke@435 | 213 | test->verify(); |
duke@435 | 214 | #endif |
duke@435 | 215 | return test; |
duke@435 | 216 | } |
duke@435 | 217 | |
duke@435 | 218 | inline NativeMovConstReg* nativeMovConstReg_before(address address) { |
duke@435 | 219 | NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); |
duke@435 | 220 | #ifdef ASSERT |
duke@435 | 221 | test->verify(); |
duke@435 | 222 | #endif |
duke@435 | 223 | return test; |
duke@435 | 224 | } |
duke@435 | 225 | |
duke@435 | 226 | class NativeMovConstRegPatching: public NativeMovConstReg { |
duke@435 | 227 | private: |
duke@435 | 228 | friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { |
duke@435 | 229 | NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); |
duke@435 | 230 | #ifdef ASSERT |
duke@435 | 231 | test->verify(); |
duke@435 | 232 | #endif |
duke@435 | 233 | return test; |
duke@435 | 234 | } |
duke@435 | 235 | }; |
duke@435 | 236 | |
duke@435 | 237 | #ifndef AMD64 |
duke@435 | 238 | |
duke@435 | 239 | // An interface for accessing/manipulating native moves of the form: |
duke@435 | 240 | // mov[b/w/l] [reg + offset], reg (instruction_code_reg2mem) |
duke@435 | 241 | // mov[b/w/l] reg, [reg+offset] (instruction_code_mem2reg |
duke@435 | 242 | // mov[s/z]x[w/b] [reg + offset], reg |
duke@435 | 243 | // fld_s [reg+offset] |
duke@435 | 244 | // fld_d [reg+offset] |
duke@435 | 245 | // fstp_s [reg + offset] |
duke@435 | 246 | // fstp_d [reg + offset] |
duke@435 | 247 | // |
duke@435 | 248 | // Warning: These routines must be able to handle any instruction sequences |
duke@435 | 249 | // that are generated as a result of the load/store byte,word,long |
duke@435 | 250 | // macros. For example: The load_unsigned_byte instruction generates |
duke@435 | 251 | // an xor reg,reg inst prior to generating the movb instruction. This |
duke@435 | 252 | // class must skip the xor instruction. |
duke@435 | 253 | |
duke@435 | 254 | class NativeMovRegMem: public NativeInstruction { |
duke@435 | 255 | public: |
duke@435 | 256 | enum Intel_specific_constants { |
duke@435 | 257 | instruction_code_xor = 0x33, |
duke@435 | 258 | instruction_extended_prefix = 0x0F, |
duke@435 | 259 | instruction_code_mem2reg_movzxb = 0xB6, |
duke@435 | 260 | instruction_code_mem2reg_movsxb = 0xBE, |
duke@435 | 261 | instruction_code_mem2reg_movzxw = 0xB7, |
duke@435 | 262 | instruction_code_mem2reg_movsxw = 0xBF, |
duke@435 | 263 | instruction_operandsize_prefix = 0x66, |
duke@435 | 264 | instruction_code_reg2meml = 0x89, |
duke@435 | 265 | instruction_code_mem2regl = 0x8b, |
duke@435 | 266 | instruction_code_reg2memb = 0x88, |
duke@435 | 267 | instruction_code_mem2regb = 0x8a, |
duke@435 | 268 | instruction_code_float_s = 0xd9, |
duke@435 | 269 | instruction_code_float_d = 0xdd, |
duke@435 | 270 | instruction_code_long_volatile = 0xdf, |
duke@435 | 271 | instruction_code_xmm_ss_prefix = 0xf3, |
duke@435 | 272 | instruction_code_xmm_sd_prefix = 0xf2, |
duke@435 | 273 | instruction_code_xmm_code = 0x0f, |
duke@435 | 274 | instruction_code_xmm_load = 0x10, |
duke@435 | 275 | instruction_code_xmm_store = 0x11, |
duke@435 | 276 | instruction_code_xmm_lpd = 0x12, |
duke@435 | 277 | |
duke@435 | 278 | instruction_size = 4, |
duke@435 | 279 | instruction_offset = 0, |
duke@435 | 280 | data_offset = 2, |
duke@435 | 281 | next_instruction_offset = 4 |
duke@435 | 282 | }; |
duke@435 | 283 | |
duke@435 | 284 | address instruction_address() const { |
duke@435 | 285 | if (*addr_at(instruction_offset) == instruction_operandsize_prefix && |
duke@435 | 286 | *addr_at(instruction_offset+1) != instruction_code_xmm_code) { |
duke@435 | 287 | return addr_at(instruction_offset+1); // Not SSE instructions |
duke@435 | 288 | } |
duke@435 | 289 | else if (*addr_at(instruction_offset) == instruction_extended_prefix) { |
duke@435 | 290 | return addr_at(instruction_offset+1); |
duke@435 | 291 | } |
duke@435 | 292 | else if (*addr_at(instruction_offset) == instruction_code_xor) { |
duke@435 | 293 | return addr_at(instruction_offset+2); |
duke@435 | 294 | } |
duke@435 | 295 | else return addr_at(instruction_offset); |
duke@435 | 296 | } |
duke@435 | 297 | |
duke@435 | 298 | address next_instruction_address() const { |
duke@435 | 299 | switch (*addr_at(instruction_offset)) { |
duke@435 | 300 | case instruction_operandsize_prefix: |
duke@435 | 301 | if (*addr_at(instruction_offset+1) == instruction_code_xmm_code) |
duke@435 | 302 | return instruction_address() + instruction_size; // SSE instructions |
duke@435 | 303 | case instruction_extended_prefix: |
duke@435 | 304 | return instruction_address() + instruction_size + 1; |
duke@435 | 305 | case instruction_code_reg2meml: |
duke@435 | 306 | case instruction_code_mem2regl: |
duke@435 | 307 | case instruction_code_reg2memb: |
duke@435 | 308 | case instruction_code_mem2regb: |
duke@435 | 309 | case instruction_code_xor: |
duke@435 | 310 | return instruction_address() + instruction_size + 2; |
duke@435 | 311 | default: |
duke@435 | 312 | return instruction_address() + instruction_size; |
duke@435 | 313 | } |
duke@435 | 314 | } |
duke@435 | 315 | int offset() const{ |
duke@435 | 316 | if (*addr_at(instruction_offset) == instruction_operandsize_prefix && |
duke@435 | 317 | *addr_at(instruction_offset+1) != instruction_code_xmm_code) { |
duke@435 | 318 | return int_at(data_offset+1); // Not SSE instructions |
duke@435 | 319 | } |
duke@435 | 320 | else if (*addr_at(instruction_offset) == instruction_extended_prefix) { |
duke@435 | 321 | return int_at(data_offset+1); |
duke@435 | 322 | } |
duke@435 | 323 | else if (*addr_at(instruction_offset) == instruction_code_xor || |
duke@435 | 324 | *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix || |
duke@435 | 325 | *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix || |
duke@435 | 326 | *addr_at(instruction_offset) == instruction_operandsize_prefix) { |
duke@435 | 327 | return int_at(data_offset+2); |
duke@435 | 328 | } |
duke@435 | 329 | else return int_at(data_offset); |
duke@435 | 330 | } |
duke@435 | 331 | |
duke@435 | 332 | void set_offset(int x) { |
duke@435 | 333 | if (*addr_at(instruction_offset) == instruction_operandsize_prefix && |
duke@435 | 334 | *addr_at(instruction_offset+1) != instruction_code_xmm_code) { |
duke@435 | 335 | set_int_at(data_offset+1, x); // Not SSE instructions |
duke@435 | 336 | } |
duke@435 | 337 | else if (*addr_at(instruction_offset) == instruction_extended_prefix) { |
duke@435 | 338 | set_int_at(data_offset+1, x); |
duke@435 | 339 | } |
duke@435 | 340 | else if (*addr_at(instruction_offset) == instruction_code_xor || |
duke@435 | 341 | *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix || |
duke@435 | 342 | *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix || |
duke@435 | 343 | *addr_at(instruction_offset) == instruction_operandsize_prefix) { |
duke@435 | 344 | set_int_at(data_offset+2, x); |
duke@435 | 345 | } |
duke@435 | 346 | else set_int_at(data_offset, x); |
duke@435 | 347 | } |
duke@435 | 348 | |
duke@435 | 349 | void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } |
duke@435 | 350 | void copy_instruction_to(address new_instruction_address); |
duke@435 | 351 | |
duke@435 | 352 | void verify(); |
duke@435 | 353 | void print (); |
duke@435 | 354 | |
duke@435 | 355 | // unit test stuff |
duke@435 | 356 | static void test() {} |
duke@435 | 357 | |
duke@435 | 358 | private: |
duke@435 | 359 | inline friend NativeMovRegMem* nativeMovRegMem_at (address address); |
duke@435 | 360 | }; |
duke@435 | 361 | |
duke@435 | 362 | inline NativeMovRegMem* nativeMovRegMem_at (address address) { |
duke@435 | 363 | NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); |
duke@435 | 364 | #ifdef ASSERT |
duke@435 | 365 | test->verify(); |
duke@435 | 366 | #endif |
duke@435 | 367 | return test; |
duke@435 | 368 | } |
duke@435 | 369 | |
duke@435 | 370 | class NativeMovRegMemPatching: public NativeMovRegMem { |
duke@435 | 371 | private: |
duke@435 | 372 | friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { |
duke@435 | 373 | NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset); |
duke@435 | 374 | #ifdef ASSERT |
duke@435 | 375 | test->verify(); |
duke@435 | 376 | #endif |
duke@435 | 377 | return test; |
duke@435 | 378 | } |
duke@435 | 379 | }; |
duke@435 | 380 | |
duke@435 | 381 | |
duke@435 | 382 | |
duke@435 | 383 | // An interface for accessing/manipulating native leal instruction of form: |
duke@435 | 384 | // leal reg, [reg + offset] |
duke@435 | 385 | |
duke@435 | 386 | class NativeLoadAddress: public NativeMovRegMem { |
duke@435 | 387 | public: |
duke@435 | 388 | enum Intel_specific_constants { |
duke@435 | 389 | instruction_code = 0x8D |
duke@435 | 390 | }; |
duke@435 | 391 | |
duke@435 | 392 | void verify(); |
duke@435 | 393 | void print (); |
duke@435 | 394 | |
duke@435 | 395 | // unit test stuff |
duke@435 | 396 | static void test() {} |
duke@435 | 397 | |
duke@435 | 398 | private: |
duke@435 | 399 | friend NativeLoadAddress* nativeLoadAddress_at (address address) { |
duke@435 | 400 | NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset); |
duke@435 | 401 | #ifdef ASSERT |
duke@435 | 402 | test->verify(); |
duke@435 | 403 | #endif |
duke@435 | 404 | return test; |
duke@435 | 405 | } |
duke@435 | 406 | }; |
duke@435 | 407 | |
duke@435 | 408 | #endif // AMD64 |
duke@435 | 409 | |
duke@435 | 410 | // jump rel32off |
duke@435 | 411 | |
duke@435 | 412 | class NativeJump: public NativeInstruction { |
duke@435 | 413 | public: |
duke@435 | 414 | enum Intel_specific_constants { |
duke@435 | 415 | instruction_code = 0xe9, |
duke@435 | 416 | instruction_size = 5, |
duke@435 | 417 | instruction_offset = 0, |
duke@435 | 418 | data_offset = 1, |
duke@435 | 419 | next_instruction_offset = 5 |
duke@435 | 420 | }; |
duke@435 | 421 | |
duke@435 | 422 | address instruction_address() const { return addr_at(instruction_offset); } |
duke@435 | 423 | address next_instruction_address() const { return addr_at(next_instruction_offset); } |
duke@435 | 424 | address jump_destination() const { |
duke@435 | 425 | address dest = (int_at(data_offset)+next_instruction_address()); |
duke@435 | 426 | #ifdef AMD64 // What is this about? |
duke@435 | 427 | // return -1 if jump to self |
duke@435 | 428 | dest = (dest == (address) this) ? (address) -1 : dest; |
duke@435 | 429 | #endif // AMD64 |
duke@435 | 430 | return dest; |
duke@435 | 431 | } |
duke@435 | 432 | |
duke@435 | 433 | void set_jump_destination(address dest) { |
duke@435 | 434 | intptr_t val = dest - next_instruction_address(); |
duke@435 | 435 | #ifdef AMD64 |
duke@435 | 436 | if (dest == (address) -1) { // can't encode jump to -1 |
duke@435 | 437 | val = -5; // jump to self |
duke@435 | 438 | } else { |
duke@435 | 439 | assert((labs(val) & 0xFFFFFFFF00000000) == 0, |
duke@435 | 440 | "must be 32bit offset"); |
duke@435 | 441 | } |
duke@435 | 442 | #endif // AMD64 |
duke@435 | 443 | set_int_at(data_offset, (jint)val); |
duke@435 | 444 | } |
duke@435 | 445 | |
duke@435 | 446 | // Creation |
duke@435 | 447 | inline friend NativeJump* nativeJump_at(address address); |
duke@435 | 448 | |
duke@435 | 449 | void verify(); |
duke@435 | 450 | |
duke@435 | 451 | // Unit testing stuff |
duke@435 | 452 | static void test() {} |
duke@435 | 453 | |
duke@435 | 454 | // Insertion of native jump instruction |
duke@435 | 455 | static void insert(address code_pos, address entry); |
duke@435 | 456 | // MT-safe insertion of native jump at verified method entry |
duke@435 | 457 | static void check_verified_entry_alignment(address entry, address verified_entry); |
duke@435 | 458 | static void patch_verified_entry(address entry, address verified_entry, address dest); |
duke@435 | 459 | }; |
duke@435 | 460 | |
duke@435 | 461 | inline NativeJump* nativeJump_at(address address) { |
duke@435 | 462 | NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); |
duke@435 | 463 | #ifdef ASSERT |
duke@435 | 464 | jump->verify(); |
duke@435 | 465 | #endif |
duke@435 | 466 | return jump; |
duke@435 | 467 | } |
duke@435 | 468 | |
duke@435 | 469 | // Handles all kinds of jump on Intel. Long/far, conditional/unconditional |
duke@435 | 470 | class NativeGeneralJump: public NativeInstruction { |
duke@435 | 471 | public: |
duke@435 | 472 | enum Intel_specific_constants { |
duke@435 | 473 | // Constants does not apply, since the lengths and offsets depends on the actual jump |
duke@435 | 474 | // used |
duke@435 | 475 | // Instruction codes: |
duke@435 | 476 | // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off) |
duke@435 | 477 | // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off) |
duke@435 | 478 | unconditional_long_jump = 0xe9, |
duke@435 | 479 | unconditional_short_jump = 0xeb, |
duke@435 | 480 | instruction_size = 5 |
duke@435 | 481 | }; |
duke@435 | 482 | |
duke@435 | 483 | address instruction_address() const { return addr_at(0); } |
duke@435 | 484 | address jump_destination() const; |
duke@435 | 485 | |
duke@435 | 486 | // Creation |
duke@435 | 487 | inline friend NativeGeneralJump* nativeGeneralJump_at(address address); |
duke@435 | 488 | |
duke@435 | 489 | // Insertion of native general jump instruction |
duke@435 | 490 | static void insert_unconditional(address code_pos, address entry); |
duke@435 | 491 | static void replace_mt_safe(address instr_addr, address code_buffer); |
duke@435 | 492 | |
duke@435 | 493 | void verify(); |
duke@435 | 494 | }; |
duke@435 | 495 | |
duke@435 | 496 | inline NativeGeneralJump* nativeGeneralJump_at(address address) { |
duke@435 | 497 | NativeGeneralJump* jump = (NativeGeneralJump*)(address); |
duke@435 | 498 | debug_only(jump->verify();) |
duke@435 | 499 | return jump; |
duke@435 | 500 | } |
duke@435 | 501 | |
duke@435 | 502 | class NativePopReg : public NativeInstruction { |
duke@435 | 503 | public: |
duke@435 | 504 | enum Intel_specific_constants { |
duke@435 | 505 | instruction_code = 0x58, |
duke@435 | 506 | instruction_size = 1, |
duke@435 | 507 | instruction_offset = 0, |
duke@435 | 508 | data_offset = 1, |
duke@435 | 509 | next_instruction_offset = 1 |
duke@435 | 510 | }; |
duke@435 | 511 | |
duke@435 | 512 | // Insert a pop instruction |
duke@435 | 513 | static void insert(address code_pos, Register reg); |
duke@435 | 514 | }; |
duke@435 | 515 | |
duke@435 | 516 | |
duke@435 | 517 | class NativeIllegalInstruction: public NativeInstruction { |
duke@435 | 518 | public: |
duke@435 | 519 | enum Intel_specific_constants { |
duke@435 | 520 | instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B |
duke@435 | 521 | instruction_size = 2, |
duke@435 | 522 | instruction_offset = 0, |
duke@435 | 523 | next_instruction_offset = 2 |
duke@435 | 524 | }; |
duke@435 | 525 | |
duke@435 | 526 | // Insert illegal opcode as specific address |
duke@435 | 527 | static void insert(address code_pos); |
duke@435 | 528 | }; |
duke@435 | 529 | |
duke@435 | 530 | // return instruction that does not pop values of the stack |
duke@435 | 531 | class NativeReturn: public NativeInstruction { |
duke@435 | 532 | public: |
duke@435 | 533 | enum Intel_specific_constants { |
duke@435 | 534 | instruction_code = 0xC3, |
duke@435 | 535 | instruction_size = 1, |
duke@435 | 536 | instruction_offset = 0, |
duke@435 | 537 | next_instruction_offset = 1 |
duke@435 | 538 | }; |
duke@435 | 539 | }; |
duke@435 | 540 | |
duke@435 | 541 | // return instruction that does pop values of the stack |
duke@435 | 542 | class NativeReturnX: public NativeInstruction { |
duke@435 | 543 | public: |
duke@435 | 544 | enum Intel_specific_constants { |
duke@435 | 545 | instruction_code = 0xC2, |
duke@435 | 546 | instruction_size = 2, |
duke@435 | 547 | instruction_offset = 0, |
duke@435 | 548 | next_instruction_offset = 2 |
duke@435 | 549 | }; |
duke@435 | 550 | }; |
duke@435 | 551 | |
duke@435 | 552 | // Simple test vs memory |
duke@435 | 553 | class NativeTstRegMem: public NativeInstruction { |
duke@435 | 554 | public: |
duke@435 | 555 | enum Intel_specific_constants { |
duke@435 | 556 | instruction_code_memXregl = 0x85 |
duke@435 | 557 | }; |
duke@435 | 558 | }; |
duke@435 | 559 | |
duke@435 | 560 | inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } |
duke@435 | 561 | inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } |
duke@435 | 562 | inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || |
duke@435 | 563 | ubyte_at(0) == NativeReturnX::instruction_code; } |
duke@435 | 564 | inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || |
duke@435 | 565 | ubyte_at(0) == 0xEB; /* short jump */ } |
duke@435 | 566 | inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || |
duke@435 | 567 | (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ } |
duke@435 | 568 | inline bool NativeInstruction::is_safepoint_poll() { |
duke@435 | 569 | #ifdef AMD64 |
duke@435 | 570 | return ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && |
duke@435 | 571 | ubyte_at(1) == 0x05 && // 00 rax 101 |
duke@435 | 572 | ((intptr_t) addr_at(6)) + int_at(2) == (intptr_t) os::get_polling_page(); |
duke@435 | 573 | #else |
duke@435 | 574 | return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2regl || |
duke@435 | 575 | ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) && |
duke@435 | 576 | (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */ |
duke@435 | 577 | (os::is_poll_address((address)int_at(2))); |
duke@435 | 578 | #endif // AMD64 |
duke@435 | 579 | } |
duke@435 | 580 | |
duke@435 | 581 | inline bool NativeInstruction::is_mov_literal64() { |
duke@435 | 582 | #ifdef AMD64 |
duke@435 | 583 | return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) && |
duke@435 | 584 | (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8); |
duke@435 | 585 | #else |
duke@435 | 586 | return false; |
duke@435 | 587 | #endif // AMD64 |
duke@435 | 588 | } |