Thu, 29 Dec 2016 13:40:20 +0800
#4814 [C2] initial 64-bit vector support
Float registers are used as 64-bit vector registers. loading/storing 64-bit vector and add.ps/sub.ps/mul.ps are added.
aoqi@1 | 1 | /* |
aoqi@1 | 2 | * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@1 | 5 | * |
aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@1 | 8 | * published by the Free Software Foundation. |
aoqi@1 | 9 | * |
aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@1 | 14 | * accompanied this code). |
aoqi@1 | 15 | * |
aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@1 | 19 | * |
aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
aoqi@1 | 22 | * questions. |
aoqi@1 | 23 | * |
aoqi@1 | 24 | */ |
aoqi@1 | 25 | |
aoqi@1 | 26 | #ifndef CPU_MIPS_VM_VM_VERSION_MIPS_HPP |
aoqi@1 | 27 | #define CPU_MIPS_VM_VM_VERSION_MIPS_HPP |
aoqi@1 | 28 | |
aoqi@1 | 29 | #include "runtime/globals_extension.hpp" |
aoqi@1 | 30 | #include "runtime/vm_version.hpp" |
aoqi@1 | 31 | |
aoqi@1 | 32 | |
aoqi@1 | 33 | class VM_Version: public Abstract_VM_Version { |
aoqi@1 | 34 | protected: |
aoqi@1 | 35 | enum Feature_Flag { |
aoqi@1 | 36 | with_l2_cache = 0, |
aoqi@1 | 37 | spt_16k_page = 1, |
aoqi@1 | 38 | //////////////////////add some other feature here////////////////// |
aoqi@1 | 39 | }; |
aoqi@1 | 40 | |
aoqi@1 | 41 | enum Feature_Flag_Set { |
aoqi@1 | 42 | unknown_m = 0, |
aoqi@1 | 43 | all_features_m = -1, |
aoqi@1 | 44 | with_l2_cache_m = 1 << with_l2_cache, |
aoqi@1 | 45 | spt_16k_page_m = 1 << spt_16k_page, |
aoqi@1 | 46 | |
aoqi@1 | 47 | //////////////////////add some other feature here////////////////// |
aoqi@1 | 48 | }; |
aoqi@1 | 49 | |
aoqi@1 | 50 | static int _features; |
aoqi@1 | 51 | static const char* _features_str; |
aoqi@1 | 52 | |
aoqi@1 | 53 | static void print_features(); |
aoqi@1 | 54 | static int determine_features(); |
aoqi@1 | 55 | |
aoqi@1 | 56 | public: |
aoqi@1 | 57 | // Initialization |
aoqi@1 | 58 | static void initialize(); |
aoqi@1 | 59 | |
aoqi@1 | 60 | //mips has no such instructions, use ll/sc instead |
aoqi@1 | 61 | static bool supports_compare_and_exchange() { return false; } |
aoqi@1 | 62 | |
aoqi@1 | 63 | static bool has_l2_cache() { return _features & with_l2_cache_m; } |
aoqi@1 | 64 | static bool has_16k_page() { return _features & spt_16k_page_m; } |
aoqi@209 | 65 | static bool supports_ps() { return 1; /*Loongson CPUs support ps instructions*/} |
aoqi@209 | 66 | static bool supports_3d() { return 0; /*Loongson CPUs do not support 3d instructions*/} |
aoqi@1 | 67 | |
aoqi@1 | 68 | //////////////////////add some other feature here////////////////// |
aoqi@1 | 69 | |
aoqi@1 | 70 | static const char* cpu_features() { return _features_str; } |
aoqi@1 | 71 | |
aoqi@1 | 72 | // Assembler testing |
aoqi@1 | 73 | static void allow_all(); |
aoqi@1 | 74 | static void revert(); |
aoqi@1 | 75 | }; |
aoqi@1 | 76 | |
aoqi@1 | 77 | #endif // CPU_MIPS_VM_VM_VERSION_MIPS_HPP |