• file
• revisions
• annotate
• diff
• comparison
• raw

src/os_cpu/solaris_x86/vm/solaris_x86_32.ad@95134e034042 (annotated)

src/os_cpu/solaris_x86/vm/solaris_x86_32.ad

Thu, 11 Aug 2011 12:08:11 -0700

author

kvn

date

Thu, 11 Aug 2011 12:08:11 -0700

changeset 3049

95134e034042

parent 1907

c18cbe5936b8

child 3577

9b8ce46870df

permissions

-rw-r--r--

7063629: use cbcond in C2 generated code on T4
Summary: Use new short branch instruction in C2 generated code.
Reviewed-by: never

duke@435	1	//
trims@1907	2	// Copyright (c) 1999, 2008, Oracle and/or its affiliates. All rights reserved.
duke@435	3	// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435	4	//
duke@435	5	// This code is free software; you can redistribute it and/or modify it
duke@435	6	// under the terms of the GNU General Public License version 2 only, as
duke@435	7	// published by the Free Software Foundation.
duke@435	8	//
duke@435	9	// This code is distributed in the hope that it will be useful, but WITHOUT
duke@435	10	// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435	11	// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435	12	// version 2 for more details (a copy is included in the LICENSE file that
duke@435	13	// accompanied this code).
duke@435	14	//
duke@435	15	// You should have received a copy of the GNU General Public License version
duke@435	16	// 2 along with this work; if not, write to the Free Software Foundation,
duke@435	17	// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435	18	//
trims@1907	19	// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907	20	// or visit www.oracle.com if you need additional information or have any
trims@1907	21	// questions.
duke@435	22	//
duke@435	23	//
duke@435	24
duke@435	25	// X86 Solaris Architecture Description File
duke@435	26
duke@435	27	//----------OS-DEPENDENT ENCODING BLOCK-----------------------------------------------------
duke@435	28	// This block specifies the encoding classes used by the compiler to output
duke@435	29	// byte streams. Encoding classes generate functions which are called by
duke@435	30	// Machine Instruction Nodes in order to generate the bit encoding of the
duke@435	31	// instruction. Operands specify their base encoding interface with the
duke@435	32	// interface keyword. There are currently supported four interfaces,
duke@435	33	// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
duke@435	34	// operand to generate a function which returns its register number when
duke@435	35	// queried. CONST_INTER causes an operand to generate a function which
duke@435	36	// returns the value of the constant when queried. MEMORY_INTER causes an
duke@435	37	// operand to generate four functions which return the Base Register, the
duke@435	38	// Index Register, the Scale Value, and the Offset Value of the operand when
duke@435	39	// queried. COND_INTER causes an operand to generate six functions which
duke@435	40	// return the encoding code (ie - encoding bits for the instruction)
duke@435	41	// associated with each basic boolean condition for a conditional instruction.
duke@435	42	// Instructions specify two basic values for encoding. They use the
duke@435	43	// ins_encode keyword to specify their encoding class (which must be one of
duke@435	44	// the class names specified in the encoding block), and they use the
duke@435	45	// opcode keyword to specify, in order, their primary, secondary, and
duke@435	46	// tertiary opcode. Only the opcode sections which a particular instruction
duke@435	47	// needs for encoding need to be specified.
duke@435	48	encode %{
duke@435	49	// Build emit functions for each basic byte or larger field in the intel
duke@435	50	// encoding scheme (opcode, rm, sib, immediate), and call them from C++
duke@435	51	// code in the enc_class source block. Emit functions will live in the
duke@435	52	// main source block for now. In future, we can generalize this by
duke@435	53	// adding a syntax that specifies the sizes of fields in an order,
duke@435	54	// so that the adlc can build the emit functions automagically
duke@435	55
duke@435	56	enc_class solaris_tlsencode (eRegP dst) %{
duke@435	57	Register dstReg = as_Register($dst$$reg);
duke@435	58	MacroAssembler* masm = new MacroAssembler(&cbuf);
duke@435	59	masm->get_thread(dstReg);
duke@435	60	%}
duke@435	61
duke@435	62	enc_class solaris_breakpoint %{
duke@435	63	MacroAssembler* masm = new MacroAssembler(&cbuf);
duke@435	64	// Really need to fix this
never@739	65	masm->push(rax);
never@739	66	masm->push(rcx);
never@739	67	masm->push(rdx);
duke@435	68	masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
never@739	69	masm->pop(rdx);
never@739	70	masm->pop(rcx);
never@739	71	masm->pop(rax);
duke@435	72	%}
duke@435	73
duke@435	74	enc_class call_epilog %{
duke@435	75	if( VerifyStackAtCalls ) {
duke@435	76	// Check that stack depth is unchanged: find majik cookie on stack
duke@435	77	int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word));
duke@435	78	if(framesize >= 128) {
duke@435	79	emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
duke@435	80	emit_d8(cbuf,0xBC);
duke@435	81	emit_d8(cbuf,0x24);
duke@435	82	emit_d32(cbuf,framesize); // Find majik cookie from ESP
duke@435	83	emit_d32(cbuf, 0xbadb100d);
duke@435	84	}
duke@435	85	else {
duke@435	86	emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
duke@435	87	emit_d8(cbuf,0x7C);
duke@435	88	emit_d8(cbuf,0x24);
duke@435	89	emit_d8(cbuf,framesize); // Find majik cookie from ESP
duke@435	90	emit_d32(cbuf, 0xbadb100d);
duke@435	91	}
duke@435	92	// jmp EQ around INT3
duke@435	93	// QQQ TODO
duke@435	94	const int jump_around = 11; // size of call to breakpoint (and register preserve), 1 for CC
duke@435	95	emit_opcode(cbuf,0x74);
duke@435	96	emit_d8(cbuf, jump_around);
duke@435	97	// QQQ temporary
duke@435	98	emit_break(cbuf);
duke@435	99	// Die if stack mismatch
duke@435	100	// emit_opcode(cbuf,0xCC);
duke@435	101	}
duke@435	102	%}
duke@435	103
duke@435	104	%}
duke@435	105
duke@435	106	// INSTRUCTIONS -- Platform dependent
duke@435	107
duke@435	108	//----------OS and Locking Instructions----------------------------------------
duke@435	109
duke@435	110	// This name is KNOWN by the ADLC and cannot be changed.
duke@435	111	// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
duke@435	112	// for this guy.
kvn@855	113	instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
duke@435	114	match(Set dst (ThreadLocal));
duke@435	115	effect(DEF dst, KILL cr);
duke@435	116
kvn@855	117	format %{ "MOV $dst, Thread::current()" %}
duke@435	118	ins_encode( solaris_tlsencode(dst) );
duke@435	119	ins_pipe( ialu_reg_fat );
duke@435	120	%}
duke@435	121
kvn@855	122	instruct TLS(eRegP dst) %{
duke@435	123	match(Set dst (ThreadLocal));
duke@435	124
duke@435	125	expand %{
duke@435	126	tlsLoadP(dst);
duke@435	127	%}
duke@435	128	%}
duke@435	129
duke@435	130	// Die now
duke@435	131	instruct ShouldNotReachHere( )
duke@435	132	%{
duke@435	133	match(Halt);
duke@435	134
duke@435	135	// Use the following format syntax
duke@435	136	format %{ "INT3 ; ShouldNotReachHere" %}
duke@435	137	// QQQ TODO for now call breakpoint
duke@435	138	// opcode(0xCC);
duke@435	139	// ins_encode(Opc);
duke@435	140	ins_encode(solaris_breakpoint);
duke@435	141	ins_pipe( pipe_slow );
duke@435	142	%}
duke@435	143
duke@435	144
duke@435	145
duke@435	146	// Platform dependent source
duke@435	147
duke@435	148	source %{
duke@435	149
duke@435	150	// emit an interrupt that is caught by the debugger
duke@435	151	void emit_break(CodeBuffer &cbuf) {
duke@435	152
duke@435	153	// Debugger doesn't really catch this but best we can do so far QQQ
duke@435	154	MacroAssembler* masm = new MacroAssembler(&cbuf);
duke@435	155	masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
duke@435	156	}
duke@435	157
duke@435	158	void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@435	159	emit_break(cbuf);
duke@435	160	}
duke@435	161
duke@435	162
duke@435	163	uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
kvn@3049	164	return MachNode::size(ra_);
duke@435	165	}
duke@435	166
duke@435	167	%}