Fri, 11 Oct 2013 10:14:02 -0700
8005173: assert(false) failed: DEBUG MESSAGE: exception oop must be empty (macroAssembler_x86.cpp:625)
Reviewed-by: kvn, iveresov
duke@435 | 1 | /* |
never@3500 | 2 | * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
trims@1907 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
trims@1907 | 20 | * or visit www.oracle.com if you need additional information or have any |
trims@1907 | 21 | * questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
stefank@2314 | 25 | #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |
stefank@2314 | 26 | #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |
stefank@2314 | 27 | |
twisti@4323 | 28 | #include "asm/register.hpp" |
duke@435 | 29 | |
duke@435 | 30 | // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction |
duke@435 | 31 | // level; i.e., what you write |
duke@435 | 32 | // is what you get. The Assembler is generating code into a CodeBuffer. |
duke@435 | 33 | |
duke@435 | 34 | class Assembler : public AbstractAssembler { |
duke@435 | 35 | friend class AbstractAssembler; |
twisti@1162 | 36 | friend class AddressLiteral; |
duke@435 | 37 | |
duke@435 | 38 | // code patchers need various routines like inv_wdisp() |
duke@435 | 39 | friend class NativeInstruction; |
duke@435 | 40 | friend class NativeGeneralJump; |
duke@435 | 41 | friend class Relocation; |
duke@435 | 42 | friend class Label; |
duke@435 | 43 | |
duke@435 | 44 | public: |
duke@435 | 45 | // op carries format info; see page 62 & 267 |
duke@435 | 46 | |
duke@435 | 47 | enum ops { |
duke@435 | 48 | call_op = 1, // fmt 1 |
duke@435 | 49 | branch_op = 0, // also sethi (fmt2) |
duke@435 | 50 | arith_op = 2, // fmt 3, arith & misc |
duke@435 | 51 | ldst_op = 3 // fmt 3, load/store |
duke@435 | 52 | }; |
duke@435 | 53 | |
duke@435 | 54 | enum op2s { |
duke@435 | 55 | bpr_op2 = 3, |
duke@435 | 56 | fb_op2 = 6, |
duke@435 | 57 | fbp_op2 = 5, |
duke@435 | 58 | br_op2 = 2, |
duke@435 | 59 | bp_op2 = 1, |
duke@435 | 60 | sethi_op2 = 4 |
duke@435 | 61 | }; |
duke@435 | 62 | |
duke@435 | 63 | enum op3s { |
duke@435 | 64 | // selected op3s |
duke@435 | 65 | add_op3 = 0x00, |
duke@435 | 66 | and_op3 = 0x01, |
duke@435 | 67 | or_op3 = 0x02, |
duke@435 | 68 | xor_op3 = 0x03, |
duke@435 | 69 | sub_op3 = 0x04, |
duke@435 | 70 | andn_op3 = 0x05, |
duke@435 | 71 | orn_op3 = 0x06, |
duke@435 | 72 | xnor_op3 = 0x07, |
duke@435 | 73 | addc_op3 = 0x08, |
duke@435 | 74 | mulx_op3 = 0x09, |
duke@435 | 75 | umul_op3 = 0x0a, |
duke@435 | 76 | smul_op3 = 0x0b, |
duke@435 | 77 | subc_op3 = 0x0c, |
duke@435 | 78 | udivx_op3 = 0x0d, |
duke@435 | 79 | udiv_op3 = 0x0e, |
duke@435 | 80 | sdiv_op3 = 0x0f, |
duke@435 | 81 | |
duke@435 | 82 | addcc_op3 = 0x10, |
duke@435 | 83 | andcc_op3 = 0x11, |
duke@435 | 84 | orcc_op3 = 0x12, |
duke@435 | 85 | xorcc_op3 = 0x13, |
duke@435 | 86 | subcc_op3 = 0x14, |
duke@435 | 87 | andncc_op3 = 0x15, |
duke@435 | 88 | orncc_op3 = 0x16, |
duke@435 | 89 | xnorcc_op3 = 0x17, |
duke@435 | 90 | addccc_op3 = 0x18, |
duke@435 | 91 | umulcc_op3 = 0x1a, |
duke@435 | 92 | smulcc_op3 = 0x1b, |
duke@435 | 93 | subccc_op3 = 0x1c, |
duke@435 | 94 | udivcc_op3 = 0x1e, |
duke@435 | 95 | sdivcc_op3 = 0x1f, |
duke@435 | 96 | |
duke@435 | 97 | taddcc_op3 = 0x20, |
duke@435 | 98 | tsubcc_op3 = 0x21, |
duke@435 | 99 | taddcctv_op3 = 0x22, |
duke@435 | 100 | tsubcctv_op3 = 0x23, |
duke@435 | 101 | mulscc_op3 = 0x24, |
duke@435 | 102 | sll_op3 = 0x25, |
duke@435 | 103 | sllx_op3 = 0x25, |
duke@435 | 104 | srl_op3 = 0x26, |
duke@435 | 105 | srlx_op3 = 0x26, |
duke@435 | 106 | sra_op3 = 0x27, |
duke@435 | 107 | srax_op3 = 0x27, |
duke@435 | 108 | rdreg_op3 = 0x28, |
duke@435 | 109 | membar_op3 = 0x28, |
duke@435 | 110 | |
duke@435 | 111 | flushw_op3 = 0x2b, |
duke@435 | 112 | movcc_op3 = 0x2c, |
duke@435 | 113 | sdivx_op3 = 0x2d, |
duke@435 | 114 | popc_op3 = 0x2e, |
duke@435 | 115 | movr_op3 = 0x2f, |
duke@435 | 116 | |
duke@435 | 117 | sir_op3 = 0x30, |
duke@435 | 118 | wrreg_op3 = 0x30, |
duke@435 | 119 | saved_op3 = 0x31, |
duke@435 | 120 | |
duke@435 | 121 | fpop1_op3 = 0x34, |
duke@435 | 122 | fpop2_op3 = 0x35, |
duke@435 | 123 | impdep1_op3 = 0x36, |
duke@435 | 124 | impdep2_op3 = 0x37, |
duke@435 | 125 | jmpl_op3 = 0x38, |
duke@435 | 126 | rett_op3 = 0x39, |
duke@435 | 127 | trap_op3 = 0x3a, |
duke@435 | 128 | flush_op3 = 0x3b, |
duke@435 | 129 | save_op3 = 0x3c, |
duke@435 | 130 | restore_op3 = 0x3d, |
duke@435 | 131 | done_op3 = 0x3e, |
duke@435 | 132 | retry_op3 = 0x3e, |
duke@435 | 133 | |
duke@435 | 134 | lduw_op3 = 0x00, |
duke@435 | 135 | ldub_op3 = 0x01, |
duke@435 | 136 | lduh_op3 = 0x02, |
duke@435 | 137 | ldd_op3 = 0x03, |
duke@435 | 138 | stw_op3 = 0x04, |
duke@435 | 139 | stb_op3 = 0x05, |
duke@435 | 140 | sth_op3 = 0x06, |
duke@435 | 141 | std_op3 = 0x07, |
duke@435 | 142 | ldsw_op3 = 0x08, |
duke@435 | 143 | ldsb_op3 = 0x09, |
duke@435 | 144 | ldsh_op3 = 0x0a, |
duke@435 | 145 | ldx_op3 = 0x0b, |
duke@435 | 146 | |
duke@435 | 147 | stx_op3 = 0x0e, |
duke@435 | 148 | swap_op3 = 0x0f, |
duke@435 | 149 | |
duke@435 | 150 | stwa_op3 = 0x14, |
duke@435 | 151 | stxa_op3 = 0x1e, |
duke@435 | 152 | |
duke@435 | 153 | ldf_op3 = 0x20, |
duke@435 | 154 | ldfsr_op3 = 0x21, |
duke@435 | 155 | ldqf_op3 = 0x22, |
duke@435 | 156 | lddf_op3 = 0x23, |
duke@435 | 157 | stf_op3 = 0x24, |
duke@435 | 158 | stfsr_op3 = 0x25, |
duke@435 | 159 | stqf_op3 = 0x26, |
duke@435 | 160 | stdf_op3 = 0x27, |
duke@435 | 161 | |
duke@435 | 162 | prefetch_op3 = 0x2d, |
duke@435 | 163 | |
duke@435 | 164 | casa_op3 = 0x3c, |
duke@435 | 165 | casxa_op3 = 0x3e, |
duke@435 | 166 | |
kvn@3001 | 167 | mftoi_op3 = 0x36, |
kvn@3001 | 168 | |
duke@435 | 169 | alt_bit_op3 = 0x10, |
duke@435 | 170 | cc_bit_op3 = 0x10 |
duke@435 | 171 | }; |
duke@435 | 172 | |
duke@435 | 173 | enum opfs { |
duke@435 | 174 | // selected opfs |
duke@435 | 175 | fmovs_opf = 0x01, |
duke@435 | 176 | fmovd_opf = 0x02, |
duke@435 | 177 | |
duke@435 | 178 | fnegs_opf = 0x05, |
duke@435 | 179 | fnegd_opf = 0x06, |
duke@435 | 180 | |
duke@435 | 181 | fadds_opf = 0x41, |
duke@435 | 182 | faddd_opf = 0x42, |
duke@435 | 183 | fsubs_opf = 0x45, |
duke@435 | 184 | fsubd_opf = 0x46, |
duke@435 | 185 | |
duke@435 | 186 | fmuls_opf = 0x49, |
duke@435 | 187 | fmuld_opf = 0x4a, |
duke@435 | 188 | fdivs_opf = 0x4d, |
duke@435 | 189 | fdivd_opf = 0x4e, |
duke@435 | 190 | |
duke@435 | 191 | fcmps_opf = 0x51, |
duke@435 | 192 | fcmpd_opf = 0x52, |
duke@435 | 193 | |
duke@435 | 194 | fstox_opf = 0x81, |
duke@435 | 195 | fdtox_opf = 0x82, |
duke@435 | 196 | fxtos_opf = 0x84, |
duke@435 | 197 | fxtod_opf = 0x88, |
duke@435 | 198 | fitos_opf = 0xc4, |
duke@435 | 199 | fdtos_opf = 0xc6, |
duke@435 | 200 | fitod_opf = 0xc8, |
duke@435 | 201 | fstod_opf = 0xc9, |
duke@435 | 202 | fstoi_opf = 0xd1, |
kvn@3001 | 203 | fdtoi_opf = 0xd2, |
kvn@3001 | 204 | |
kvn@3001 | 205 | mdtox_opf = 0x110, |
kvn@3001 | 206 | mstouw_opf = 0x111, |
kvn@3001 | 207 | mstosw_opf = 0x113, |
kvn@3001 | 208 | mxtod_opf = 0x118, |
kvn@3001 | 209 | mwtos_opf = 0x119 |
duke@435 | 210 | }; |
duke@435 | 211 | |
kvn@3037 | 212 | enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez }; |
duke@435 | 213 | |
duke@435 | 214 | enum Condition { |
duke@435 | 215 | // for FBfcc & FBPfcc instruction |
duke@435 | 216 | f_never = 0, |
duke@435 | 217 | f_notEqual = 1, |
duke@435 | 218 | f_notZero = 1, |
duke@435 | 219 | f_lessOrGreater = 2, |
duke@435 | 220 | f_unorderedOrLess = 3, |
duke@435 | 221 | f_less = 4, |
duke@435 | 222 | f_unorderedOrGreater = 5, |
duke@435 | 223 | f_greater = 6, |
duke@435 | 224 | f_unordered = 7, |
duke@435 | 225 | f_always = 8, |
duke@435 | 226 | f_equal = 9, |
duke@435 | 227 | f_zero = 9, |
duke@435 | 228 | f_unorderedOrEqual = 10, |
duke@435 | 229 | f_greaterOrEqual = 11, |
duke@435 | 230 | f_unorderedOrGreaterOrEqual = 12, |
duke@435 | 231 | f_lessOrEqual = 13, |
duke@435 | 232 | f_unorderedOrLessOrEqual = 14, |
duke@435 | 233 | f_ordered = 15, |
duke@435 | 234 | |
duke@435 | 235 | // V8 coproc, pp 123 v8 manual |
duke@435 | 236 | |
duke@435 | 237 | cp_always = 8, |
duke@435 | 238 | cp_never = 0, |
duke@435 | 239 | cp_3 = 7, |
duke@435 | 240 | cp_2 = 6, |
duke@435 | 241 | cp_2or3 = 5, |
duke@435 | 242 | cp_1 = 4, |
duke@435 | 243 | cp_1or3 = 3, |
duke@435 | 244 | cp_1or2 = 2, |
duke@435 | 245 | cp_1or2or3 = 1, |
duke@435 | 246 | cp_0 = 9, |
duke@435 | 247 | cp_0or3 = 10, |
duke@435 | 248 | cp_0or2 = 11, |
duke@435 | 249 | cp_0or2or3 = 12, |
duke@435 | 250 | cp_0or1 = 13, |
duke@435 | 251 | cp_0or1or3 = 14, |
duke@435 | 252 | cp_0or1or2 = 15, |
duke@435 | 253 | |
duke@435 | 254 | |
duke@435 | 255 | // for integers |
duke@435 | 256 | |
duke@435 | 257 | never = 0, |
duke@435 | 258 | equal = 1, |
duke@435 | 259 | zero = 1, |
duke@435 | 260 | lessEqual = 2, |
duke@435 | 261 | less = 3, |
duke@435 | 262 | lessEqualUnsigned = 4, |
duke@435 | 263 | lessUnsigned = 5, |
duke@435 | 264 | carrySet = 5, |
duke@435 | 265 | negative = 6, |
duke@435 | 266 | overflowSet = 7, |
duke@435 | 267 | always = 8, |
duke@435 | 268 | notEqual = 9, |
duke@435 | 269 | notZero = 9, |
duke@435 | 270 | greater = 10, |
duke@435 | 271 | greaterEqual = 11, |
duke@435 | 272 | greaterUnsigned = 12, |
duke@435 | 273 | greaterEqualUnsigned = 13, |
duke@435 | 274 | carryClear = 13, |
duke@435 | 275 | positive = 14, |
duke@435 | 276 | overflowClear = 15 |
duke@435 | 277 | }; |
duke@435 | 278 | |
duke@435 | 279 | enum CC { |
duke@435 | 280 | icc = 0, xcc = 2, |
duke@435 | 281 | // ptr_cc is the correct condition code for a pointer or intptr_t: |
duke@435 | 282 | ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), |
duke@435 | 283 | fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 |
duke@435 | 284 | }; |
duke@435 | 285 | |
duke@435 | 286 | enum PrefetchFcn { |
duke@435 | 287 | severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 |
duke@435 | 288 | }; |
duke@435 | 289 | |
duke@435 | 290 | public: |
duke@435 | 291 | // Helper functions for groups of instructions |
duke@435 | 292 | |
duke@435 | 293 | enum Predict { pt = 1, pn = 0 }; // pt = predict taken |
duke@435 | 294 | |
duke@435 | 295 | enum Membar_mask_bits { // page 184, v9 |
duke@435 | 296 | StoreStore = 1 << 3, |
duke@435 | 297 | LoadStore = 1 << 2, |
duke@435 | 298 | StoreLoad = 1 << 1, |
duke@435 | 299 | LoadLoad = 1 << 0, |
duke@435 | 300 | |
duke@435 | 301 | Sync = 1 << 6, |
duke@435 | 302 | MemIssue = 1 << 5, |
duke@435 | 303 | Lookaside = 1 << 4 |
duke@435 | 304 | }; |
duke@435 | 305 | |
iveresov@2441 | 306 | static bool is_in_wdisp_range(address a, address b, int nbits) { |
iveresov@2441 | 307 | intptr_t d = intptr_t(b) - intptr_t(a); |
iveresov@2441 | 308 | return is_simm(d, nbits + 2); |
iveresov@2441 | 309 | } |
duke@435 | 310 | |
kvn@3037 | 311 | address target_distance(Label& L) { |
kvn@3037 | 312 | // Assembler::target(L) should be called only when |
kvn@3037 | 313 | // a branch instruction is emitted since non-bound |
kvn@3037 | 314 | // labels record current pc() as a branch address. |
kvn@3037 | 315 | if (L.is_bound()) return target(L); |
kvn@3037 | 316 | // Return current address for non-bound labels. |
kvn@3037 | 317 | return pc(); |
kvn@3037 | 318 | } |
kvn@3037 | 319 | |
iveresov@2203 | 320 | // test if label is in simm16 range in words (wdisp16). |
iveresov@2203 | 321 | bool is_in_wdisp16_range(Label& L) { |
kvn@3037 | 322 | return is_in_wdisp_range(target_distance(L), pc(), 16); |
iveresov@2441 | 323 | } |
iveresov@2441 | 324 | // test if the distance between two addresses fits in simm30 range in words |
iveresov@2441 | 325 | static bool is_in_wdisp30_range(address a, address b) { |
iveresov@2441 | 326 | return is_in_wdisp_range(a, b, 30); |
iveresov@2203 | 327 | } |
iveresov@2203 | 328 | |
duke@435 | 329 | enum ASIs { // page 72, v9 |
kvn@3092 | 330 | ASI_PRIMARY = 0x80, |
kvn@3092 | 331 | ASI_PRIMARY_NOFAULT = 0x82, |
kvn@3092 | 332 | ASI_PRIMARY_LITTLE = 0x88, |
kvn@3052 | 333 | // Block initializing store |
kvn@3052 | 334 | ASI_ST_BLKINIT_PRIMARY = 0xE2, |
kvn@3052 | 335 | // Most-Recently-Used (MRU) BIS variant |
kvn@3052 | 336 | ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2 |
duke@435 | 337 | // add more from book as needed |
duke@435 | 338 | }; |
duke@435 | 339 | |
duke@435 | 340 | protected: |
duke@435 | 341 | // helpers |
duke@435 | 342 | |
duke@435 | 343 | // x is supposed to fit in a field "nbits" wide |
duke@435 | 344 | // and be sign-extended. Check the range. |
duke@435 | 345 | |
duke@435 | 346 | static void assert_signed_range(intptr_t x, int nbits) { |
never@2950 | 347 | assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)), |
never@2950 | 348 | err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits)); |
duke@435 | 349 | } |
duke@435 | 350 | |
duke@435 | 351 | static void assert_signed_word_disp_range(intptr_t x, int nbits) { |
duke@435 | 352 | assert( (x & 3) == 0, "not word aligned"); |
duke@435 | 353 | assert_signed_range(x, nbits + 2); |
duke@435 | 354 | } |
duke@435 | 355 | |
duke@435 | 356 | static void assert_unsigned_const(int x, int nbits) { |
duke@435 | 357 | assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); |
duke@435 | 358 | } |
duke@435 | 359 | |
duke@435 | 360 | // fields: note bits numbered from LSB = 0, |
duke@435 | 361 | // fields known by inclusive bit range |
duke@435 | 362 | |
duke@435 | 363 | static int fmask(juint hi_bit, juint lo_bit) { |
duke@435 | 364 | assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); |
duke@435 | 365 | return (1 << ( hi_bit-lo_bit + 1 )) - 1; |
duke@435 | 366 | } |
duke@435 | 367 | |
duke@435 | 368 | // inverse of u_field |
duke@435 | 369 | |
duke@435 | 370 | static int inv_u_field(int x, int hi_bit, int lo_bit) { |
duke@435 | 371 | juint r = juint(x) >> lo_bit; |
duke@435 | 372 | r &= fmask( hi_bit, lo_bit); |
duke@435 | 373 | return int(r); |
duke@435 | 374 | } |
duke@435 | 375 | |
duke@435 | 376 | |
duke@435 | 377 | // signed version: extract from field and sign-extend |
duke@435 | 378 | |
duke@435 | 379 | static int inv_s_field(int x, int hi_bit, int lo_bit) { |
duke@435 | 380 | int sign_shift = 31 - hi_bit; |
duke@435 | 381 | return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); |
duke@435 | 382 | } |
duke@435 | 383 | |
duke@435 | 384 | // given a field that ranges from hi_bit to lo_bit (inclusive, |
duke@435 | 385 | // LSB = 0), and an unsigned value for the field, |
duke@435 | 386 | // shift it into the field |
duke@435 | 387 | |
duke@435 | 388 | #ifdef ASSERT |
duke@435 | 389 | static int u_field(int x, int hi_bit, int lo_bit) { |
duke@435 | 390 | assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, |
duke@435 | 391 | "value out of range"); |
duke@435 | 392 | int r = x << lo_bit; |
duke@435 | 393 | assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); |
duke@435 | 394 | return r; |
duke@435 | 395 | } |
duke@435 | 396 | #else |
duke@435 | 397 | // make sure this is inlined as it will reduce code size significantly |
duke@435 | 398 | #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) |
duke@435 | 399 | #endif |
duke@435 | 400 | |
duke@435 | 401 | static int inv_op( int x ) { return inv_u_field(x, 31, 30); } |
duke@435 | 402 | static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } |
duke@435 | 403 | static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } |
duke@435 | 404 | static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } |
duke@435 | 405 | |
duke@435 | 406 | static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } |
duke@435 | 407 | |
duke@435 | 408 | static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } |
duke@435 | 409 | static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } |
duke@435 | 410 | static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } |
duke@435 | 411 | |
duke@435 | 412 | static int op( int x) { return u_field(x, 31, 30); } |
duke@435 | 413 | static int rd( Register r) { return u_field(r->encoding(), 29, 25); } |
duke@435 | 414 | static int fcn( int x) { return u_field(x, 29, 25); } |
duke@435 | 415 | static int op3( int x) { return u_field(x, 24, 19); } |
duke@435 | 416 | static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } |
duke@435 | 417 | static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } |
duke@435 | 418 | static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } |
duke@435 | 419 | static int cond( int x) { return u_field(x, 28, 25); } |
duke@435 | 420 | static int cond_mov( int x) { return u_field(x, 17, 14); } |
duke@435 | 421 | static int rcond( RCondition x) { return u_field(x, 12, 10); } |
duke@435 | 422 | static int op2( int x) { return u_field(x, 24, 22); } |
duke@435 | 423 | static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } |
duke@435 | 424 | static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } |
duke@435 | 425 | static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } |
duke@435 | 426 | static int imm_asi( int x) { return u_field(x, 12, 5); } |
duke@435 | 427 | static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } |
duke@435 | 428 | static int opf_low6( int w) { return u_field(w, 10, 5); } |
duke@435 | 429 | static int opf_low5( int w) { return u_field(w, 9, 5); } |
duke@435 | 430 | static int trapcc( CC cc) { return u_field(cc, 12, 11); } |
duke@435 | 431 | static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit |
duke@435 | 432 | static int opf( int x) { return u_field(x, 13, 5); } |
duke@435 | 433 | |
kvn@3037 | 434 | static bool is_cbcond( int x ) { |
kvn@3037 | 435 | return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) && |
kvn@3037 | 436 | inv_op(x) == branch_op && inv_op2(x) == bpr_op2); |
kvn@3037 | 437 | } |
kvn@3037 | 438 | static bool is_cxb( int x ) { |
kvn@3037 | 439 | assert(is_cbcond(x), "wrong instruction"); |
kvn@3037 | 440 | return (x & (1<<21)) != 0; |
kvn@3037 | 441 | } |
kvn@3037 | 442 | static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); } |
kvn@3037 | 443 | static int inv_cond_cbcond(int x) { |
kvn@3037 | 444 | assert(is_cbcond(x), "wrong instruction"); |
kvn@3037 | 445 | return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3); |
kvn@3037 | 446 | } |
kvn@3037 | 447 | |
duke@435 | 448 | static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } |
duke@435 | 449 | static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } |
duke@435 | 450 | |
duke@435 | 451 | static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; |
duke@435 | 452 | static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; |
duke@435 | 453 | static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; |
duke@435 | 454 | |
duke@435 | 455 | // some float instructions use this encoding on the op3 field |
duke@435 | 456 | static int alt_op3(int op, FloatRegisterImpl::Width w) { |
duke@435 | 457 | int r; |
duke@435 | 458 | switch(w) { |
duke@435 | 459 | case FloatRegisterImpl::S: r = op + 0; break; |
duke@435 | 460 | case FloatRegisterImpl::D: r = op + 3; break; |
duke@435 | 461 | case FloatRegisterImpl::Q: r = op + 2; break; |
duke@435 | 462 | default: ShouldNotReachHere(); break; |
duke@435 | 463 | } |
duke@435 | 464 | return op3(r); |
duke@435 | 465 | } |
duke@435 | 466 | |
duke@435 | 467 | |
duke@435 | 468 | // compute inverse of simm |
duke@435 | 469 | static int inv_simm(int x, int nbits) { |
duke@435 | 470 | return (int)(x << (32 - nbits)) >> (32 - nbits); |
duke@435 | 471 | } |
duke@435 | 472 | |
duke@435 | 473 | static int inv_simm13( int x ) { return inv_simm(x, 13); } |
duke@435 | 474 | |
duke@435 | 475 | // signed immediate, in low bits, nbits long |
duke@435 | 476 | static int simm(int x, int nbits) { |
duke@435 | 477 | assert_signed_range(x, nbits); |
duke@435 | 478 | return x & (( 1 << nbits ) - 1); |
duke@435 | 479 | } |
duke@435 | 480 | |
duke@435 | 481 | // compute inverse of wdisp16 |
duke@435 | 482 | static intptr_t inv_wdisp16(int x, intptr_t pos) { |
duke@435 | 483 | int lo = x & (( 1 << 14 ) - 1); |
duke@435 | 484 | int hi = (x >> 20) & 3; |
duke@435 | 485 | if (hi >= 2) hi |= ~1; |
duke@435 | 486 | return (((hi << 14) | lo) << 2) + pos; |
duke@435 | 487 | } |
duke@435 | 488 | |
duke@435 | 489 | // word offset, 14 bits at LSend, 2 bits at B21, B20 |
duke@435 | 490 | static int wdisp16(intptr_t x, intptr_t off) { |
duke@435 | 491 | intptr_t xx = x - off; |
duke@435 | 492 | assert_signed_word_disp_range(xx, 16); |
duke@435 | 493 | int r = (xx >> 2) & ((1 << 14) - 1) |
duke@435 | 494 | | ( ( (xx>>(2+14)) & 3 ) << 20 ); |
duke@435 | 495 | assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); |
duke@435 | 496 | return r; |
duke@435 | 497 | } |
duke@435 | 498 | |
kvn@3037 | 499 | // compute inverse of wdisp10 |
kvn@3037 | 500 | static intptr_t inv_wdisp10(int x, intptr_t pos) { |
kvn@3037 | 501 | assert(is_cbcond(x), "wrong instruction"); |
kvn@3037 | 502 | int lo = inv_u_field(x, 12, 5); |
kvn@3037 | 503 | int hi = (x >> 19) & 3; |
kvn@3037 | 504 | if (hi >= 2) hi |= ~1; |
kvn@3037 | 505 | return (((hi << 8) | lo) << 2) + pos; |
kvn@3037 | 506 | } |
kvn@3037 | 507 | |
kvn@3037 | 508 | // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19] |
kvn@3037 | 509 | static int wdisp10(intptr_t x, intptr_t off) { |
kvn@3037 | 510 | assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction"); |
kvn@3037 | 511 | intptr_t xx = x - off; |
kvn@3037 | 512 | assert_signed_word_disp_range(xx, 10); |
kvn@3037 | 513 | int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 ) |
kvn@3037 | 514 | | ( ( (xx >> (2+8)) & 3 ) << 19 ); |
kvn@3037 | 515 | // Have to fake cbcond instruction to pass assert in inv_wdisp10() |
kvn@3037 | 516 | assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse"); |
kvn@3037 | 517 | return r; |
kvn@3037 | 518 | } |
duke@435 | 519 | |
duke@435 | 520 | // word displacement in low-order nbits bits |
duke@435 | 521 | |
duke@435 | 522 | static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { |
duke@435 | 523 | int pre_sign_extend = x & (( 1 << nbits ) - 1); |
duke@435 | 524 | int r = pre_sign_extend >= ( 1 << (nbits-1) ) |
duke@435 | 525 | ? pre_sign_extend | ~(( 1 << nbits ) - 1) |
duke@435 | 526 | : pre_sign_extend; |
duke@435 | 527 | return (r << 2) + pos; |
duke@435 | 528 | } |
duke@435 | 529 | |
duke@435 | 530 | static int wdisp( intptr_t x, intptr_t off, int nbits ) { |
duke@435 | 531 | intptr_t xx = x - off; |
duke@435 | 532 | assert_signed_word_disp_range(xx, nbits); |
duke@435 | 533 | int r = (xx >> 2) & (( 1 << nbits ) - 1); |
duke@435 | 534 | assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); |
duke@435 | 535 | return r; |
duke@435 | 536 | } |
duke@435 | 537 | |
duke@435 | 538 | |
duke@435 | 539 | // Extract the top 32 bits in a 64 bit word |
duke@435 | 540 | static int32_t hi32( int64_t x ) { |
duke@435 | 541 | int32_t r = int32_t( (uint64_t)x >> 32 ); |
duke@435 | 542 | return r; |
duke@435 | 543 | } |
duke@435 | 544 | |
duke@435 | 545 | // given a sethi instruction, extract the constant, left-justified |
duke@435 | 546 | static int inv_hi22( int x ) { |
duke@435 | 547 | return x << 10; |
duke@435 | 548 | } |
duke@435 | 549 | |
duke@435 | 550 | // create an imm22 field, given a 32-bit left-justified constant |
duke@435 | 551 | static int hi22( int x ) { |
duke@435 | 552 | int r = int( juint(x) >> 10 ); |
duke@435 | 553 | assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); |
duke@435 | 554 | return r; |
duke@435 | 555 | } |
duke@435 | 556 | |
duke@435 | 557 | // create a low10 __value__ (not a field) for a given a 32-bit constant |
duke@435 | 558 | static int low10( int x ) { |
duke@435 | 559 | return x & ((1 << 10) - 1); |
duke@435 | 560 | } |
duke@435 | 561 | |
kvn@3001 | 562 | // instruction only in VIS3 |
kvn@3001 | 563 | static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } |
kvn@3001 | 564 | |
duke@435 | 565 | // instruction only in v9 |
morris@5283 | 566 | static void v9_only() { } // do nothing |
duke@435 | 567 | |
duke@435 | 568 | // instruction deprecated in v9 |
duke@435 | 569 | static void v9_dep() { } // do nothing for now |
duke@435 | 570 | |
duke@435 | 571 | // v8 has no CC field |
duke@435 | 572 | static void v8_no_cc(CC cc) { if (cc) v9_only(); } |
duke@435 | 573 | |
duke@435 | 574 | protected: |
duke@435 | 575 | // Simple delay-slot scheme: |
duke@435 | 576 | // In order to check the programmer, the assembler keeps track of deley slots. |
duke@435 | 577 | // It forbids CTIs in delay slots (conservative, but should be OK). |
duke@435 | 578 | // Also, when putting an instruction into a delay slot, you must say |
duke@435 | 579 | // asm->delayed()->add(...), in order to check that you don't omit |
duke@435 | 580 | // delay-slot instructions. |
duke@435 | 581 | // To implement this, we use a simple FSA |
duke@435 | 582 | |
duke@435 | 583 | #ifdef ASSERT |
duke@435 | 584 | #define CHECK_DELAY |
duke@435 | 585 | #endif |
duke@435 | 586 | #ifdef CHECK_DELAY |
duke@435 | 587 | enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; |
duke@435 | 588 | #endif |
duke@435 | 589 | |
duke@435 | 590 | public: |
duke@435 | 591 | // Tells assembler next instruction must NOT be in delay slot. |
duke@435 | 592 | // Use at start of multinstruction macros. |
duke@435 | 593 | void assert_not_delayed() { |
duke@435 | 594 | // This is a separate overloading to avoid creation of string constants |
duke@435 | 595 | // in non-asserted code--with some compilers this pollutes the object code. |
duke@435 | 596 | #ifdef CHECK_DELAY |
duke@435 | 597 | assert_not_delayed("next instruction should not be a delay slot"); |
duke@435 | 598 | #endif |
duke@435 | 599 | } |
duke@435 | 600 | void assert_not_delayed(const char* msg) { |
duke@435 | 601 | #ifdef CHECK_DELAY |
jcoomes@1845 | 602 | assert(delay_state == no_delay, msg); |
duke@435 | 603 | #endif |
duke@435 | 604 | } |
duke@435 | 605 | |
duke@435 | 606 | protected: |
duke@435 | 607 | // Delay slot helpers |
duke@435 | 608 | // cti is called when emitting control-transfer instruction, |
duke@435 | 609 | // BEFORE doing the emitting. |
duke@435 | 610 | // Only effective when assertion-checking is enabled. |
duke@435 | 611 | void cti() { |
duke@435 | 612 | #ifdef CHECK_DELAY |
duke@435 | 613 | assert_not_delayed("cti should not be in delay slot"); |
duke@435 | 614 | #endif |
duke@435 | 615 | } |
duke@435 | 616 | |
duke@435 | 617 | // called when emitting cti with a delay slot, AFTER emitting |
duke@435 | 618 | void has_delay_slot() { |
duke@435 | 619 | #ifdef CHECK_DELAY |
duke@435 | 620 | assert_not_delayed("just checking"); |
duke@435 | 621 | delay_state = at_delay_slot; |
duke@435 | 622 | #endif |
duke@435 | 623 | } |
duke@435 | 624 | |
kvn@3037 | 625 | // cbcond instruction should not be generated one after an other |
kvn@3037 | 626 | bool cbcond_before() { |
kvn@3037 | 627 | if (offset() == 0) return false; // it is first instruction |
kvn@3037 | 628 | int x = *(int*)(intptr_t(pc()) - 4); // previous instruction |
kvn@3037 | 629 | return is_cbcond(x); |
kvn@3037 | 630 | } |
kvn@3037 | 631 | |
kvn@3037 | 632 | void no_cbcond_before() { |
kvn@3037 | 633 | assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond"); |
kvn@3037 | 634 | } |
kvn@3037 | 635 | |
kvn@3049 | 636 | public: |
kvn@3049 | 637 | |
kvn@3037 | 638 | bool use_cbcond(Label& L) { |
kvn@3037 | 639 | if (!UseCBCond || cbcond_before()) return false; |
kvn@3037 | 640 | intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc()); |
kvn@3037 | 641 | assert( (x & 3) == 0, "not word aligned"); |
twisti@3310 | 642 | return is_simm12(x); |
kvn@3037 | 643 | } |
kvn@3037 | 644 | |
duke@435 | 645 | // Tells assembler you know that next instruction is delayed |
duke@435 | 646 | Assembler* delayed() { |
duke@435 | 647 | #ifdef CHECK_DELAY |
duke@435 | 648 | assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); |
duke@435 | 649 | delay_state = filling_delay_slot; |
duke@435 | 650 | #endif |
duke@435 | 651 | return this; |
duke@435 | 652 | } |
duke@435 | 653 | |
duke@435 | 654 | void flush() { |
duke@435 | 655 | #ifdef CHECK_DELAY |
duke@435 | 656 | assert ( delay_state == no_delay, "ending code with a delay slot"); |
duke@435 | 657 | #endif |
duke@435 | 658 | AbstractAssembler::flush(); |
duke@435 | 659 | } |
duke@435 | 660 | |
twisti@4412 | 661 | inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 |
twisti@4412 | 662 | inline void emit_data(int x) { emit_int32(x); } |
duke@435 | 663 | inline void emit_data(int, RelocationHolder const&); |
duke@435 | 664 | inline void emit_data(int, relocInfo::relocType rtype); |
duke@435 | 665 | // helper for above fcns |
duke@435 | 666 | inline void check_delay(); |
duke@435 | 667 | |
duke@435 | 668 | |
duke@435 | 669 | public: |
duke@435 | 670 | // instructions, refer to page numbers in the SPARC Architecture Manual, V9 |
duke@435 | 671 | |
duke@435 | 672 | // pp 135 (addc was addx in v8) |
duke@435 | 673 | |
twisti@1162 | 674 | inline void add(Register s1, Register s2, Register d ); |
twisti@4323 | 675 | inline void add(Register s1, int simm13a, Register d ); |
duke@435 | 676 | |
twisti@4412 | 677 | void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 678 | void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 679 | void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 680 | void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 681 | void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 682 | void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 683 | |
kvn@3037 | 684 | |
duke@435 | 685 | // pp 136 |
duke@435 | 686 | |
kvn@3037 | 687 | inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none); |
kvn@3037 | 688 | inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L); |
duke@435 | 689 | |
kvn@3037 | 690 | // compare and branch |
kvn@3037 | 691 | inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L); |
kvn@3037 | 692 | inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L); |
kvn@3037 | 693 | |
kvn@3049 | 694 | protected: // use MacroAssembler::br instead |
kvn@3049 | 695 | |
kvn@3049 | 696 | // pp 138 |
kvn@3049 | 697 | |
kvn@3049 | 698 | inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); |
kvn@3049 | 699 | inline void fb( Condition c, bool a, Label& L ); |
kvn@3049 | 700 | |
kvn@3049 | 701 | // pp 141 |
kvn@3049 | 702 | |
kvn@3049 | 703 | inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
kvn@3049 | 704 | inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); |
kvn@3049 | 705 | |
kvn@3049 | 706 | // pp 144 |
kvn@3049 | 707 | |
kvn@3049 | 708 | inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); |
kvn@3049 | 709 | inline void br( Condition c, bool a, Label& L ); |
kvn@3049 | 710 | |
kvn@3049 | 711 | // pp 146 |
kvn@3049 | 712 | |
kvn@3049 | 713 | inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
kvn@3049 | 714 | inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); |
kvn@3049 | 715 | |
duke@435 | 716 | // pp 149 |
duke@435 | 717 | |
duke@435 | 718 | inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); |
duke@435 | 719 | inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); |
duke@435 | 720 | |
kvn@3037 | 721 | public: |
kvn@3037 | 722 | |
duke@435 | 723 | // pp 150 |
duke@435 | 724 | |
duke@435 | 725 | // These instructions compare the contents of s2 with the contents of |
duke@435 | 726 | // memory at address in s1. If the values are equal, the contents of memory |
duke@435 | 727 | // at address s1 is swapped with the data in d. If the values are not equal, |
duke@435 | 728 | // the the contents of memory at s1 is loaded into d, without the swap. |
duke@435 | 729 | |
twisti@4412 | 730 | void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } |
twisti@4412 | 731 | void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } |
duke@435 | 732 | |
duke@435 | 733 | // pp 152 |
duke@435 | 734 | |
twisti@4412 | 735 | void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } |
twisti@4412 | 736 | void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 737 | void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } |
twisti@4412 | 738 | void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 739 | void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } |
twisti@4412 | 740 | void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 741 | void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } |
twisti@4412 | 742 | void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 743 | |
duke@435 | 744 | // pp 155 |
duke@435 | 745 | |
twisti@4412 | 746 | void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); } |
twisti@4412 | 747 | void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); } |
duke@435 | 748 | |
duke@435 | 749 | // pp 156 |
duke@435 | 750 | |
twisti@4412 | 751 | void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } |
twisti@4412 | 752 | void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } |
duke@435 | 753 | |
duke@435 | 754 | // pp 157 |
duke@435 | 755 | |
morris@5283 | 756 | void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } |
morris@5283 | 757 | void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } |
duke@435 | 758 | |
duke@435 | 759 | // pp 159 |
duke@435 | 760 | |
twisti@4412 | 761 | void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } |
twisti@4412 | 762 | void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } |
duke@435 | 763 | |
duke@435 | 764 | // pp 160 |
duke@435 | 765 | |
twisti@4412 | 766 | void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } |
duke@435 | 767 | |
duke@435 | 768 | // pp 161 |
duke@435 | 769 | |
twisti@4412 | 770 | void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); } |
twisti@4412 | 771 | void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); } |
duke@435 | 772 | |
duke@435 | 773 | // pp 162 |
duke@435 | 774 | |
morris@5283 | 775 | void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } |
duke@435 | 776 | |
morris@5283 | 777 | void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } |
duke@435 | 778 | |
morris@5283 | 779 | void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } |
duke@435 | 780 | |
duke@435 | 781 | // pp 163 |
duke@435 | 782 | |
twisti@4412 | 783 | void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } |
twisti@4412 | 784 | void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } |
twisti@4412 | 785 | void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } |
duke@435 | 786 | |
duke@435 | 787 | // pp 164 |
duke@435 | 788 | |
twisti@4412 | 789 | void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } |
duke@435 | 790 | |
duke@435 | 791 | // pp 165 |
duke@435 | 792 | |
duke@435 | 793 | inline void flush( Register s1, Register s2 ); |
duke@435 | 794 | inline void flush( Register s1, int simm13a); |
duke@435 | 795 | |
duke@435 | 796 | // pp 167 |
duke@435 | 797 | |
twisti@4412 | 798 | void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); } |
duke@435 | 799 | |
duke@435 | 800 | // pp 168 |
duke@435 | 801 | |
twisti@4412 | 802 | void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); } |
duke@435 | 803 | // v8 unimp == illtrap(0) |
duke@435 | 804 | |
duke@435 | 805 | // pp 169 |
duke@435 | 806 | |
twisti@4412 | 807 | void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } |
twisti@4412 | 808 | void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } |
duke@435 | 809 | |
duke@435 | 810 | // pp 170 |
duke@435 | 811 | |
duke@435 | 812 | void jmpl( Register s1, Register s2, Register d ); |
duke@435 | 813 | void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); |
duke@435 | 814 | |
duke@435 | 815 | // 171 |
duke@435 | 816 | |
twisti@1162 | 817 | inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); |
twisti@1162 | 818 | inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder()); |
twisti@1162 | 819 | |
duke@435 | 820 | |
duke@435 | 821 | inline void ldfsr( Register s1, Register s2 ); |
duke@435 | 822 | inline void ldfsr( Register s1, int simm13a); |
duke@435 | 823 | inline void ldxfsr( Register s1, Register s2 ); |
duke@435 | 824 | inline void ldxfsr( Register s1, int simm13a); |
duke@435 | 825 | |
duke@435 | 826 | // 173 |
duke@435 | 827 | |
twisti@4412 | 828 | void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 829 | void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 830 | |
duke@435 | 831 | // pp 175, lduw is ld on v8 |
duke@435 | 832 | |
duke@435 | 833 | inline void ldsb( Register s1, Register s2, Register d ); |
duke@435 | 834 | inline void ldsb( Register s1, int simm13a, Register d); |
duke@435 | 835 | inline void ldsh( Register s1, Register s2, Register d ); |
duke@435 | 836 | inline void ldsh( Register s1, int simm13a, Register d); |
duke@435 | 837 | inline void ldsw( Register s1, Register s2, Register d ); |
duke@435 | 838 | inline void ldsw( Register s1, int simm13a, Register d); |
duke@435 | 839 | inline void ldub( Register s1, Register s2, Register d ); |
duke@435 | 840 | inline void ldub( Register s1, int simm13a, Register d); |
duke@435 | 841 | inline void lduh( Register s1, Register s2, Register d ); |
duke@435 | 842 | inline void lduh( Register s1, int simm13a, Register d); |
duke@435 | 843 | inline void lduw( Register s1, Register s2, Register d ); |
duke@435 | 844 | inline void lduw( Register s1, int simm13a, Register d); |
duke@435 | 845 | inline void ldx( Register s1, Register s2, Register d ); |
duke@435 | 846 | inline void ldx( Register s1, int simm13a, Register d); |
duke@435 | 847 | inline void ldd( Register s1, Register s2, Register d ); |
duke@435 | 848 | inline void ldd( Register s1, int simm13a, Register d); |
duke@435 | 849 | |
duke@435 | 850 | // pp 177 |
duke@435 | 851 | |
twisti@4412 | 852 | void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 853 | void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 854 | void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 855 | void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 856 | void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 857 | void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 858 | void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 859 | void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 860 | void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 861 | void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 862 | void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 863 | void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 864 | void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 865 | void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 866 | |
duke@435 | 867 | // pp 181 |
duke@435 | 868 | |
twisti@4412 | 869 | void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 870 | void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 871 | void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 872 | void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 873 | void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 874 | void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 875 | void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 876 | void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 877 | void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 878 | void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 879 | void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 880 | void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 881 | void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 882 | void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 883 | void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 884 | void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 885 | void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 886 | void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 887 | void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 888 | void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 889 | void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 890 | void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 891 | void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 892 | void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 893 | |
duke@435 | 894 | // pp 183 |
duke@435 | 895 | |
twisti@4412 | 896 | void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } |
duke@435 | 897 | |
duke@435 | 898 | // pp 185 |
duke@435 | 899 | |
twisti@4412 | 900 | void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } |
duke@435 | 901 | |
duke@435 | 902 | // pp 189 |
duke@435 | 903 | |
twisti@4412 | 904 | void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } |
duke@435 | 905 | |
duke@435 | 906 | // pp 191 |
duke@435 | 907 | |
twisti@4412 | 908 | void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } |
twisti@4412 | 909 | void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } |
duke@435 | 910 | |
duke@435 | 911 | // pp 195 |
duke@435 | 912 | |
twisti@4412 | 913 | void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } |
twisti@4412 | 914 | void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } |
duke@435 | 915 | |
duke@435 | 916 | // pp 196 |
duke@435 | 917 | |
twisti@4412 | 918 | void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 919 | void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 920 | void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 921 | void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 922 | void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 923 | void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 924 | |
duke@435 | 925 | // pp 197 |
duke@435 | 926 | |
twisti@4412 | 927 | void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 928 | void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 929 | void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 930 | void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 931 | void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 932 | void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 933 | void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 934 | void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 935 | |
duke@435 | 936 | // pp 201 |
duke@435 | 937 | |
twisti@4412 | 938 | void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); } |
duke@435 | 939 | |
duke@435 | 940 | |
duke@435 | 941 | // pp 202 |
duke@435 | 942 | |
twisti@4412 | 943 | void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } |
twisti@4412 | 944 | void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 945 | |
duke@435 | 946 | // pp 203 |
duke@435 | 947 | |
twisti@4412 | 948 | void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4323 | 949 | void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
twisti@4323 | 950 | |
twisti@4412 | 951 | void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 952 | void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 953 | |
duke@435 | 954 | // pp 208 |
duke@435 | 955 | |
duke@435 | 956 | // not implementing read privileged register |
duke@435 | 957 | |
twisti@4412 | 958 | inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } |
twisti@4412 | 959 | inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } |
twisti@4412 | 960 | inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } |
twisti@4412 | 961 | inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! |
twisti@4412 | 962 | inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } |
twisti@4412 | 963 | inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } |
duke@435 | 964 | |
duke@435 | 965 | // pp 213 |
duke@435 | 966 | |
duke@435 | 967 | inline void rett( Register s1, Register s2); |
duke@435 | 968 | inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); |
duke@435 | 969 | |
duke@435 | 970 | // pp 214 |
duke@435 | 971 | |
twisti@4412 | 972 | void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } |
ysr@777 | 973 | void save( Register s1, int simm13a, Register d ) { |
ysr@777 | 974 | // make sure frame is at least large enough for the register save area |
ysr@777 | 975 | assert(-simm13a >= 16 * wordSize, "frame too small"); |
twisti@4412 | 976 | emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); |
ysr@777 | 977 | } |
duke@435 | 978 | |
twisti@4412 | 979 | void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 980 | void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 981 | |
duke@435 | 982 | // pp 216 |
duke@435 | 983 | |
twisti@4412 | 984 | void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); } |
twisti@4412 | 985 | void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); } |
duke@435 | 986 | |
duke@435 | 987 | // pp 217 |
duke@435 | 988 | |
duke@435 | 989 | inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); |
duke@435 | 990 | // pp 218 |
duke@435 | 991 | |
twisti@4412 | 992 | void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } |
twisti@4412 | 993 | void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } |
twisti@4412 | 994 | void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } |
twisti@4412 | 995 | void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } |
twisti@4412 | 996 | void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } |
twisti@4412 | 997 | void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } |
duke@435 | 998 | |
twisti@4412 | 999 | void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } |
twisti@4412 | 1000 | void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } |
twisti@4412 | 1001 | void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } |
twisti@4412 | 1002 | void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } |
twisti@4412 | 1003 | void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } |
twisti@4412 | 1004 | void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } |
duke@435 | 1005 | |
duke@435 | 1006 | // pp 220 |
duke@435 | 1007 | |
twisti@4412 | 1008 | void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } |
duke@435 | 1009 | |
duke@435 | 1010 | // pp 221 |
duke@435 | 1011 | |
twisti@4412 | 1012 | void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } |
duke@435 | 1013 | |
duke@435 | 1014 | // pp 222 |
duke@435 | 1015 | |
twisti@1441 | 1016 | inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); |
duke@435 | 1017 | inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); |
duke@435 | 1018 | |
duke@435 | 1019 | inline void stfsr( Register s1, Register s2 ); |
duke@435 | 1020 | inline void stfsr( Register s1, int simm13a); |
duke@435 | 1021 | inline void stxfsr( Register s1, Register s2 ); |
duke@435 | 1022 | inline void stxfsr( Register s1, int simm13a); |
duke@435 | 1023 | |
duke@435 | 1024 | // pp 224 |
duke@435 | 1025 | |
twisti@4412 | 1026 | void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 1027 | void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 1028 | |
duke@435 | 1029 | // p 226 |
duke@435 | 1030 | |
duke@435 | 1031 | inline void stb( Register d, Register s1, Register s2 ); |
duke@435 | 1032 | inline void stb( Register d, Register s1, int simm13a); |
duke@435 | 1033 | inline void sth( Register d, Register s1, Register s2 ); |
duke@435 | 1034 | inline void sth( Register d, Register s1, int simm13a); |
duke@435 | 1035 | inline void stw( Register d, Register s1, Register s2 ); |
duke@435 | 1036 | inline void stw( Register d, Register s1, int simm13a); |
duke@435 | 1037 | inline void stx( Register d, Register s1, Register s2 ); |
duke@435 | 1038 | inline void stx( Register d, Register s1, int simm13a); |
duke@435 | 1039 | inline void std( Register d, Register s1, Register s2 ); |
duke@435 | 1040 | inline void std( Register d, Register s1, int simm13a); |
duke@435 | 1041 | |
duke@435 | 1042 | // pp 177 |
duke@435 | 1043 | |
twisti@4412 | 1044 | void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 1045 | void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 1046 | void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 1047 | void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 1048 | void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 1049 | void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 1050 | void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 1051 | void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 1052 | void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 1053 | void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 1054 | |
duke@435 | 1055 | // pp 230 |
duke@435 | 1056 | |
twisti@4412 | 1057 | void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 1058 | void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@2350 | 1059 | |
twisti@4412 | 1060 | void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 1061 | void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 1062 | void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 1063 | void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
twisti@4412 | 1064 | void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 1065 | void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 1066 | |
duke@435 | 1067 | // pp 231 |
duke@435 | 1068 | |
duke@435 | 1069 | inline void swap( Register s1, Register s2, Register d ); |
duke@435 | 1070 | inline void swap( Register s1, int simm13a, Register d); |
duke@435 | 1071 | |
duke@435 | 1072 | // pp 232 |
duke@435 | 1073 | |
twisti@4412 | 1074 | void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
twisti@4412 | 1075 | void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 1076 | |
duke@435 | 1077 | // pp 234, note op in book is wrong, see pp 268 |
duke@435 | 1078 | |
twisti@4412 | 1079 | void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 1080 | void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 1081 | |
duke@435 | 1082 | // pp 235 |
duke@435 | 1083 | |
twisti@4412 | 1084 | void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } |
twisti@4412 | 1085 | void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
duke@435 | 1086 | |
duke@435 | 1087 | // pp 237 |
duke@435 | 1088 | |
morris@5283 | 1089 | void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } |
morris@5283 | 1090 | void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } |
duke@435 | 1091 | // simple uncond. trap |
duke@435 | 1092 | void trap( int trapa ) { trap( always, icc, G0, trapa ); } |
duke@435 | 1093 | |
duke@435 | 1094 | // pp 239 omit write priv register for now |
duke@435 | 1095 | |
twisti@4412 | 1096 | inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } |
twisti@4412 | 1097 | inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } |
twisti@4412 | 1098 | inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) | |
duke@435 | 1099 | rs1(s) | |
duke@435 | 1100 | op3(wrreg_op3) | |
duke@435 | 1101 | u_field(2, 29, 25) | |
kvn@3092 | 1102 | immed(true) | |
duke@435 | 1103 | simm(simm13a, 13)); } |
twisti@4412 | 1104 | inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } |
kvn@3092 | 1105 | // wrasi(d, imm) stores (d xor imm) to asi |
twisti@4412 | 1106 | inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | |
kvn@3092 | 1107 | u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); } |
twisti@4412 | 1108 | inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } |
duke@435 | 1109 | |
kvn@3001 | 1110 | |
kvn@3001 | 1111 | // VIS3 instructions |
kvn@3001 | 1112 | |
twisti@4412 | 1113 | void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); } |
twisti@4412 | 1114 | void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); } |
twisti@4412 | 1115 | void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); } |
kvn@3001 | 1116 | |
twisti@4412 | 1117 | void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); } |
twisti@4412 | 1118 | void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); } |
kvn@3001 | 1119 | |
duke@435 | 1120 | // Creation |
duke@435 | 1121 | Assembler(CodeBuffer* code) : AbstractAssembler(code) { |
duke@435 | 1122 | #ifdef CHECK_DELAY |
duke@435 | 1123 | delay_state = no_delay; |
duke@435 | 1124 | #endif |
duke@435 | 1125 | } |
duke@435 | 1126 | }; |
duke@435 | 1127 | |
stefank@2314 | 1128 | #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |