Tue, 08 Aug 2017 15:57:29 +0800
merge
aoqi@0 | 1 | /* |
aoqi@0 | 2 | * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
aoqi@0 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@0 | 4 | * |
aoqi@0 | 5 | * This code is free software; you can redistribute it and/or modify it |
aoqi@0 | 6 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@0 | 7 | * published by the Free Software Foundation. |
aoqi@0 | 8 | * |
aoqi@0 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@0 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@0 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@0 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@0 | 13 | * accompanied this code). |
aoqi@0 | 14 | * |
aoqi@0 | 15 | * You should have received a copy of the GNU General Public License version |
aoqi@0 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@0 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@0 | 18 | * |
aoqi@0 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@0 | 20 | * or visit www.oracle.com if you need additional information or have any |
aoqi@0 | 21 | * questions. |
aoqi@0 | 22 | * |
aoqi@0 | 23 | */ |
aoqi@0 | 24 | |
aoqi@1 | 25 | /* |
aoqi@1 | 26 | * This file has been modified by Loongson Technology in 2015. These |
aoqi@1 | 27 | * modifications are Copyright (c) 2015 Loongson Technology, and are made |
aoqi@1 | 28 | * available on the same license terms set forth above. |
aoqi@1 | 29 | */ |
aoqi@1 | 30 | |
aoqi@0 | 31 | #ifndef SHARE_VM_C1_C1_LIR_HPP |
aoqi@0 | 32 | #define SHARE_VM_C1_C1_LIR_HPP |
aoqi@0 | 33 | |
aoqi@0 | 34 | #include "c1/c1_ValueType.hpp" |
aoqi@0 | 35 | #include "oops/method.hpp" |
aoqi@0 | 36 | |
aoqi@0 | 37 | class BlockBegin; |
aoqi@0 | 38 | class BlockList; |
aoqi@0 | 39 | class LIR_Assembler; |
aoqi@0 | 40 | class CodeEmitInfo; |
aoqi@0 | 41 | class CodeStub; |
aoqi@0 | 42 | class CodeStubList; |
aoqi@0 | 43 | class ArrayCopyStub; |
aoqi@0 | 44 | class LIR_Op; |
aoqi@0 | 45 | class ciType; |
aoqi@0 | 46 | class ValueType; |
aoqi@0 | 47 | class LIR_OpVisitState; |
aoqi@0 | 48 | class FpuStackSim; |
aoqi@0 | 49 | |
aoqi@0 | 50 | //--------------------------------------------------------------------- |
aoqi@0 | 51 | // LIR Operands |
aoqi@0 | 52 | // LIR_OprDesc |
aoqi@0 | 53 | // LIR_OprPtr |
aoqi@0 | 54 | // LIR_Const |
aoqi@0 | 55 | // LIR_Address |
aoqi@0 | 56 | //--------------------------------------------------------------------- |
aoqi@0 | 57 | class LIR_OprDesc; |
aoqi@0 | 58 | class LIR_OprPtr; |
aoqi@0 | 59 | class LIR_Const; |
aoqi@0 | 60 | class LIR_Address; |
aoqi@0 | 61 | class LIR_OprVisitor; |
aoqi@0 | 62 | |
aoqi@0 | 63 | |
aoqi@0 | 64 | typedef LIR_OprDesc* LIR_Opr; |
aoqi@0 | 65 | typedef int RegNr; |
aoqi@0 | 66 | |
aoqi@0 | 67 | define_array(LIR_OprArray, LIR_Opr) |
aoqi@0 | 68 | define_stack(LIR_OprList, LIR_OprArray) |
aoqi@0 | 69 | |
aoqi@0 | 70 | define_array(LIR_OprRefArray, LIR_Opr*) |
aoqi@0 | 71 | define_stack(LIR_OprRefList, LIR_OprRefArray) |
aoqi@0 | 72 | |
aoqi@0 | 73 | define_array(CodeEmitInfoArray, CodeEmitInfo*) |
aoqi@0 | 74 | define_stack(CodeEmitInfoList, CodeEmitInfoArray) |
aoqi@0 | 75 | |
aoqi@0 | 76 | define_array(LIR_OpArray, LIR_Op*) |
aoqi@0 | 77 | define_stack(LIR_OpList, LIR_OpArray) |
aoqi@0 | 78 | |
aoqi@0 | 79 | // define LIR_OprPtr early so LIR_OprDesc can refer to it |
aoqi@0 | 80 | class LIR_OprPtr: public CompilationResourceObj { |
aoqi@0 | 81 | public: |
aoqi@0 | 82 | bool is_oop_pointer() const { return (type() == T_OBJECT); } |
aoqi@0 | 83 | bool is_float_kind() const { BasicType t = type(); return (t == T_FLOAT) || (t == T_DOUBLE); } |
aoqi@0 | 84 | |
aoqi@0 | 85 | virtual LIR_Const* as_constant() { return NULL; } |
aoqi@0 | 86 | virtual LIR_Address* as_address() { return NULL; } |
aoqi@0 | 87 | virtual BasicType type() const = 0; |
aoqi@0 | 88 | virtual void print_value_on(outputStream* out) const = 0; |
aoqi@0 | 89 | }; |
aoqi@0 | 90 | |
aoqi@0 | 91 | |
aoqi@0 | 92 | |
aoqi@0 | 93 | // LIR constants |
aoqi@0 | 94 | class LIR_Const: public LIR_OprPtr { |
aoqi@0 | 95 | private: |
aoqi@0 | 96 | JavaValue _value; |
aoqi@0 | 97 | |
aoqi@0 | 98 | void type_check(BasicType t) const { assert(type() == t, "type check"); } |
aoqi@0 | 99 | void type_check(BasicType t1, BasicType t2) const { assert(type() == t1 || type() == t2, "type check"); } |
aoqi@0 | 100 | void type_check(BasicType t1, BasicType t2, BasicType t3) const { assert(type() == t1 || type() == t2 || type() == t3, "type check"); } |
aoqi@0 | 101 | |
aoqi@0 | 102 | public: |
aoqi@0 | 103 | LIR_Const(jint i, bool is_address=false) { _value.set_type(is_address?T_ADDRESS:T_INT); _value.set_jint(i); } |
aoqi@0 | 104 | LIR_Const(jlong l) { _value.set_type(T_LONG); _value.set_jlong(l); } |
aoqi@0 | 105 | LIR_Const(jfloat f) { _value.set_type(T_FLOAT); _value.set_jfloat(f); } |
aoqi@0 | 106 | LIR_Const(jdouble d) { _value.set_type(T_DOUBLE); _value.set_jdouble(d); } |
aoqi@0 | 107 | LIR_Const(jobject o) { _value.set_type(T_OBJECT); _value.set_jobject(o); } |
aoqi@0 | 108 | LIR_Const(void* p) { |
aoqi@0 | 109 | #ifdef _LP64 |
aoqi@0 | 110 | assert(sizeof(jlong) >= sizeof(p), "too small");; |
aoqi@0 | 111 | _value.set_type(T_LONG); _value.set_jlong((jlong)p); |
aoqi@0 | 112 | #else |
aoqi@0 | 113 | assert(sizeof(jint) >= sizeof(p), "too small");; |
aoqi@0 | 114 | _value.set_type(T_INT); _value.set_jint((jint)p); |
aoqi@0 | 115 | #endif |
aoqi@0 | 116 | } |
aoqi@0 | 117 | LIR_Const(Metadata* m) { |
aoqi@0 | 118 | _value.set_type(T_METADATA); |
aoqi@0 | 119 | #ifdef _LP64 |
aoqi@0 | 120 | _value.set_jlong((jlong)m); |
aoqi@0 | 121 | #else |
aoqi@0 | 122 | _value.set_jint((jint)m); |
aoqi@0 | 123 | #endif // _LP64 |
aoqi@0 | 124 | } |
aoqi@0 | 125 | |
aoqi@0 | 126 | virtual BasicType type() const { return _value.get_type(); } |
aoqi@0 | 127 | virtual LIR_Const* as_constant() { return this; } |
aoqi@0 | 128 | |
aoqi@0 | 129 | jint as_jint() const { type_check(T_INT, T_ADDRESS); return _value.get_jint(); } |
aoqi@0 | 130 | jlong as_jlong() const { type_check(T_LONG ); return _value.get_jlong(); } |
aoqi@0 | 131 | jfloat as_jfloat() const { type_check(T_FLOAT ); return _value.get_jfloat(); } |
aoqi@0 | 132 | jdouble as_jdouble() const { type_check(T_DOUBLE); return _value.get_jdouble(); } |
aoqi@0 | 133 | jobject as_jobject() const { type_check(T_OBJECT); return _value.get_jobject(); } |
aoqi@0 | 134 | jint as_jint_lo() const { type_check(T_LONG ); return low(_value.get_jlong()); } |
aoqi@0 | 135 | jint as_jint_hi() const { type_check(T_LONG ); return high(_value.get_jlong()); } |
aoqi@0 | 136 | |
aoqi@0 | 137 | #ifdef _LP64 |
aoqi@0 | 138 | address as_pointer() const { type_check(T_LONG ); return (address)_value.get_jlong(); } |
aoqi@0 | 139 | Metadata* as_metadata() const { type_check(T_METADATA); return (Metadata*)_value.get_jlong(); } |
aoqi@0 | 140 | #else |
aoqi@0 | 141 | address as_pointer() const { type_check(T_INT ); return (address)_value.get_jint(); } |
aoqi@0 | 142 | Metadata* as_metadata() const { type_check(T_METADATA); return (Metadata*)_value.get_jint(); } |
aoqi@0 | 143 | #endif |
aoqi@0 | 144 | |
aoqi@0 | 145 | |
aoqi@0 | 146 | jint as_jint_bits() const { type_check(T_FLOAT, T_INT, T_ADDRESS); return _value.get_jint(); } |
aoqi@0 | 147 | jint as_jint_lo_bits() const { |
aoqi@0 | 148 | if (type() == T_DOUBLE) { |
aoqi@0 | 149 | return low(jlong_cast(_value.get_jdouble())); |
aoqi@0 | 150 | } else { |
aoqi@0 | 151 | return as_jint_lo(); |
aoqi@0 | 152 | } |
aoqi@0 | 153 | } |
aoqi@0 | 154 | jint as_jint_hi_bits() const { |
aoqi@0 | 155 | if (type() == T_DOUBLE) { |
aoqi@0 | 156 | return high(jlong_cast(_value.get_jdouble())); |
aoqi@0 | 157 | } else { |
aoqi@0 | 158 | return as_jint_hi(); |
aoqi@0 | 159 | } |
aoqi@0 | 160 | } |
aoqi@0 | 161 | jlong as_jlong_bits() const { |
aoqi@0 | 162 | if (type() == T_DOUBLE) { |
aoqi@0 | 163 | return jlong_cast(_value.get_jdouble()); |
aoqi@0 | 164 | } else { |
aoqi@0 | 165 | return as_jlong(); |
aoqi@0 | 166 | } |
aoqi@0 | 167 | } |
aoqi@0 | 168 | |
aoqi@0 | 169 | virtual void print_value_on(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 170 | |
aoqi@0 | 171 | |
aoqi@0 | 172 | bool is_zero_float() { |
aoqi@0 | 173 | jfloat f = as_jfloat(); |
aoqi@0 | 174 | jfloat ok = 0.0f; |
aoqi@0 | 175 | return jint_cast(f) == jint_cast(ok); |
aoqi@0 | 176 | } |
aoqi@0 | 177 | |
aoqi@0 | 178 | bool is_one_float() { |
aoqi@0 | 179 | jfloat f = as_jfloat(); |
aoqi@0 | 180 | return !g_isnan(f) && g_isfinite(f) && f == 1.0; |
aoqi@0 | 181 | } |
aoqi@0 | 182 | |
aoqi@0 | 183 | bool is_zero_double() { |
aoqi@0 | 184 | jdouble d = as_jdouble(); |
aoqi@0 | 185 | jdouble ok = 0.0; |
aoqi@0 | 186 | return jlong_cast(d) == jlong_cast(ok); |
aoqi@0 | 187 | } |
aoqi@0 | 188 | |
aoqi@0 | 189 | bool is_one_double() { |
aoqi@0 | 190 | jdouble d = as_jdouble(); |
aoqi@0 | 191 | return !g_isnan(d) && g_isfinite(d) && d == 1.0; |
aoqi@0 | 192 | } |
aoqi@0 | 193 | }; |
aoqi@0 | 194 | |
aoqi@0 | 195 | |
aoqi@0 | 196 | //---------------------LIR Operand descriptor------------------------------------ |
aoqi@0 | 197 | // |
aoqi@0 | 198 | // The class LIR_OprDesc represents a LIR instruction operand; |
aoqi@0 | 199 | // it can be a register (ALU/FPU), stack location or a constant; |
aoqi@0 | 200 | // Constants and addresses are represented as resource area allocated |
aoqi@0 | 201 | // structures (see above). |
aoqi@0 | 202 | // Registers and stack locations are inlined into the this pointer |
aoqi@0 | 203 | // (see value function). |
aoqi@0 | 204 | |
aoqi@0 | 205 | class LIR_OprDesc: public CompilationResourceObj { |
aoqi@0 | 206 | public: |
aoqi@0 | 207 | // value structure: |
aoqi@0 | 208 | // data opr-type opr-kind |
aoqi@0 | 209 | // +--------------+-------+-------+ |
aoqi@0 | 210 | // [max...........|7 6 5 4|3 2 1 0] |
aoqi@0 | 211 | // ^ |
aoqi@0 | 212 | // is_pointer bit |
aoqi@0 | 213 | // |
aoqi@0 | 214 | // lowest bit cleared, means it is a structure pointer |
aoqi@0 | 215 | // we need 4 bits to represent types |
aoqi@0 | 216 | |
aoqi@0 | 217 | private: |
aoqi@0 | 218 | friend class LIR_OprFact; |
aoqi@0 | 219 | |
aoqi@0 | 220 | // Conversion |
aoqi@0 | 221 | intptr_t value() const { return (intptr_t) this; } |
aoqi@0 | 222 | |
aoqi@0 | 223 | bool check_value_mask(intptr_t mask, intptr_t masked_value) const { |
aoqi@0 | 224 | return (value() & mask) == masked_value; |
aoqi@0 | 225 | } |
aoqi@0 | 226 | |
aoqi@0 | 227 | enum OprKind { |
aoqi@0 | 228 | pointer_value = 0 |
aoqi@0 | 229 | , stack_value = 1 |
aoqi@0 | 230 | , cpu_register = 3 |
aoqi@0 | 231 | , fpu_register = 5 |
aoqi@0 | 232 | , illegal_value = 7 |
aoqi@0 | 233 | }; |
aoqi@0 | 234 | |
aoqi@0 | 235 | enum OprBits { |
aoqi@0 | 236 | pointer_bits = 1 |
aoqi@0 | 237 | , kind_bits = 3 |
aoqi@0 | 238 | , type_bits = 4 |
aoqi@0 | 239 | , size_bits = 2 |
aoqi@0 | 240 | , destroys_bits = 1 |
aoqi@0 | 241 | , virtual_bits = 1 |
aoqi@0 | 242 | , is_xmm_bits = 1 |
aoqi@0 | 243 | , last_use_bits = 1 |
aoqi@0 | 244 | , is_fpu_stack_offset_bits = 1 // used in assertion checking on x86 for FPU stack slot allocation |
aoqi@0 | 245 | , non_data_bits = kind_bits + type_bits + size_bits + destroys_bits + last_use_bits + |
aoqi@0 | 246 | is_fpu_stack_offset_bits + virtual_bits + is_xmm_bits |
aoqi@0 | 247 | , data_bits = BitsPerInt - non_data_bits |
aoqi@0 | 248 | , reg_bits = data_bits / 2 // for two registers in one value encoding |
aoqi@0 | 249 | }; |
aoqi@0 | 250 | |
aoqi@0 | 251 | enum OprShift { |
aoqi@0 | 252 | kind_shift = 0 |
aoqi@0 | 253 | , type_shift = kind_shift + kind_bits |
aoqi@0 | 254 | , size_shift = type_shift + type_bits |
aoqi@0 | 255 | , destroys_shift = size_shift + size_bits |
aoqi@0 | 256 | , last_use_shift = destroys_shift + destroys_bits |
aoqi@0 | 257 | , is_fpu_stack_offset_shift = last_use_shift + last_use_bits |
aoqi@0 | 258 | , virtual_shift = is_fpu_stack_offset_shift + is_fpu_stack_offset_bits |
aoqi@0 | 259 | , is_xmm_shift = virtual_shift + virtual_bits |
aoqi@0 | 260 | , data_shift = is_xmm_shift + is_xmm_bits |
aoqi@0 | 261 | , reg1_shift = data_shift |
aoqi@0 | 262 | , reg2_shift = data_shift + reg_bits |
aoqi@0 | 263 | |
aoqi@0 | 264 | }; |
aoqi@0 | 265 | |
aoqi@0 | 266 | enum OprSize { |
aoqi@0 | 267 | single_size = 0 << size_shift |
aoqi@0 | 268 | , double_size = 1 << size_shift |
aoqi@0 | 269 | }; |
aoqi@0 | 270 | |
aoqi@0 | 271 | enum OprMask { |
aoqi@0 | 272 | kind_mask = right_n_bits(kind_bits) |
aoqi@0 | 273 | , type_mask = right_n_bits(type_bits) << type_shift |
aoqi@0 | 274 | , size_mask = right_n_bits(size_bits) << size_shift |
aoqi@0 | 275 | , last_use_mask = right_n_bits(last_use_bits) << last_use_shift |
aoqi@0 | 276 | , is_fpu_stack_offset_mask = right_n_bits(is_fpu_stack_offset_bits) << is_fpu_stack_offset_shift |
aoqi@0 | 277 | , virtual_mask = right_n_bits(virtual_bits) << virtual_shift |
aoqi@0 | 278 | , is_xmm_mask = right_n_bits(is_xmm_bits) << is_xmm_shift |
aoqi@0 | 279 | , pointer_mask = right_n_bits(pointer_bits) |
aoqi@0 | 280 | , lower_reg_mask = right_n_bits(reg_bits) |
aoqi@0 | 281 | , no_type_mask = (int)(~(type_mask | last_use_mask | is_fpu_stack_offset_mask)) |
aoqi@0 | 282 | }; |
aoqi@0 | 283 | |
aoqi@0 | 284 | uintptr_t data() const { return value() >> data_shift; } |
aoqi@0 | 285 | int lo_reg_half() const { return data() & lower_reg_mask; } |
aoqi@0 | 286 | int hi_reg_half() const { return (data() >> reg_bits) & lower_reg_mask; } |
aoqi@0 | 287 | OprKind kind_field() const { return (OprKind)(value() & kind_mask); } |
aoqi@0 | 288 | OprSize size_field() const { return (OprSize)(value() & size_mask); } |
aoqi@0 | 289 | |
aoqi@0 | 290 | static char type_char(BasicType t); |
aoqi@0 | 291 | |
aoqi@0 | 292 | public: |
aoqi@0 | 293 | enum { |
aoqi@0 | 294 | vreg_base = ConcreteRegisterImpl::number_of_registers, |
aoqi@0 | 295 | vreg_max = (1 << data_bits) - 1 |
aoqi@0 | 296 | }; |
aoqi@0 | 297 | |
aoqi@0 | 298 | static inline LIR_Opr illegalOpr(); |
aoqi@0 | 299 | |
aoqi@0 | 300 | enum OprType { |
aoqi@0 | 301 | unknown_type = 0 << type_shift // means: not set (catch uninitialized types) |
aoqi@0 | 302 | , int_type = 1 << type_shift |
aoqi@0 | 303 | , long_type = 2 << type_shift |
aoqi@0 | 304 | , object_type = 3 << type_shift |
aoqi@0 | 305 | , address_type = 4 << type_shift |
aoqi@0 | 306 | , float_type = 5 << type_shift |
aoqi@0 | 307 | , double_type = 6 << type_shift |
aoqi@0 | 308 | , metadata_type = 7 << type_shift |
aoqi@0 | 309 | }; |
aoqi@0 | 310 | friend OprType as_OprType(BasicType t); |
aoqi@0 | 311 | friend BasicType as_BasicType(OprType t); |
aoqi@0 | 312 | |
aoqi@0 | 313 | OprType type_field_valid() const { assert(is_register() || is_stack(), "should not be called otherwise"); return (OprType)(value() & type_mask); } |
aoqi@0 | 314 | OprType type_field() const { return is_illegal() ? unknown_type : (OprType)(value() & type_mask); } |
aoqi@0 | 315 | |
aoqi@0 | 316 | static OprSize size_for(BasicType t) { |
aoqi@0 | 317 | switch (t) { |
aoqi@0 | 318 | case T_LONG: |
aoqi@0 | 319 | case T_DOUBLE: |
aoqi@0 | 320 | return double_size; |
aoqi@0 | 321 | break; |
aoqi@0 | 322 | |
aoqi@0 | 323 | case T_FLOAT: |
aoqi@0 | 324 | case T_BOOLEAN: |
aoqi@0 | 325 | case T_CHAR: |
aoqi@0 | 326 | case T_BYTE: |
aoqi@0 | 327 | case T_SHORT: |
aoqi@0 | 328 | case T_INT: |
aoqi@0 | 329 | case T_ADDRESS: |
aoqi@0 | 330 | case T_OBJECT: |
aoqi@0 | 331 | case T_ARRAY: |
aoqi@0 | 332 | case T_METADATA: |
aoqi@0 | 333 | return single_size; |
aoqi@0 | 334 | break; |
aoqi@0 | 335 | |
aoqi@0 | 336 | default: |
aoqi@0 | 337 | ShouldNotReachHere(); |
aoqi@0 | 338 | return single_size; |
aoqi@0 | 339 | } |
aoqi@0 | 340 | } |
aoqi@0 | 341 | |
aoqi@0 | 342 | |
aoqi@0 | 343 | void validate_type() const PRODUCT_RETURN; |
aoqi@0 | 344 | |
aoqi@0 | 345 | BasicType type() const { |
aoqi@0 | 346 | if (is_pointer()) { |
aoqi@0 | 347 | return pointer()->type(); |
aoqi@0 | 348 | } |
aoqi@0 | 349 | return as_BasicType(type_field()); |
aoqi@0 | 350 | } |
aoqi@0 | 351 | |
aoqi@0 | 352 | |
aoqi@0 | 353 | ValueType* value_type() const { return as_ValueType(type()); } |
aoqi@0 | 354 | |
aoqi@0 | 355 | char type_char() const { return type_char((is_pointer()) ? pointer()->type() : type()); } |
aoqi@0 | 356 | |
aoqi@0 | 357 | bool is_equal(LIR_Opr opr) const { return this == opr; } |
aoqi@0 | 358 | // checks whether types are same |
aoqi@0 | 359 | bool is_same_type(LIR_Opr opr) const { |
aoqi@0 | 360 | assert(type_field() != unknown_type && |
aoqi@0 | 361 | opr->type_field() != unknown_type, "shouldn't see unknown_type"); |
aoqi@0 | 362 | return type_field() == opr->type_field(); |
aoqi@0 | 363 | } |
aoqi@0 | 364 | bool is_same_register(LIR_Opr opr) { |
aoqi@0 | 365 | return (is_register() && opr->is_register() && |
aoqi@0 | 366 | kind_field() == opr->kind_field() && |
aoqi@0 | 367 | (value() & no_type_mask) == (opr->value() & no_type_mask)); |
aoqi@0 | 368 | } |
aoqi@0 | 369 | |
aoqi@0 | 370 | bool is_pointer() const { return check_value_mask(pointer_mask, pointer_value); } |
aoqi@0 | 371 | bool is_illegal() const { return kind_field() == illegal_value; } |
aoqi@0 | 372 | bool is_valid() const { return kind_field() != illegal_value; } |
aoqi@0 | 373 | |
aoqi@0 | 374 | bool is_register() const { return is_cpu_register() || is_fpu_register(); } |
aoqi@0 | 375 | bool is_virtual() const { return is_virtual_cpu() || is_virtual_fpu(); } |
aoqi@0 | 376 | |
aoqi@0 | 377 | bool is_constant() const { return is_pointer() && pointer()->as_constant() != NULL; } |
aoqi@0 | 378 | bool is_address() const { return is_pointer() && pointer()->as_address() != NULL; } |
aoqi@0 | 379 | |
aoqi@0 | 380 | bool is_float_kind() const { return is_pointer() ? pointer()->is_float_kind() : (kind_field() == fpu_register); } |
aoqi@0 | 381 | bool is_oop() const; |
aoqi@0 | 382 | |
aoqi@0 | 383 | // semantic for fpu- and xmm-registers: |
aoqi@0 | 384 | // * is_float and is_double return true for xmm_registers |
aoqi@0 | 385 | // (so is_single_fpu and is_single_xmm are true) |
aoqi@0 | 386 | // * So you must always check for is_???_xmm prior to is_???_fpu to |
aoqi@0 | 387 | // distinguish between fpu- and xmm-registers |
aoqi@0 | 388 | |
aoqi@0 | 389 | bool is_stack() const { validate_type(); return check_value_mask(kind_mask, stack_value); } |
aoqi@0 | 390 | bool is_single_stack() const { validate_type(); return check_value_mask(kind_mask | size_mask, stack_value | single_size); } |
aoqi@0 | 391 | bool is_double_stack() const { validate_type(); return check_value_mask(kind_mask | size_mask, stack_value | double_size); } |
aoqi@0 | 392 | |
aoqi@0 | 393 | bool is_cpu_register() const { validate_type(); return check_value_mask(kind_mask, cpu_register); } |
aoqi@0 | 394 | bool is_virtual_cpu() const { validate_type(); return check_value_mask(kind_mask | virtual_mask, cpu_register | virtual_mask); } |
aoqi@0 | 395 | bool is_fixed_cpu() const { validate_type(); return check_value_mask(kind_mask | virtual_mask, cpu_register); } |
aoqi@0 | 396 | bool is_single_cpu() const { validate_type(); return check_value_mask(kind_mask | size_mask, cpu_register | single_size); } |
aoqi@0 | 397 | bool is_double_cpu() const { validate_type(); return check_value_mask(kind_mask | size_mask, cpu_register | double_size); } |
aoqi@0 | 398 | |
aoqi@0 | 399 | bool is_fpu_register() const { validate_type(); return check_value_mask(kind_mask, fpu_register); } |
aoqi@0 | 400 | bool is_virtual_fpu() const { validate_type(); return check_value_mask(kind_mask | virtual_mask, fpu_register | virtual_mask); } |
aoqi@0 | 401 | bool is_fixed_fpu() const { validate_type(); return check_value_mask(kind_mask | virtual_mask, fpu_register); } |
aoqi@0 | 402 | bool is_single_fpu() const { validate_type(); return check_value_mask(kind_mask | size_mask, fpu_register | single_size); } |
aoqi@0 | 403 | bool is_double_fpu() const { validate_type(); return check_value_mask(kind_mask | size_mask, fpu_register | double_size); } |
aoqi@0 | 404 | |
aoqi@0 | 405 | bool is_xmm_register() const { validate_type(); return check_value_mask(kind_mask | is_xmm_mask, fpu_register | is_xmm_mask); } |
aoqi@0 | 406 | bool is_single_xmm() const { validate_type(); return check_value_mask(kind_mask | size_mask | is_xmm_mask, fpu_register | single_size | is_xmm_mask); } |
aoqi@0 | 407 | bool is_double_xmm() const { validate_type(); return check_value_mask(kind_mask | size_mask | is_xmm_mask, fpu_register | double_size | is_xmm_mask); } |
aoqi@0 | 408 | |
aoqi@0 | 409 | // fast accessor functions for special bits that do not work for pointers |
aoqi@0 | 410 | // (in this functions, the check for is_pointer() is omitted) |
aoqi@0 | 411 | bool is_single_word() const { assert(is_register() || is_stack(), "type check"); return check_value_mask(size_mask, single_size); } |
aoqi@0 | 412 | bool is_double_word() const { assert(is_register() || is_stack(), "type check"); return check_value_mask(size_mask, double_size); } |
aoqi@0 | 413 | bool is_virtual_register() const { assert(is_register(), "type check"); return check_value_mask(virtual_mask, virtual_mask); } |
aoqi@0 | 414 | bool is_oop_register() const { assert(is_register() || is_stack(), "type check"); return type_field_valid() == object_type; } |
aoqi@0 | 415 | BasicType type_register() const { assert(is_register() || is_stack(), "type check"); return as_BasicType(type_field_valid()); } |
aoqi@0 | 416 | |
aoqi@0 | 417 | bool is_last_use() const { assert(is_register(), "only works for registers"); return (value() & last_use_mask) != 0; } |
aoqi@0 | 418 | bool is_fpu_stack_offset() const { assert(is_register(), "only works for registers"); return (value() & is_fpu_stack_offset_mask) != 0; } |
aoqi@0 | 419 | LIR_Opr make_last_use() { assert(is_register(), "only works for registers"); return (LIR_Opr)(value() | last_use_mask); } |
aoqi@0 | 420 | LIR_Opr make_fpu_stack_offset() { assert(is_register(), "only works for registers"); return (LIR_Opr)(value() | is_fpu_stack_offset_mask); } |
aoqi@0 | 421 | |
aoqi@0 | 422 | |
aoqi@0 | 423 | int single_stack_ix() const { assert(is_single_stack() && !is_virtual(), "type check"); return (int)data(); } |
aoqi@0 | 424 | int double_stack_ix() const { assert(is_double_stack() && !is_virtual(), "type check"); return (int)data(); } |
aoqi@0 | 425 | RegNr cpu_regnr() const { assert(is_single_cpu() && !is_virtual(), "type check"); return (RegNr)data(); } |
aoqi@0 | 426 | RegNr cpu_regnrLo() const { assert(is_double_cpu() && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); } |
aoqi@0 | 427 | RegNr cpu_regnrHi() const { assert(is_double_cpu() && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); } |
aoqi@0 | 428 | RegNr fpu_regnr() const { assert(is_single_fpu() && !is_virtual(), "type check"); return (RegNr)data(); } |
aoqi@0 | 429 | RegNr fpu_regnrLo() const { assert(is_double_fpu() && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); } |
aoqi@0 | 430 | RegNr fpu_regnrHi() const { assert(is_double_fpu() && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); } |
aoqi@0 | 431 | RegNr xmm_regnr() const { assert(is_single_xmm() && !is_virtual(), "type check"); return (RegNr)data(); } |
aoqi@0 | 432 | RegNr xmm_regnrLo() const { assert(is_double_xmm() && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); } |
aoqi@0 | 433 | RegNr xmm_regnrHi() const { assert(is_double_xmm() && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); } |
aoqi@0 | 434 | int vreg_number() const { assert(is_virtual(), "type check"); return (RegNr)data(); } |
aoqi@0 | 435 | |
aoqi@0 | 436 | LIR_OprPtr* pointer() const { assert(is_pointer(), "type check"); return (LIR_OprPtr*)this; } |
aoqi@0 | 437 | LIR_Const* as_constant_ptr() const { return pointer()->as_constant(); } |
aoqi@0 | 438 | LIR_Address* as_address_ptr() const { return pointer()->as_address(); } |
aoqi@0 | 439 | |
aoqi@0 | 440 | Register as_register() const; |
aoqi@0 | 441 | Register as_register_lo() const; |
aoqi@0 | 442 | Register as_register_hi() const; |
aoqi@0 | 443 | |
aoqi@0 | 444 | Register as_pointer_register() { |
aoqi@0 | 445 | #ifdef _LP64 |
aoqi@0 | 446 | if (is_double_cpu()) { |
aoqi@0 | 447 | assert(as_register_lo() == as_register_hi(), "should be a single register"); |
aoqi@0 | 448 | return as_register_lo(); |
aoqi@0 | 449 | } |
aoqi@0 | 450 | #endif |
aoqi@0 | 451 | return as_register(); |
aoqi@0 | 452 | } |
aoqi@0 | 453 | |
aoqi@0 | 454 | #ifdef X86 |
aoqi@0 | 455 | XMMRegister as_xmm_float_reg() const; |
aoqi@0 | 456 | XMMRegister as_xmm_double_reg() const; |
aoqi@0 | 457 | // for compatibility with RInfo |
aoqi@0 | 458 | int fpu () const { return lo_reg_half(); } |
aoqi@0 | 459 | #endif // X86 |
aoqi@0 | 460 | #if defined(SPARC) || defined(ARM) || defined(PPC) |
aoqi@0 | 461 | FloatRegister as_float_reg () const; |
aoqi@0 | 462 | FloatRegister as_double_reg () const; |
aoqi@0 | 463 | #endif |
aoqi@1 | 464 | #ifdef MIPS64 |
aoqi@1 | 465 | FloatRegister as_float_reg () const; |
aoqi@1 | 466 | FloatRegister as_double_reg () const; |
aoqi@1 | 467 | |
aoqi@1 | 468 | FloatRegister as_fpu_lo () const; |
aoqi@1 | 469 | FloatRegister as_fpu_hi () const; |
aoqi@1 | 470 | |
aoqi@1 | 471 | #endif |
aoqi@0 | 472 | |
aoqi@0 | 473 | jint as_jint() const { return as_constant_ptr()->as_jint(); } |
aoqi@0 | 474 | jlong as_jlong() const { return as_constant_ptr()->as_jlong(); } |
aoqi@0 | 475 | jfloat as_jfloat() const { return as_constant_ptr()->as_jfloat(); } |
aoqi@0 | 476 | jdouble as_jdouble() const { return as_constant_ptr()->as_jdouble(); } |
aoqi@0 | 477 | jobject as_jobject() const { return as_constant_ptr()->as_jobject(); } |
aoqi@0 | 478 | |
aoqi@0 | 479 | void print() const PRODUCT_RETURN; |
aoqi@0 | 480 | void print(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 481 | }; |
aoqi@0 | 482 | |
aoqi@0 | 483 | |
aoqi@0 | 484 | inline LIR_OprDesc::OprType as_OprType(BasicType type) { |
aoqi@0 | 485 | switch (type) { |
aoqi@0 | 486 | case T_INT: return LIR_OprDesc::int_type; |
aoqi@0 | 487 | case T_LONG: return LIR_OprDesc::long_type; |
aoqi@0 | 488 | case T_FLOAT: return LIR_OprDesc::float_type; |
aoqi@0 | 489 | case T_DOUBLE: return LIR_OprDesc::double_type; |
aoqi@0 | 490 | case T_OBJECT: |
aoqi@0 | 491 | case T_ARRAY: return LIR_OprDesc::object_type; |
aoqi@0 | 492 | case T_ADDRESS: return LIR_OprDesc::address_type; |
aoqi@0 | 493 | case T_METADATA: return LIR_OprDesc::metadata_type; |
aoqi@0 | 494 | case T_ILLEGAL: // fall through |
aoqi@0 | 495 | default: ShouldNotReachHere(); return LIR_OprDesc::unknown_type; |
aoqi@0 | 496 | } |
aoqi@0 | 497 | } |
aoqi@0 | 498 | |
aoqi@0 | 499 | inline BasicType as_BasicType(LIR_OprDesc::OprType t) { |
aoqi@0 | 500 | switch (t) { |
aoqi@0 | 501 | case LIR_OprDesc::int_type: return T_INT; |
aoqi@0 | 502 | case LIR_OprDesc::long_type: return T_LONG; |
aoqi@0 | 503 | case LIR_OprDesc::float_type: return T_FLOAT; |
aoqi@0 | 504 | case LIR_OprDesc::double_type: return T_DOUBLE; |
aoqi@0 | 505 | case LIR_OprDesc::object_type: return T_OBJECT; |
aoqi@0 | 506 | case LIR_OprDesc::address_type: return T_ADDRESS; |
aoqi@0 | 507 | case LIR_OprDesc::metadata_type:return T_METADATA; |
aoqi@0 | 508 | case LIR_OprDesc::unknown_type: // fall through |
aoqi@0 | 509 | default: ShouldNotReachHere(); return T_ILLEGAL; |
aoqi@0 | 510 | } |
aoqi@0 | 511 | } |
aoqi@0 | 512 | |
aoqi@0 | 513 | |
aoqi@0 | 514 | // LIR_Address |
aoqi@0 | 515 | class LIR_Address: public LIR_OprPtr { |
aoqi@0 | 516 | friend class LIR_OpVisitState; |
aoqi@0 | 517 | |
aoqi@0 | 518 | public: |
aoqi@0 | 519 | // NOTE: currently these must be the log2 of the scale factor (and |
aoqi@0 | 520 | // must also be equivalent to the ScaleFactor enum in |
aoqi@0 | 521 | // assembler_i486.hpp) |
aoqi@0 | 522 | enum Scale { |
aoqi@0 | 523 | times_1 = 0, |
aoqi@0 | 524 | times_2 = 1, |
aoqi@0 | 525 | times_4 = 2, |
aoqi@0 | 526 | times_8 = 3 |
aoqi@0 | 527 | }; |
aoqi@0 | 528 | |
aoqi@0 | 529 | private: |
aoqi@0 | 530 | LIR_Opr _base; |
aoqi@0 | 531 | LIR_Opr _index; |
aoqi@0 | 532 | Scale _scale; |
aoqi@0 | 533 | intx _disp; |
aoqi@0 | 534 | BasicType _type; |
aoqi@0 | 535 | |
aoqi@0 | 536 | public: |
aoqi@0 | 537 | LIR_Address(LIR_Opr base, LIR_Opr index, BasicType type): |
aoqi@0 | 538 | _base(base) |
aoqi@0 | 539 | , _index(index) |
aoqi@0 | 540 | , _scale(times_1) |
aoqi@0 | 541 | , _type(type) |
aoqi@0 | 542 | , _disp(0) { verify(); } |
aoqi@0 | 543 | |
aoqi@1 | 544 | #ifndef MIPS64 |
aoqi@0 | 545 | LIR_Address(LIR_Opr base, intx disp, BasicType type): |
aoqi@1 | 546 | #else |
aoqi@1 | 547 | LIR_Address(LIR_Opr base, int disp, BasicType type): |
aoqi@1 | 548 | #endif |
aoqi@0 | 549 | _base(base) |
aoqi@0 | 550 | , _index(LIR_OprDesc::illegalOpr()) |
aoqi@0 | 551 | , _scale(times_1) |
aoqi@0 | 552 | , _type(type) |
aoqi@0 | 553 | , _disp(disp) { verify(); } |
aoqi@0 | 554 | |
aoqi@0 | 555 | LIR_Address(LIR_Opr base, BasicType type): |
aoqi@0 | 556 | _base(base) |
aoqi@0 | 557 | , _index(LIR_OprDesc::illegalOpr()) |
aoqi@0 | 558 | , _scale(times_1) |
aoqi@0 | 559 | , _type(type) |
aoqi@0 | 560 | , _disp(0) { verify(); } |
aoqi@0 | 561 | |
aoqi@0 | 562 | #if defined(X86) || defined(ARM) |
aoqi@0 | 563 | LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type): |
aoqi@0 | 564 | _base(base) |
aoqi@0 | 565 | , _index(index) |
aoqi@0 | 566 | , _scale(scale) |
aoqi@0 | 567 | , _type(type) |
aoqi@0 | 568 | , _disp(disp) { verify(); } |
aoqi@0 | 569 | #endif // X86 || ARM |
aoqi@0 | 570 | |
aoqi@0 | 571 | LIR_Opr base() const { return _base; } |
aoqi@0 | 572 | LIR_Opr index() const { return _index; } |
aoqi@0 | 573 | Scale scale() const { return _scale; } |
aoqi@0 | 574 | intx disp() const { return _disp; } |
aoqi@0 | 575 | |
aoqi@0 | 576 | bool equals(LIR_Address* other) const { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); } |
aoqi@0 | 577 | |
aoqi@0 | 578 | virtual LIR_Address* as_address() { return this; } |
aoqi@0 | 579 | virtual BasicType type() const { return _type; } |
aoqi@0 | 580 | virtual void print_value_on(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 581 | |
aoqi@0 | 582 | void verify() const PRODUCT_RETURN; |
aoqi@0 | 583 | |
aoqi@0 | 584 | static Scale scale(BasicType type); |
aoqi@0 | 585 | }; |
aoqi@0 | 586 | |
aoqi@0 | 587 | |
aoqi@0 | 588 | // operand factory |
aoqi@0 | 589 | class LIR_OprFact: public AllStatic { |
aoqi@0 | 590 | public: |
aoqi@0 | 591 | |
aoqi@0 | 592 | static LIR_Opr illegalOpr; |
aoqi@0 | 593 | |
aoqi@0 | 594 | static LIR_Opr single_cpu(int reg) { |
aoqi@0 | 595 | return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 596 | LIR_OprDesc::int_type | |
aoqi@0 | 597 | LIR_OprDesc::cpu_register | |
aoqi@0 | 598 | LIR_OprDesc::single_size); |
aoqi@0 | 599 | } |
aoqi@0 | 600 | static LIR_Opr single_cpu_oop(int reg) { |
aoqi@0 | 601 | return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 602 | LIR_OprDesc::object_type | |
aoqi@0 | 603 | LIR_OprDesc::cpu_register | |
aoqi@0 | 604 | LIR_OprDesc::single_size); |
aoqi@0 | 605 | } |
aoqi@0 | 606 | static LIR_Opr single_cpu_address(int reg) { |
aoqi@0 | 607 | return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 608 | LIR_OprDesc::address_type | |
aoqi@0 | 609 | LIR_OprDesc::cpu_register | |
aoqi@0 | 610 | LIR_OprDesc::single_size); |
aoqi@0 | 611 | } |
aoqi@0 | 612 | static LIR_Opr single_cpu_metadata(int reg) { |
aoqi@0 | 613 | return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 614 | LIR_OprDesc::metadata_type | |
aoqi@0 | 615 | LIR_OprDesc::cpu_register | |
aoqi@0 | 616 | LIR_OprDesc::single_size); |
aoqi@0 | 617 | } |
aoqi@0 | 618 | static LIR_Opr double_cpu(int reg1, int reg2) { |
aoqi@0 | 619 | LP64_ONLY(assert(reg1 == reg2, "must be identical")); |
aoqi@0 | 620 | return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 621 | (reg2 << LIR_OprDesc::reg2_shift) | |
aoqi@0 | 622 | LIR_OprDesc::long_type | |
aoqi@0 | 623 | LIR_OprDesc::cpu_register | |
aoqi@0 | 624 | LIR_OprDesc::double_size); |
aoqi@0 | 625 | } |
aoqi@0 | 626 | |
aoqi@0 | 627 | static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 628 | LIR_OprDesc::float_type | |
aoqi@0 | 629 | LIR_OprDesc::fpu_register | |
aoqi@0 | 630 | LIR_OprDesc::single_size); } |
aoqi@0 | 631 | #if defined(ARM) |
aoqi@0 | 632 | static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); } |
aoqi@0 | 633 | static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); } |
aoqi@0 | 634 | static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); } |
aoqi@0 | 635 | #endif |
aoqi@0 | 636 | #ifdef SPARC |
aoqi@0 | 637 | static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 638 | (reg2 << LIR_OprDesc::reg2_shift) | |
aoqi@0 | 639 | LIR_OprDesc::double_type | |
aoqi@0 | 640 | LIR_OprDesc::fpu_register | |
aoqi@0 | 641 | LIR_OprDesc::double_size); } |
aoqi@0 | 642 | #endif |
aoqi@1 | 643 | #ifdef MIPS64 |
aoqi@1 | 644 | static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@1 | 645 | (reg << LIR_OprDesc::reg2_shift) | |
aoqi@1 | 646 | LIR_OprDesc::double_type | |
aoqi@1 | 647 | LIR_OprDesc::fpu_register | |
aoqi@1 | 648 | LIR_OprDesc::double_size); } |
aoqi@1 | 649 | #endif |
aoqi@0 | 650 | #ifdef X86 |
aoqi@0 | 651 | static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 652 | (reg << LIR_OprDesc::reg2_shift) | |
aoqi@0 | 653 | LIR_OprDesc::double_type | |
aoqi@0 | 654 | LIR_OprDesc::fpu_register | |
aoqi@0 | 655 | LIR_OprDesc::double_size); } |
aoqi@0 | 656 | |
aoqi@0 | 657 | static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 658 | LIR_OprDesc::float_type | |
aoqi@0 | 659 | LIR_OprDesc::fpu_register | |
aoqi@0 | 660 | LIR_OprDesc::single_size | |
aoqi@0 | 661 | LIR_OprDesc::is_xmm_mask); } |
aoqi@0 | 662 | static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 663 | (reg << LIR_OprDesc::reg2_shift) | |
aoqi@0 | 664 | LIR_OprDesc::double_type | |
aoqi@0 | 665 | LIR_OprDesc::fpu_register | |
aoqi@0 | 666 | LIR_OprDesc::double_size | |
aoqi@0 | 667 | LIR_OprDesc::is_xmm_mask); } |
aoqi@0 | 668 | #endif // X86 |
aoqi@0 | 669 | #ifdef PPC |
aoqi@0 | 670 | static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 671 | (reg << LIR_OprDesc::reg2_shift) | |
aoqi@0 | 672 | LIR_OprDesc::double_type | |
aoqi@0 | 673 | LIR_OprDesc::fpu_register | |
aoqi@0 | 674 | LIR_OprDesc::double_size); } |
aoqi@0 | 675 | static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 676 | LIR_OprDesc::float_type | |
aoqi@0 | 677 | LIR_OprDesc::cpu_register | |
aoqi@0 | 678 | LIR_OprDesc::single_size); } |
aoqi@0 | 679 | static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) | |
aoqi@0 | 680 | (reg1 << LIR_OprDesc::reg2_shift) | |
aoqi@0 | 681 | LIR_OprDesc::double_type | |
aoqi@0 | 682 | LIR_OprDesc::cpu_register | |
aoqi@0 | 683 | LIR_OprDesc::double_size); } |
aoqi@0 | 684 | #endif // PPC |
aoqi@0 | 685 | |
aoqi@0 | 686 | static LIR_Opr virtual_register(int index, BasicType type) { |
aoqi@0 | 687 | LIR_Opr res; |
aoqi@0 | 688 | switch (type) { |
aoqi@0 | 689 | case T_OBJECT: // fall through |
aoqi@0 | 690 | case T_ARRAY: |
aoqi@0 | 691 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 692 | LIR_OprDesc::object_type | |
aoqi@0 | 693 | LIR_OprDesc::cpu_register | |
aoqi@0 | 694 | LIR_OprDesc::single_size | |
aoqi@0 | 695 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 696 | break; |
aoqi@0 | 697 | |
aoqi@0 | 698 | case T_METADATA: |
aoqi@0 | 699 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 700 | LIR_OprDesc::metadata_type| |
aoqi@0 | 701 | LIR_OprDesc::cpu_register | |
aoqi@0 | 702 | LIR_OprDesc::single_size | |
aoqi@0 | 703 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 704 | break; |
aoqi@0 | 705 | |
aoqi@0 | 706 | case T_INT: |
aoqi@0 | 707 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 708 | LIR_OprDesc::int_type | |
aoqi@0 | 709 | LIR_OprDesc::cpu_register | |
aoqi@0 | 710 | LIR_OprDesc::single_size | |
aoqi@0 | 711 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 712 | break; |
aoqi@0 | 713 | |
aoqi@0 | 714 | case T_ADDRESS: |
aoqi@0 | 715 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 716 | LIR_OprDesc::address_type | |
aoqi@0 | 717 | LIR_OprDesc::cpu_register | |
aoqi@0 | 718 | LIR_OprDesc::single_size | |
aoqi@0 | 719 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 720 | break; |
aoqi@0 | 721 | |
aoqi@0 | 722 | case T_LONG: |
aoqi@0 | 723 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 724 | LIR_OprDesc::long_type | |
aoqi@0 | 725 | LIR_OprDesc::cpu_register | |
aoqi@0 | 726 | LIR_OprDesc::double_size | |
aoqi@0 | 727 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 728 | break; |
aoqi@0 | 729 | |
aoqi@0 | 730 | #ifdef __SOFTFP__ |
aoqi@0 | 731 | case T_FLOAT: |
aoqi@0 | 732 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 733 | LIR_OprDesc::float_type | |
aoqi@0 | 734 | LIR_OprDesc::cpu_register | |
aoqi@0 | 735 | LIR_OprDesc::single_size | |
aoqi@0 | 736 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 737 | break; |
aoqi@0 | 738 | case T_DOUBLE: |
aoqi@0 | 739 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 740 | LIR_OprDesc::double_type | |
aoqi@0 | 741 | LIR_OprDesc::cpu_register | |
aoqi@0 | 742 | LIR_OprDesc::double_size | |
aoqi@0 | 743 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 744 | break; |
aoqi@0 | 745 | #else // __SOFTFP__ |
aoqi@0 | 746 | case T_FLOAT: |
aoqi@0 | 747 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 748 | LIR_OprDesc::float_type | |
aoqi@0 | 749 | LIR_OprDesc::fpu_register | |
aoqi@0 | 750 | LIR_OprDesc::single_size | |
aoqi@0 | 751 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 752 | break; |
aoqi@0 | 753 | |
aoqi@0 | 754 | case |
aoqi@0 | 755 | T_DOUBLE: res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 756 | LIR_OprDesc::double_type | |
aoqi@0 | 757 | LIR_OprDesc::fpu_register | |
aoqi@0 | 758 | LIR_OprDesc::double_size | |
aoqi@0 | 759 | LIR_OprDesc::virtual_mask); |
aoqi@0 | 760 | break; |
aoqi@0 | 761 | #endif // __SOFTFP__ |
aoqi@0 | 762 | default: ShouldNotReachHere(); res = illegalOpr; |
aoqi@0 | 763 | } |
aoqi@0 | 764 | |
aoqi@0 | 765 | #ifdef ASSERT |
aoqi@0 | 766 | res->validate_type(); |
aoqi@0 | 767 | assert(res->vreg_number() == index, "conversion check"); |
aoqi@0 | 768 | assert(index >= LIR_OprDesc::vreg_base, "must start at vreg_base"); |
aoqi@0 | 769 | assert(index <= (max_jint >> LIR_OprDesc::data_shift), "index is too big"); |
aoqi@0 | 770 | |
aoqi@0 | 771 | // old-style calculation; check if old and new method are equal |
aoqi@0 | 772 | LIR_OprDesc::OprType t = as_OprType(type); |
aoqi@0 | 773 | #ifdef __SOFTFP__ |
aoqi@0 | 774 | LIR_Opr old_res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 775 | t | |
aoqi@0 | 776 | LIR_OprDesc::cpu_register | |
aoqi@0 | 777 | LIR_OprDesc::size_for(type) | LIR_OprDesc::virtual_mask); |
aoqi@0 | 778 | #else // __SOFTFP__ |
aoqi@0 | 779 | LIR_Opr old_res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | t | |
aoqi@0 | 780 | ((type == T_FLOAT || type == T_DOUBLE) ? LIR_OprDesc::fpu_register : LIR_OprDesc::cpu_register) | |
aoqi@0 | 781 | LIR_OprDesc::size_for(type) | LIR_OprDesc::virtual_mask); |
aoqi@0 | 782 | assert(res == old_res, "old and new method not equal"); |
aoqi@0 | 783 | #endif // __SOFTFP__ |
aoqi@0 | 784 | #endif // ASSERT |
aoqi@0 | 785 | |
aoqi@0 | 786 | return res; |
aoqi@0 | 787 | } |
aoqi@0 | 788 | |
aoqi@0 | 789 | // 'index' is computed by FrameMap::local_stack_pos(index); do not use other parameters as |
aoqi@0 | 790 | // the index is platform independent; a double stack useing indeces 2 and 3 has always |
aoqi@0 | 791 | // index 2. |
aoqi@0 | 792 | static LIR_Opr stack(int index, BasicType type) { |
aoqi@0 | 793 | LIR_Opr res; |
aoqi@0 | 794 | switch (type) { |
aoqi@0 | 795 | case T_OBJECT: // fall through |
aoqi@0 | 796 | case T_ARRAY: |
aoqi@0 | 797 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 798 | LIR_OprDesc::object_type | |
aoqi@0 | 799 | LIR_OprDesc::stack_value | |
aoqi@0 | 800 | LIR_OprDesc::single_size); |
aoqi@0 | 801 | break; |
aoqi@0 | 802 | |
aoqi@0 | 803 | case T_METADATA: |
aoqi@0 | 804 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 805 | LIR_OprDesc::metadata_type | |
aoqi@0 | 806 | LIR_OprDesc::stack_value | |
aoqi@0 | 807 | LIR_OprDesc::single_size); |
aoqi@0 | 808 | break; |
aoqi@0 | 809 | case T_INT: |
aoqi@0 | 810 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 811 | LIR_OprDesc::int_type | |
aoqi@0 | 812 | LIR_OprDesc::stack_value | |
aoqi@0 | 813 | LIR_OprDesc::single_size); |
aoqi@0 | 814 | break; |
aoqi@0 | 815 | |
aoqi@0 | 816 | case T_ADDRESS: |
aoqi@0 | 817 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 818 | LIR_OprDesc::address_type | |
aoqi@0 | 819 | LIR_OprDesc::stack_value | |
aoqi@0 | 820 | LIR_OprDesc::single_size); |
aoqi@0 | 821 | break; |
aoqi@0 | 822 | |
aoqi@0 | 823 | case T_LONG: |
aoqi@0 | 824 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 825 | LIR_OprDesc::long_type | |
aoqi@0 | 826 | LIR_OprDesc::stack_value | |
aoqi@0 | 827 | LIR_OprDesc::double_size); |
aoqi@0 | 828 | break; |
aoqi@0 | 829 | |
aoqi@0 | 830 | case T_FLOAT: |
aoqi@0 | 831 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 832 | LIR_OprDesc::float_type | |
aoqi@0 | 833 | LIR_OprDesc::stack_value | |
aoqi@0 | 834 | LIR_OprDesc::single_size); |
aoqi@0 | 835 | break; |
aoqi@0 | 836 | case T_DOUBLE: |
aoqi@0 | 837 | res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 838 | LIR_OprDesc::double_type | |
aoqi@0 | 839 | LIR_OprDesc::stack_value | |
aoqi@0 | 840 | LIR_OprDesc::double_size); |
aoqi@0 | 841 | break; |
aoqi@0 | 842 | |
aoqi@0 | 843 | default: ShouldNotReachHere(); res = illegalOpr; |
aoqi@0 | 844 | } |
aoqi@0 | 845 | |
aoqi@0 | 846 | #ifdef ASSERT |
aoqi@0 | 847 | assert(index >= 0, "index must be positive"); |
aoqi@0 | 848 | assert(index <= (max_jint >> LIR_OprDesc::data_shift), "index is too big"); |
aoqi@0 | 849 | |
aoqi@0 | 850 | LIR_Opr old_res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
aoqi@0 | 851 | LIR_OprDesc::stack_value | |
aoqi@0 | 852 | as_OprType(type) | |
aoqi@0 | 853 | LIR_OprDesc::size_for(type)); |
aoqi@0 | 854 | assert(res == old_res, "old and new method not equal"); |
aoqi@0 | 855 | #endif |
aoqi@0 | 856 | |
aoqi@0 | 857 | return res; |
aoqi@0 | 858 | } |
aoqi@0 | 859 | |
aoqi@0 | 860 | static LIR_Opr intConst(jint i) { return (LIR_Opr)(new LIR_Const(i)); } |
aoqi@0 | 861 | static LIR_Opr longConst(jlong l) { return (LIR_Opr)(new LIR_Const(l)); } |
aoqi@0 | 862 | static LIR_Opr floatConst(jfloat f) { return (LIR_Opr)(new LIR_Const(f)); } |
aoqi@0 | 863 | static LIR_Opr doubleConst(jdouble d) { return (LIR_Opr)(new LIR_Const(d)); } |
aoqi@0 | 864 | static LIR_Opr oopConst(jobject o) { return (LIR_Opr)(new LIR_Const(o)); } |
aoqi@0 | 865 | static LIR_Opr address(LIR_Address* a) { return (LIR_Opr)a; } |
aoqi@0 | 866 | static LIR_Opr intptrConst(void* p) { return (LIR_Opr)(new LIR_Const(p)); } |
aoqi@0 | 867 | static LIR_Opr intptrConst(intptr_t v) { return (LIR_Opr)(new LIR_Const((void*)v)); } |
aoqi@0 | 868 | static LIR_Opr illegal() { return (LIR_Opr)-1; } |
aoqi@0 | 869 | static LIR_Opr addressConst(jint i) { return (LIR_Opr)(new LIR_Const(i, true)); } |
aoqi@0 | 870 | static LIR_Opr metadataConst(Metadata* m) { return (LIR_Opr)(new LIR_Const(m)); } |
aoqi@0 | 871 | |
aoqi@0 | 872 | static LIR_Opr value_type(ValueType* type); |
aoqi@0 | 873 | static LIR_Opr dummy_value_type(ValueType* type); |
aoqi@0 | 874 | }; |
aoqi@0 | 875 | |
aoqi@0 | 876 | |
aoqi@0 | 877 | //------------------------------------------------------------------------------- |
aoqi@0 | 878 | // LIR Instructions |
aoqi@0 | 879 | //------------------------------------------------------------------------------- |
aoqi@0 | 880 | // |
aoqi@0 | 881 | // Note: |
aoqi@0 | 882 | // - every instruction has a result operand |
aoqi@0 | 883 | // - every instruction has an CodeEmitInfo operand (can be revisited later) |
aoqi@0 | 884 | // - every instruction has a LIR_OpCode operand |
aoqi@0 | 885 | // - LIR_OpN, means an instruction that has N input operands |
aoqi@0 | 886 | // |
aoqi@0 | 887 | // class hierarchy: |
aoqi@0 | 888 | // |
aoqi@0 | 889 | class LIR_Op; |
aoqi@0 | 890 | class LIR_Op0; |
aoqi@0 | 891 | class LIR_OpLabel; |
aoqi@0 | 892 | class LIR_Op1; |
aoqi@0 | 893 | class LIR_OpBranch; |
aoqi@0 | 894 | class LIR_OpConvert; |
aoqi@0 | 895 | class LIR_OpAllocObj; |
aoqi@0 | 896 | class LIR_OpRoundFP; |
aoqi@0 | 897 | class LIR_Op2; |
aoqi@0 | 898 | class LIR_OpDelay; |
aoqi@0 | 899 | class LIR_Op3; |
aoqi@0 | 900 | class LIR_OpAllocArray; |
aoqi@0 | 901 | class LIR_OpCall; |
aoqi@0 | 902 | class LIR_OpJavaCall; |
aoqi@0 | 903 | class LIR_OpRTCall; |
aoqi@0 | 904 | class LIR_OpArrayCopy; |
aoqi@0 | 905 | class LIR_OpUpdateCRC32; |
aoqi@0 | 906 | class LIR_OpLock; |
aoqi@0 | 907 | class LIR_OpTypeCheck; |
aoqi@0 | 908 | class LIR_OpCompareAndSwap; |
aoqi@0 | 909 | class LIR_OpProfileCall; |
aoqi@0 | 910 | class LIR_OpProfileType; |
aoqi@0 | 911 | #ifdef ASSERT |
aoqi@0 | 912 | class LIR_OpAssert; |
aoqi@0 | 913 | #endif |
aoqi@0 | 914 | |
aoqi@0 | 915 | // LIR operation codes |
aoqi@0 | 916 | enum LIR_Code { |
aoqi@0 | 917 | lir_none |
aoqi@0 | 918 | , begin_op0 |
aoqi@0 | 919 | , lir_word_align |
aoqi@0 | 920 | , lir_label |
aoqi@0 | 921 | , lir_nop |
aoqi@0 | 922 | , lir_backwardbranch_target |
aoqi@0 | 923 | , lir_std_entry |
aoqi@0 | 924 | , lir_osr_entry |
aoqi@0 | 925 | , lir_build_frame |
aoqi@0 | 926 | , lir_fpop_raw |
aoqi@0 | 927 | , lir_24bit_FPU |
aoqi@0 | 928 | , lir_reset_FPU |
aoqi@0 | 929 | , lir_breakpoint |
aoqi@0 | 930 | , lir_rtcall |
aoqi@0 | 931 | , lir_membar |
aoqi@0 | 932 | , lir_membar_acquire |
aoqi@0 | 933 | , lir_membar_release |
aoqi@0 | 934 | , lir_membar_loadload |
aoqi@0 | 935 | , lir_membar_storestore |
aoqi@0 | 936 | , lir_membar_loadstore |
aoqi@0 | 937 | , lir_membar_storeload |
aoqi@0 | 938 | , lir_get_thread |
aoqi@0 | 939 | , end_op0 |
aoqi@0 | 940 | , begin_op1 |
aoqi@0 | 941 | , lir_fxch |
aoqi@0 | 942 | , lir_fld |
aoqi@0 | 943 | , lir_ffree |
aoqi@0 | 944 | , lir_push |
aoqi@0 | 945 | , lir_pop |
aoqi@0 | 946 | , lir_null_check |
aoqi@0 | 947 | , lir_return |
aoqi@0 | 948 | , lir_leal |
aoqi@0 | 949 | , lir_neg |
aoqi@1 | 950 | #ifndef MIPS64 |
aoqi@0 | 951 | , lir_branch |
aoqi@0 | 952 | , lir_cond_float_branch |
aoqi@1 | 953 | #endif |
aoqi@0 | 954 | , lir_move |
aoqi@0 | 955 | , lir_prefetchr |
aoqi@0 | 956 | , lir_prefetchw |
aoqi@0 | 957 | , lir_convert |
aoqi@0 | 958 | , lir_alloc_object |
aoqi@0 | 959 | , lir_monaddr |
aoqi@0 | 960 | , lir_roundfp |
aoqi@0 | 961 | , lir_safepoint |
aoqi@0 | 962 | , lir_pack64 |
aoqi@0 | 963 | , lir_unpack64 |
aoqi@0 | 964 | , lir_unwind |
aoqi@0 | 965 | , end_op1 |
aoqi@0 | 966 | , begin_op2 |
aoqi@1 | 967 | #ifdef MIPS64 |
aoqi@1 | 968 | , lir_branch |
aoqi@1 | 969 | , lir_cond_float_branch |
aoqi@1 | 970 | , lir_null_check_for_branch |
aoqi@1 | 971 | #else |
aoqi@0 | 972 | , lir_cmp |
aoqi@1 | 973 | #endif |
aoqi@0 | 974 | , lir_cmp_l2i |
aoqi@0 | 975 | , lir_ucmp_fd2i |
aoqi@0 | 976 | , lir_cmp_fd2i |
aoqi@0 | 977 | , lir_cmove |
aoqi@0 | 978 | , lir_add |
aoqi@0 | 979 | , lir_sub |
aoqi@0 | 980 | , lir_mul |
aoqi@0 | 981 | , lir_mul_strictfp |
aoqi@0 | 982 | , lir_div |
aoqi@0 | 983 | , lir_div_strictfp |
aoqi@0 | 984 | , lir_rem |
aoqi@0 | 985 | , lir_sqrt |
aoqi@0 | 986 | , lir_abs |
aoqi@0 | 987 | , lir_sin |
aoqi@0 | 988 | , lir_cos |
aoqi@0 | 989 | , lir_tan |
aoqi@0 | 990 | , lir_log |
aoqi@0 | 991 | , lir_log10 |
aoqi@0 | 992 | , lir_exp |
aoqi@0 | 993 | , lir_pow |
aoqi@0 | 994 | , lir_logic_and |
aoqi@0 | 995 | , lir_logic_or |
aoqi@0 | 996 | , lir_logic_xor |
aoqi@0 | 997 | , lir_shl |
aoqi@0 | 998 | , lir_shr |
aoqi@0 | 999 | , lir_ushr |
aoqi@0 | 1000 | , lir_alloc_array |
aoqi@0 | 1001 | , lir_throw |
aoqi@0 | 1002 | , lir_compare_to |
aoqi@0 | 1003 | , lir_xadd |
aoqi@0 | 1004 | , lir_xchg |
aoqi@0 | 1005 | , end_op2 |
aoqi@0 | 1006 | , begin_op3 |
aoqi@1 | 1007 | #ifdef MIPS64 |
aoqi@1 | 1008 | , lir_frem |
aoqi@1 | 1009 | #endif |
aoqi@0 | 1010 | , lir_idiv |
aoqi@0 | 1011 | , lir_irem |
aoqi@0 | 1012 | , end_op3 |
aoqi@0 | 1013 | , begin_opJavaCall |
aoqi@0 | 1014 | , lir_static_call |
aoqi@0 | 1015 | , lir_optvirtual_call |
aoqi@0 | 1016 | , lir_icvirtual_call |
aoqi@0 | 1017 | , lir_virtual_call |
aoqi@0 | 1018 | , lir_dynamic_call |
aoqi@0 | 1019 | , end_opJavaCall |
aoqi@0 | 1020 | , begin_opArrayCopy |
aoqi@0 | 1021 | , lir_arraycopy |
aoqi@0 | 1022 | , end_opArrayCopy |
aoqi@0 | 1023 | , begin_opUpdateCRC32 |
aoqi@0 | 1024 | , lir_updatecrc32 |
aoqi@0 | 1025 | , end_opUpdateCRC32 |
aoqi@0 | 1026 | , begin_opLock |
aoqi@0 | 1027 | , lir_lock |
aoqi@0 | 1028 | , lir_unlock |
aoqi@0 | 1029 | , end_opLock |
aoqi@0 | 1030 | , begin_delay_slot |
aoqi@0 | 1031 | , lir_delay_slot |
aoqi@0 | 1032 | , end_delay_slot |
aoqi@0 | 1033 | , begin_opTypeCheck |
aoqi@0 | 1034 | , lir_instanceof |
aoqi@0 | 1035 | , lir_checkcast |
aoqi@0 | 1036 | , lir_store_check |
aoqi@0 | 1037 | , end_opTypeCheck |
aoqi@0 | 1038 | , begin_opCompareAndSwap |
aoqi@0 | 1039 | , lir_cas_long |
aoqi@0 | 1040 | , lir_cas_obj |
aoqi@0 | 1041 | , lir_cas_int |
aoqi@0 | 1042 | , end_opCompareAndSwap |
aoqi@0 | 1043 | , begin_opMDOProfile |
aoqi@0 | 1044 | , lir_profile_call |
aoqi@0 | 1045 | , lir_profile_type |
aoqi@0 | 1046 | , end_opMDOProfile |
aoqi@0 | 1047 | , begin_opAssert |
aoqi@0 | 1048 | , lir_assert |
aoqi@0 | 1049 | , end_opAssert |
aoqi@0 | 1050 | }; |
aoqi@0 | 1051 | |
aoqi@0 | 1052 | |
aoqi@0 | 1053 | enum LIR_Condition { |
aoqi@0 | 1054 | lir_cond_equal |
aoqi@0 | 1055 | , lir_cond_notEqual |
aoqi@0 | 1056 | , lir_cond_less |
aoqi@0 | 1057 | , lir_cond_lessEqual |
aoqi@0 | 1058 | , lir_cond_greaterEqual |
aoqi@0 | 1059 | , lir_cond_greater |
aoqi@0 | 1060 | , lir_cond_belowEqual |
aoqi@0 | 1061 | , lir_cond_aboveEqual |
aoqi@0 | 1062 | , lir_cond_always |
aoqi@0 | 1063 | , lir_cond_unknown = -1 |
aoqi@0 | 1064 | }; |
aoqi@0 | 1065 | |
aoqi@0 | 1066 | |
aoqi@0 | 1067 | enum LIR_PatchCode { |
aoqi@0 | 1068 | lir_patch_none, |
aoqi@0 | 1069 | lir_patch_low, |
aoqi@0 | 1070 | lir_patch_high, |
aoqi@0 | 1071 | lir_patch_normal |
aoqi@0 | 1072 | }; |
aoqi@0 | 1073 | |
aoqi@0 | 1074 | |
aoqi@0 | 1075 | enum LIR_MoveKind { |
aoqi@0 | 1076 | lir_move_normal, |
aoqi@0 | 1077 | lir_move_volatile, |
aoqi@0 | 1078 | lir_move_unaligned, |
aoqi@0 | 1079 | lir_move_wide, |
aoqi@0 | 1080 | lir_move_max_flag |
aoqi@0 | 1081 | }; |
aoqi@0 | 1082 | |
aoqi@0 | 1083 | |
aoqi@0 | 1084 | // -------------------------------------------------- |
aoqi@0 | 1085 | // LIR_Op |
aoqi@0 | 1086 | // -------------------------------------------------- |
aoqi@0 | 1087 | class LIR_Op: public CompilationResourceObj { |
aoqi@0 | 1088 | friend class LIR_OpVisitState; |
aoqi@0 | 1089 | |
aoqi@0 | 1090 | #ifdef ASSERT |
aoqi@0 | 1091 | private: |
aoqi@0 | 1092 | const char * _file; |
aoqi@0 | 1093 | int _line; |
aoqi@0 | 1094 | #endif |
aoqi@0 | 1095 | |
aoqi@0 | 1096 | protected: |
aoqi@0 | 1097 | LIR_Opr _result; |
aoqi@0 | 1098 | unsigned short _code; |
aoqi@0 | 1099 | unsigned short _flags; |
aoqi@0 | 1100 | CodeEmitInfo* _info; |
aoqi@0 | 1101 | int _id; // value id for register allocation |
aoqi@0 | 1102 | int _fpu_pop_count; |
aoqi@0 | 1103 | Instruction* _source; // for debugging |
aoqi@0 | 1104 | |
aoqi@0 | 1105 | static void print_condition(outputStream* out, LIR_Condition cond) PRODUCT_RETURN; |
aoqi@0 | 1106 | |
aoqi@0 | 1107 | protected: |
aoqi@0 | 1108 | static bool is_in_range(LIR_Code test, LIR_Code start, LIR_Code end) { return start < test && test < end; } |
aoqi@0 | 1109 | |
aoqi@0 | 1110 | public: |
aoqi@0 | 1111 | LIR_Op() |
aoqi@0 | 1112 | : _result(LIR_OprFact::illegalOpr) |
aoqi@0 | 1113 | , _code(lir_none) |
aoqi@0 | 1114 | , _flags(0) |
aoqi@0 | 1115 | , _info(NULL) |
aoqi@0 | 1116 | #ifdef ASSERT |
aoqi@0 | 1117 | , _file(NULL) |
aoqi@0 | 1118 | , _line(0) |
aoqi@0 | 1119 | #endif |
aoqi@0 | 1120 | , _fpu_pop_count(0) |
aoqi@0 | 1121 | , _source(NULL) |
aoqi@0 | 1122 | , _id(-1) {} |
aoqi@0 | 1123 | |
aoqi@0 | 1124 | LIR_Op(LIR_Code code, LIR_Opr result, CodeEmitInfo* info) |
aoqi@0 | 1125 | : _result(result) |
aoqi@0 | 1126 | , _code(code) |
aoqi@0 | 1127 | , _flags(0) |
aoqi@0 | 1128 | , _info(info) |
aoqi@0 | 1129 | #ifdef ASSERT |
aoqi@0 | 1130 | , _file(NULL) |
aoqi@0 | 1131 | , _line(0) |
aoqi@0 | 1132 | #endif |
aoqi@0 | 1133 | , _fpu_pop_count(0) |
aoqi@0 | 1134 | , _source(NULL) |
aoqi@0 | 1135 | , _id(-1) {} |
aoqi@0 | 1136 | |
aoqi@0 | 1137 | CodeEmitInfo* info() const { return _info; } |
aoqi@0 | 1138 | LIR_Code code() const { return (LIR_Code)_code; } |
aoqi@0 | 1139 | LIR_Opr result_opr() const { return _result; } |
aoqi@0 | 1140 | void set_result_opr(LIR_Opr opr) { _result = opr; } |
aoqi@0 | 1141 | |
aoqi@0 | 1142 | #ifdef ASSERT |
aoqi@0 | 1143 | void set_file_and_line(const char * file, int line) { |
aoqi@0 | 1144 | _file = file; |
aoqi@0 | 1145 | _line = line; |
aoqi@0 | 1146 | } |
aoqi@0 | 1147 | #endif |
aoqi@0 | 1148 | |
aoqi@0 | 1149 | virtual const char * name() const PRODUCT_RETURN0; |
aoqi@0 | 1150 | |
aoqi@0 | 1151 | int id() const { return _id; } |
aoqi@0 | 1152 | void set_id(int id) { _id = id; } |
aoqi@0 | 1153 | |
aoqi@0 | 1154 | // FPU stack simulation helpers -- only used on Intel |
aoqi@0 | 1155 | void set_fpu_pop_count(int count) { assert(count >= 0 && count <= 1, "currently only 0 and 1 are valid"); _fpu_pop_count = count; } |
aoqi@0 | 1156 | int fpu_pop_count() const { return _fpu_pop_count; } |
aoqi@0 | 1157 | bool pop_fpu_stack() { return _fpu_pop_count > 0; } |
aoqi@0 | 1158 | |
aoqi@0 | 1159 | Instruction* source() const { return _source; } |
aoqi@0 | 1160 | void set_source(Instruction* ins) { _source = ins; } |
aoqi@0 | 1161 | |
aoqi@0 | 1162 | virtual void emit_code(LIR_Assembler* masm) = 0; |
aoqi@0 | 1163 | virtual void print_instr(outputStream* out) const = 0; |
aoqi@0 | 1164 | virtual void print_on(outputStream* st) const PRODUCT_RETURN; |
aoqi@0 | 1165 | |
aoqi@0 | 1166 | virtual bool is_patching() { return false; } |
aoqi@0 | 1167 | virtual LIR_OpCall* as_OpCall() { return NULL; } |
aoqi@0 | 1168 | virtual LIR_OpJavaCall* as_OpJavaCall() { return NULL; } |
aoqi@0 | 1169 | virtual LIR_OpLabel* as_OpLabel() { return NULL; } |
aoqi@0 | 1170 | virtual LIR_OpDelay* as_OpDelay() { return NULL; } |
aoqi@0 | 1171 | virtual LIR_OpLock* as_OpLock() { return NULL; } |
aoqi@0 | 1172 | virtual LIR_OpAllocArray* as_OpAllocArray() { return NULL; } |
aoqi@0 | 1173 | virtual LIR_OpAllocObj* as_OpAllocObj() { return NULL; } |
aoqi@0 | 1174 | virtual LIR_OpRoundFP* as_OpRoundFP() { return NULL; } |
aoqi@0 | 1175 | virtual LIR_OpBranch* as_OpBranch() { return NULL; } |
aoqi@0 | 1176 | virtual LIR_OpRTCall* as_OpRTCall() { return NULL; } |
aoqi@0 | 1177 | virtual LIR_OpConvert* as_OpConvert() { return NULL; } |
aoqi@0 | 1178 | virtual LIR_Op0* as_Op0() { return NULL; } |
aoqi@0 | 1179 | virtual LIR_Op1* as_Op1() { return NULL; } |
aoqi@0 | 1180 | virtual LIR_Op2* as_Op2() { return NULL; } |
aoqi@0 | 1181 | virtual LIR_Op3* as_Op3() { return NULL; } |
aoqi@0 | 1182 | virtual LIR_OpArrayCopy* as_OpArrayCopy() { return NULL; } |
aoqi@0 | 1183 | virtual LIR_OpUpdateCRC32* as_OpUpdateCRC32() { return NULL; } |
aoqi@0 | 1184 | virtual LIR_OpTypeCheck* as_OpTypeCheck() { return NULL; } |
aoqi@0 | 1185 | virtual LIR_OpCompareAndSwap* as_OpCompareAndSwap() { return NULL; } |
aoqi@0 | 1186 | virtual LIR_OpProfileCall* as_OpProfileCall() { return NULL; } |
aoqi@0 | 1187 | virtual LIR_OpProfileType* as_OpProfileType() { return NULL; } |
aoqi@0 | 1188 | #ifdef ASSERT |
aoqi@0 | 1189 | virtual LIR_OpAssert* as_OpAssert() { return NULL; } |
aoqi@0 | 1190 | #endif |
aoqi@0 | 1191 | |
aoqi@0 | 1192 | virtual void verify() const {} |
aoqi@0 | 1193 | }; |
aoqi@0 | 1194 | |
aoqi@0 | 1195 | // for calls |
aoqi@0 | 1196 | class LIR_OpCall: public LIR_Op { |
aoqi@0 | 1197 | friend class LIR_OpVisitState; |
aoqi@0 | 1198 | |
aoqi@0 | 1199 | protected: |
aoqi@0 | 1200 | address _addr; |
aoqi@0 | 1201 | LIR_OprList* _arguments; |
aoqi@0 | 1202 | protected: |
aoqi@0 | 1203 | LIR_OpCall(LIR_Code code, address addr, LIR_Opr result, |
aoqi@0 | 1204 | LIR_OprList* arguments, CodeEmitInfo* info = NULL) |
aoqi@0 | 1205 | : LIR_Op(code, result, info) |
aoqi@0 | 1206 | , _arguments(arguments) |
aoqi@0 | 1207 | , _addr(addr) {} |
aoqi@0 | 1208 | |
aoqi@0 | 1209 | public: |
aoqi@0 | 1210 | address addr() const { return _addr; } |
aoqi@0 | 1211 | const LIR_OprList* arguments() const { return _arguments; } |
aoqi@0 | 1212 | virtual LIR_OpCall* as_OpCall() { return this; } |
aoqi@0 | 1213 | }; |
aoqi@0 | 1214 | |
aoqi@0 | 1215 | |
aoqi@0 | 1216 | // -------------------------------------------------- |
aoqi@0 | 1217 | // LIR_OpJavaCall |
aoqi@0 | 1218 | // -------------------------------------------------- |
aoqi@0 | 1219 | class LIR_OpJavaCall: public LIR_OpCall { |
aoqi@0 | 1220 | friend class LIR_OpVisitState; |
aoqi@0 | 1221 | |
aoqi@0 | 1222 | private: |
aoqi@0 | 1223 | ciMethod* _method; |
aoqi@0 | 1224 | LIR_Opr _receiver; |
aoqi@0 | 1225 | LIR_Opr _method_handle_invoke_SP_save_opr; // Used in LIR_OpVisitState::visit to store the reference to FrameMap::method_handle_invoke_SP_save_opr. |
aoqi@0 | 1226 | |
aoqi@0 | 1227 | public: |
aoqi@0 | 1228 | LIR_OpJavaCall(LIR_Code code, ciMethod* method, |
aoqi@0 | 1229 | LIR_Opr receiver, LIR_Opr result, |
aoqi@0 | 1230 | address addr, LIR_OprList* arguments, |
aoqi@0 | 1231 | CodeEmitInfo* info) |
aoqi@0 | 1232 | : LIR_OpCall(code, addr, result, arguments, info) |
aoqi@0 | 1233 | , _receiver(receiver) |
aoqi@0 | 1234 | , _method(method) |
aoqi@0 | 1235 | , _method_handle_invoke_SP_save_opr(LIR_OprFact::illegalOpr) |
aoqi@0 | 1236 | { assert(is_in_range(code, begin_opJavaCall, end_opJavaCall), "code check"); } |
aoqi@0 | 1237 | |
aoqi@0 | 1238 | LIR_OpJavaCall(LIR_Code code, ciMethod* method, |
aoqi@0 | 1239 | LIR_Opr receiver, LIR_Opr result, intptr_t vtable_offset, |
aoqi@0 | 1240 | LIR_OprList* arguments, CodeEmitInfo* info) |
aoqi@0 | 1241 | : LIR_OpCall(code, (address)vtable_offset, result, arguments, info) |
aoqi@0 | 1242 | , _receiver(receiver) |
aoqi@0 | 1243 | , _method(method) |
aoqi@0 | 1244 | , _method_handle_invoke_SP_save_opr(LIR_OprFact::illegalOpr) |
aoqi@0 | 1245 | { assert(is_in_range(code, begin_opJavaCall, end_opJavaCall), "code check"); } |
aoqi@0 | 1246 | |
aoqi@0 | 1247 | LIR_Opr receiver() const { return _receiver; } |
aoqi@0 | 1248 | ciMethod* method() const { return _method; } |
aoqi@0 | 1249 | |
aoqi@0 | 1250 | // JSR 292 support. |
aoqi@0 | 1251 | bool is_invokedynamic() const { return code() == lir_dynamic_call; } |
aoqi@0 | 1252 | bool is_method_handle_invoke() const { |
aoqi@0 | 1253 | return |
aoqi@0 | 1254 | method()->is_compiled_lambda_form() // Java-generated adapter |
aoqi@0 | 1255 | || |
aoqi@0 | 1256 | method()->is_method_handle_intrinsic(); // JVM-generated MH intrinsic |
aoqi@0 | 1257 | } |
aoqi@0 | 1258 | |
aoqi@0 | 1259 | intptr_t vtable_offset() const { |
aoqi@0 | 1260 | assert(_code == lir_virtual_call, "only have vtable for real vcall"); |
aoqi@0 | 1261 | return (intptr_t) addr(); |
aoqi@0 | 1262 | } |
aoqi@0 | 1263 | |
aoqi@0 | 1264 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1265 | virtual LIR_OpJavaCall* as_OpJavaCall() { return this; } |
aoqi@0 | 1266 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1267 | }; |
aoqi@0 | 1268 | |
aoqi@0 | 1269 | // -------------------------------------------------- |
aoqi@0 | 1270 | // LIR_OpLabel |
aoqi@0 | 1271 | // -------------------------------------------------- |
aoqi@0 | 1272 | // Location where a branch can continue |
aoqi@0 | 1273 | class LIR_OpLabel: public LIR_Op { |
aoqi@0 | 1274 | friend class LIR_OpVisitState; |
aoqi@0 | 1275 | |
aoqi@0 | 1276 | private: |
aoqi@0 | 1277 | Label* _label; |
aoqi@0 | 1278 | public: |
aoqi@0 | 1279 | LIR_OpLabel(Label* lbl) |
aoqi@0 | 1280 | : LIR_Op(lir_label, LIR_OprFact::illegalOpr, NULL) |
aoqi@0 | 1281 | , _label(lbl) {} |
aoqi@0 | 1282 | Label* label() const { return _label; } |
aoqi@0 | 1283 | |
aoqi@0 | 1284 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1285 | virtual LIR_OpLabel* as_OpLabel() { return this; } |
aoqi@0 | 1286 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1287 | }; |
aoqi@0 | 1288 | |
aoqi@0 | 1289 | // LIR_OpArrayCopy |
aoqi@0 | 1290 | class LIR_OpArrayCopy: public LIR_Op { |
aoqi@0 | 1291 | friend class LIR_OpVisitState; |
aoqi@0 | 1292 | |
aoqi@0 | 1293 | private: |
aoqi@0 | 1294 | ArrayCopyStub* _stub; |
aoqi@0 | 1295 | LIR_Opr _src; |
aoqi@0 | 1296 | LIR_Opr _src_pos; |
aoqi@0 | 1297 | LIR_Opr _dst; |
aoqi@0 | 1298 | LIR_Opr _dst_pos; |
aoqi@0 | 1299 | LIR_Opr _length; |
aoqi@0 | 1300 | LIR_Opr _tmp; |
aoqi@0 | 1301 | ciArrayKlass* _expected_type; |
aoqi@0 | 1302 | int _flags; |
aoqi@0 | 1303 | |
aoqi@0 | 1304 | public: |
aoqi@0 | 1305 | enum Flags { |
aoqi@0 | 1306 | src_null_check = 1 << 0, |
aoqi@0 | 1307 | dst_null_check = 1 << 1, |
aoqi@0 | 1308 | src_pos_positive_check = 1 << 2, |
aoqi@0 | 1309 | dst_pos_positive_check = 1 << 3, |
aoqi@0 | 1310 | length_positive_check = 1 << 4, |
aoqi@0 | 1311 | src_range_check = 1 << 5, |
aoqi@0 | 1312 | dst_range_check = 1 << 6, |
aoqi@0 | 1313 | type_check = 1 << 7, |
aoqi@0 | 1314 | overlapping = 1 << 8, |
aoqi@0 | 1315 | unaligned = 1 << 9, |
aoqi@0 | 1316 | src_objarray = 1 << 10, |
aoqi@0 | 1317 | dst_objarray = 1 << 11, |
aoqi@0 | 1318 | all_flags = (1 << 12) - 1 |
aoqi@0 | 1319 | }; |
aoqi@0 | 1320 | |
aoqi@0 | 1321 | LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, LIR_Opr tmp, |
aoqi@0 | 1322 | ciArrayKlass* expected_type, int flags, CodeEmitInfo* info); |
aoqi@0 | 1323 | |
aoqi@0 | 1324 | LIR_Opr src() const { return _src; } |
aoqi@0 | 1325 | LIR_Opr src_pos() const { return _src_pos; } |
aoqi@0 | 1326 | LIR_Opr dst() const { return _dst; } |
aoqi@0 | 1327 | LIR_Opr dst_pos() const { return _dst_pos; } |
aoqi@0 | 1328 | LIR_Opr length() const { return _length; } |
aoqi@0 | 1329 | LIR_Opr tmp() const { return _tmp; } |
aoqi@0 | 1330 | int flags() const { return _flags; } |
aoqi@0 | 1331 | ciArrayKlass* expected_type() const { return _expected_type; } |
aoqi@0 | 1332 | ArrayCopyStub* stub() const { return _stub; } |
aoqi@0 | 1333 | |
aoqi@0 | 1334 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1335 | virtual LIR_OpArrayCopy* as_OpArrayCopy() { return this; } |
aoqi@0 | 1336 | void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1337 | }; |
aoqi@0 | 1338 | |
aoqi@0 | 1339 | // LIR_OpUpdateCRC32 |
aoqi@0 | 1340 | class LIR_OpUpdateCRC32: public LIR_Op { |
aoqi@0 | 1341 | friend class LIR_OpVisitState; |
aoqi@0 | 1342 | |
aoqi@0 | 1343 | private: |
aoqi@0 | 1344 | LIR_Opr _crc; |
aoqi@0 | 1345 | LIR_Opr _val; |
aoqi@0 | 1346 | |
aoqi@0 | 1347 | public: |
aoqi@0 | 1348 | |
aoqi@0 | 1349 | LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res); |
aoqi@0 | 1350 | |
aoqi@0 | 1351 | LIR_Opr crc() const { return _crc; } |
aoqi@0 | 1352 | LIR_Opr val() const { return _val; } |
aoqi@0 | 1353 | |
aoqi@0 | 1354 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1355 | virtual LIR_OpUpdateCRC32* as_OpUpdateCRC32() { return this; } |
aoqi@0 | 1356 | void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1357 | }; |
aoqi@0 | 1358 | |
aoqi@0 | 1359 | // -------------------------------------------------- |
aoqi@0 | 1360 | // LIR_Op0 |
aoqi@0 | 1361 | // -------------------------------------------------- |
aoqi@0 | 1362 | class LIR_Op0: public LIR_Op { |
aoqi@0 | 1363 | friend class LIR_OpVisitState; |
aoqi@0 | 1364 | |
aoqi@0 | 1365 | public: |
aoqi@0 | 1366 | LIR_Op0(LIR_Code code) |
aoqi@0 | 1367 | : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) { assert(is_in_range(code, begin_op0, end_op0), "code check"); } |
aoqi@0 | 1368 | LIR_Op0(LIR_Code code, LIR_Opr result, CodeEmitInfo* info = NULL) |
aoqi@0 | 1369 | : LIR_Op(code, result, info) { assert(is_in_range(code, begin_op0, end_op0), "code check"); } |
aoqi@0 | 1370 | |
aoqi@0 | 1371 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1372 | virtual LIR_Op0* as_Op0() { return this; } |
aoqi@0 | 1373 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1374 | }; |
aoqi@0 | 1375 | |
aoqi@0 | 1376 | |
aoqi@0 | 1377 | // -------------------------------------------------- |
aoqi@0 | 1378 | // LIR_Op1 |
aoqi@0 | 1379 | // -------------------------------------------------- |
aoqi@0 | 1380 | |
aoqi@0 | 1381 | class LIR_Op1: public LIR_Op { |
aoqi@0 | 1382 | friend class LIR_OpVisitState; |
aoqi@0 | 1383 | |
aoqi@0 | 1384 | protected: |
aoqi@0 | 1385 | LIR_Opr _opr; // input operand |
aoqi@0 | 1386 | BasicType _type; // Operand types |
aoqi@0 | 1387 | LIR_PatchCode _patch; // only required with patchin (NEEDS_CLEANUP: do we want a special instruction for patching?) |
aoqi@0 | 1388 | |
aoqi@0 | 1389 | static void print_patch_code(outputStream* out, LIR_PatchCode code); |
aoqi@0 | 1390 | |
aoqi@0 | 1391 | void set_kind(LIR_MoveKind kind) { |
aoqi@0 | 1392 | assert(code() == lir_move, "must be"); |
aoqi@0 | 1393 | _flags = kind; |
aoqi@0 | 1394 | } |
aoqi@0 | 1395 | |
aoqi@0 | 1396 | public: |
aoqi@0 | 1397 | LIR_Op1(LIR_Code code, LIR_Opr opr, LIR_Opr result = LIR_OprFact::illegalOpr, BasicType type = T_ILLEGAL, LIR_PatchCode patch = lir_patch_none, CodeEmitInfo* info = NULL) |
aoqi@0 | 1398 | : LIR_Op(code, result, info) |
aoqi@0 | 1399 | , _opr(opr) |
aoqi@0 | 1400 | , _patch(patch) |
aoqi@0 | 1401 | , _type(type) { assert(is_in_range(code, begin_op1, end_op1), "code check"); } |
aoqi@0 | 1402 | |
aoqi@0 | 1403 | LIR_Op1(LIR_Code code, LIR_Opr opr, LIR_Opr result, BasicType type, LIR_PatchCode patch, CodeEmitInfo* info, LIR_MoveKind kind) |
aoqi@0 | 1404 | : LIR_Op(code, result, info) |
aoqi@0 | 1405 | , _opr(opr) |
aoqi@0 | 1406 | , _patch(patch) |
aoqi@0 | 1407 | , _type(type) { |
aoqi@0 | 1408 | assert(code == lir_move, "must be"); |
aoqi@0 | 1409 | set_kind(kind); |
aoqi@0 | 1410 | } |
aoqi@0 | 1411 | |
aoqi@0 | 1412 | LIR_Op1(LIR_Code code, LIR_Opr opr, CodeEmitInfo* info) |
aoqi@0 | 1413 | : LIR_Op(code, LIR_OprFact::illegalOpr, info) |
aoqi@0 | 1414 | , _opr(opr) |
aoqi@0 | 1415 | , _patch(lir_patch_none) |
aoqi@0 | 1416 | , _type(T_ILLEGAL) { assert(is_in_range(code, begin_op1, end_op1), "code check"); } |
aoqi@0 | 1417 | |
aoqi@0 | 1418 | LIR_Opr in_opr() const { return _opr; } |
aoqi@0 | 1419 | LIR_PatchCode patch_code() const { return _patch; } |
aoqi@0 | 1420 | BasicType type() const { return _type; } |
aoqi@0 | 1421 | |
aoqi@0 | 1422 | LIR_MoveKind move_kind() const { |
aoqi@0 | 1423 | assert(code() == lir_move, "must be"); |
aoqi@0 | 1424 | return (LIR_MoveKind)_flags; |
aoqi@0 | 1425 | } |
aoqi@0 | 1426 | |
aoqi@0 | 1427 | virtual bool is_patching() { return _patch != lir_patch_none; } |
aoqi@0 | 1428 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1429 | virtual LIR_Op1* as_Op1() { return this; } |
aoqi@0 | 1430 | virtual const char * name() const PRODUCT_RETURN0; |
aoqi@0 | 1431 | |
aoqi@0 | 1432 | void set_in_opr(LIR_Opr opr) { _opr = opr; } |
aoqi@0 | 1433 | |
aoqi@0 | 1434 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1435 | virtual void verify() const; |
aoqi@0 | 1436 | }; |
aoqi@0 | 1437 | |
aoqi@0 | 1438 | |
aoqi@0 | 1439 | // for runtime calls |
aoqi@0 | 1440 | class LIR_OpRTCall: public LIR_OpCall { |
aoqi@0 | 1441 | friend class LIR_OpVisitState; |
aoqi@0 | 1442 | |
aoqi@0 | 1443 | private: |
aoqi@0 | 1444 | LIR_Opr _tmp; |
aoqi@0 | 1445 | public: |
aoqi@0 | 1446 | LIR_OpRTCall(address addr, LIR_Opr tmp, |
aoqi@0 | 1447 | LIR_Opr result, LIR_OprList* arguments, CodeEmitInfo* info = NULL) |
aoqi@0 | 1448 | : LIR_OpCall(lir_rtcall, addr, result, arguments, info) |
aoqi@0 | 1449 | , _tmp(tmp) {} |
aoqi@0 | 1450 | |
aoqi@0 | 1451 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1452 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1453 | virtual LIR_OpRTCall* as_OpRTCall() { return this; } |
aoqi@0 | 1454 | |
aoqi@0 | 1455 | LIR_Opr tmp() const { return _tmp; } |
aoqi@0 | 1456 | |
aoqi@0 | 1457 | virtual void verify() const; |
aoqi@0 | 1458 | }; |
aoqi@0 | 1459 | |
aoqi@1 | 1460 | #ifndef MIPS64 |
aoqi@0 | 1461 | class LIR_OpBranch: public LIR_Op { |
aoqi@0 | 1462 | friend class LIR_OpVisitState; |
aoqi@0 | 1463 | |
aoqi@0 | 1464 | private: |
aoqi@0 | 1465 | LIR_Condition _cond; |
aoqi@0 | 1466 | BasicType _type; |
aoqi@0 | 1467 | Label* _label; |
aoqi@0 | 1468 | BlockBegin* _block; // if this is a branch to a block, this is the block |
aoqi@0 | 1469 | BlockBegin* _ublock; // if this is a float-branch, this is the unorderd block |
aoqi@0 | 1470 | CodeStub* _stub; // if this is a branch to a stub, this is the stub |
aoqi@0 | 1471 | |
aoqi@0 | 1472 | public: |
aoqi@0 | 1473 | LIR_OpBranch(LIR_Condition cond, BasicType type, Label* lbl) |
aoqi@0 | 1474 | : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*) NULL) |
aoqi@0 | 1475 | , _cond(cond) |
aoqi@0 | 1476 | , _type(type) |
aoqi@0 | 1477 | , _label(lbl) |
aoqi@0 | 1478 | , _block(NULL) |
aoqi@0 | 1479 | , _ublock(NULL) |
aoqi@0 | 1480 | , _stub(NULL) { } |
aoqi@0 | 1481 | |
aoqi@0 | 1482 | LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block); |
aoqi@0 | 1483 | LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub); |
aoqi@0 | 1484 | |
aoqi@0 | 1485 | // for unordered comparisons |
aoqi@0 | 1486 | LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock); |
aoqi@0 | 1487 | |
aoqi@0 | 1488 | LIR_Condition cond() const { return _cond; } |
aoqi@0 | 1489 | BasicType type() const { return _type; } |
aoqi@0 | 1490 | Label* label() const { return _label; } |
aoqi@0 | 1491 | BlockBegin* block() const { return _block; } |
aoqi@0 | 1492 | BlockBegin* ublock() const { return _ublock; } |
aoqi@0 | 1493 | CodeStub* stub() const { return _stub; } |
aoqi@0 | 1494 | |
aoqi@0 | 1495 | void change_block(BlockBegin* b); |
aoqi@0 | 1496 | void change_ublock(BlockBegin* b); |
aoqi@0 | 1497 | void negate_cond(); |
aoqi@0 | 1498 | |
aoqi@0 | 1499 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1500 | virtual LIR_OpBranch* as_OpBranch() { return this; } |
aoqi@0 | 1501 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1502 | }; |
aoqi@1 | 1503 | #endif |
aoqi@0 | 1504 | |
aoqi@0 | 1505 | class ConversionStub; |
aoqi@0 | 1506 | |
aoqi@0 | 1507 | class LIR_OpConvert: public LIR_Op1 { |
aoqi@0 | 1508 | friend class LIR_OpVisitState; |
aoqi@0 | 1509 | |
aoqi@0 | 1510 | private: |
aoqi@0 | 1511 | Bytecodes::Code _bytecode; |
aoqi@0 | 1512 | ConversionStub* _stub; |
aoqi@0 | 1513 | #ifdef PPC |
aoqi@0 | 1514 | LIR_Opr _tmp1; |
aoqi@0 | 1515 | LIR_Opr _tmp2; |
aoqi@0 | 1516 | #endif |
aoqi@0 | 1517 | |
aoqi@0 | 1518 | public: |
aoqi@0 | 1519 | LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub) |
aoqi@0 | 1520 | : LIR_Op1(lir_convert, opr, result) |
aoqi@0 | 1521 | , _stub(stub) |
aoqi@0 | 1522 | #ifdef PPC |
aoqi@0 | 1523 | , _tmp1(LIR_OprDesc::illegalOpr()) |
aoqi@0 | 1524 | , _tmp2(LIR_OprDesc::illegalOpr()) |
aoqi@0 | 1525 | #endif |
aoqi@0 | 1526 | , _bytecode(code) {} |
aoqi@0 | 1527 | |
aoqi@0 | 1528 | #ifdef PPC |
aoqi@0 | 1529 | LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub |
aoqi@0 | 1530 | ,LIR_Opr tmp1, LIR_Opr tmp2) |
aoqi@0 | 1531 | : LIR_Op1(lir_convert, opr, result) |
aoqi@0 | 1532 | , _stub(stub) |
aoqi@0 | 1533 | , _tmp1(tmp1) |
aoqi@0 | 1534 | , _tmp2(tmp2) |
aoqi@0 | 1535 | , _bytecode(code) {} |
aoqi@0 | 1536 | #endif |
aoqi@0 | 1537 | |
aoqi@0 | 1538 | Bytecodes::Code bytecode() const { return _bytecode; } |
aoqi@0 | 1539 | ConversionStub* stub() const { return _stub; } |
aoqi@0 | 1540 | #ifdef PPC |
aoqi@0 | 1541 | LIR_Opr tmp1() const { return _tmp1; } |
aoqi@0 | 1542 | LIR_Opr tmp2() const { return _tmp2; } |
aoqi@0 | 1543 | #endif |
aoqi@0 | 1544 | |
aoqi@0 | 1545 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1546 | virtual LIR_OpConvert* as_OpConvert() { return this; } |
aoqi@0 | 1547 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1548 | |
aoqi@0 | 1549 | static void print_bytecode(outputStream* out, Bytecodes::Code code) PRODUCT_RETURN; |
aoqi@0 | 1550 | }; |
aoqi@0 | 1551 | |
aoqi@1 | 1552 | #ifndef MIPS64 |
aoqi@0 | 1553 | // LIR_OpAllocObj |
aoqi@0 | 1554 | class LIR_OpAllocObj : public LIR_Op1 { |
aoqi@0 | 1555 | friend class LIR_OpVisitState; |
aoqi@0 | 1556 | |
aoqi@0 | 1557 | private: |
aoqi@0 | 1558 | LIR_Opr _tmp1; |
aoqi@0 | 1559 | LIR_Opr _tmp2; |
aoqi@0 | 1560 | LIR_Opr _tmp3; |
aoqi@0 | 1561 | LIR_Opr _tmp4; |
aoqi@0 | 1562 | int _hdr_size; |
aoqi@0 | 1563 | int _obj_size; |
aoqi@0 | 1564 | CodeStub* _stub; |
aoqi@0 | 1565 | bool _init_check; |
aoqi@0 | 1566 | |
aoqi@0 | 1567 | public: |
aoqi@0 | 1568 | LIR_OpAllocObj(LIR_Opr klass, LIR_Opr result, |
aoqi@0 | 1569 | LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, |
aoqi@0 | 1570 | int hdr_size, int obj_size, bool init_check, CodeStub* stub) |
aoqi@0 | 1571 | : LIR_Op1(lir_alloc_object, klass, result) |
aoqi@0 | 1572 | , _tmp1(t1) |
aoqi@0 | 1573 | , _tmp2(t2) |
aoqi@0 | 1574 | , _tmp3(t3) |
aoqi@0 | 1575 | , _tmp4(t4) |
aoqi@0 | 1576 | , _hdr_size(hdr_size) |
aoqi@0 | 1577 | , _obj_size(obj_size) |
aoqi@0 | 1578 | , _init_check(init_check) |
aoqi@0 | 1579 | , _stub(stub) { } |
aoqi@0 | 1580 | |
aoqi@0 | 1581 | LIR_Opr klass() const { return in_opr(); } |
aoqi@0 | 1582 | LIR_Opr obj() const { return result_opr(); } |
aoqi@0 | 1583 | LIR_Opr tmp1() const { return _tmp1; } |
aoqi@0 | 1584 | LIR_Opr tmp2() const { return _tmp2; } |
aoqi@0 | 1585 | LIR_Opr tmp3() const { return _tmp3; } |
aoqi@0 | 1586 | LIR_Opr tmp4() const { return _tmp4; } |
aoqi@0 | 1587 | int header_size() const { return _hdr_size; } |
aoqi@0 | 1588 | int object_size() const { return _obj_size; } |
aoqi@0 | 1589 | bool init_check() const { return _init_check; } |
aoqi@0 | 1590 | CodeStub* stub() const { return _stub; } |
aoqi@0 | 1591 | |
aoqi@0 | 1592 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1593 | virtual LIR_OpAllocObj * as_OpAllocObj () { return this; } |
aoqi@0 | 1594 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1595 | }; |
aoqi@1 | 1596 | #else |
aoqi@1 | 1597 | class LIR_OpAllocObj : public LIR_Op1 { |
aoqi@1 | 1598 | friend class LIR_OpVisitState; |
aoqi@1 | 1599 | |
aoqi@1 | 1600 | private: |
aoqi@1 | 1601 | LIR_Opr _tmp1; |
aoqi@1 | 1602 | LIR_Opr _tmp2; |
aoqi@1 | 1603 | LIR_Opr _tmp3; |
aoqi@1 | 1604 | LIR_Opr _tmp4; |
aoqi@1 | 1605 | LIR_Opr _tmp5; |
aoqi@1 | 1606 | LIR_Opr _tmp6; |
aoqi@1 | 1607 | int _hdr_size; |
aoqi@1 | 1608 | int _obj_size; |
aoqi@1 | 1609 | CodeStub* _stub; |
aoqi@1 | 1610 | bool _init_check; |
aoqi@1 | 1611 | |
aoqi@1 | 1612 | public: |
aoqi@1 | 1613 | LIR_OpAllocObj(LIR_Opr klass, LIR_Opr result, |
aoqi@1 | 1614 | LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,LIR_Opr t5, LIR_Opr t6, |
aoqi@1 | 1615 | int hdr_size, int obj_size, bool init_check, CodeStub* stub) |
aoqi@1 | 1616 | : LIR_Op1(lir_alloc_object, klass, result) |
aoqi@1 | 1617 | , _tmp1(t1) |
aoqi@1 | 1618 | , _tmp2(t2) |
aoqi@1 | 1619 | , _tmp3(t3) |
aoqi@1 | 1620 | , _tmp4(t4) |
aoqi@1 | 1621 | , _tmp5(t5) |
aoqi@1 | 1622 | , _tmp6(t6) |
aoqi@1 | 1623 | , _hdr_size(hdr_size) |
aoqi@1 | 1624 | , _obj_size(obj_size) |
aoqi@1 | 1625 | , _init_check(init_check) |
aoqi@1 | 1626 | , _stub(stub) { } |
aoqi@1 | 1627 | |
aoqi@1 | 1628 | LIR_Opr klass() const { return in_opr(); } |
aoqi@1 | 1629 | LIR_Opr obj() const { return result_opr(); } |
aoqi@1 | 1630 | LIR_Opr tmp1() const { return _tmp1; } |
aoqi@1 | 1631 | LIR_Opr tmp2() const { return _tmp2; } |
aoqi@1 | 1632 | LIR_Opr tmp3() const { return _tmp3; } |
aoqi@1 | 1633 | LIR_Opr tmp4() const { return _tmp4; } |
aoqi@1 | 1634 | LIR_Opr tmp5() const { return _tmp5; } |
aoqi@1 | 1635 | LIR_Opr tmp6() const { return _tmp6; } |
aoqi@1 | 1636 | int header_size() const { return _hdr_size; } |
aoqi@1 | 1637 | int object_size() const { return _obj_size; } |
aoqi@1 | 1638 | bool init_check() const { return _init_check; } |
aoqi@1 | 1639 | CodeStub* stub() const { return _stub; } |
aoqi@1 | 1640 | |
aoqi@1 | 1641 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@1 | 1642 | virtual LIR_OpAllocObj * as_OpAllocObj () { return this; } |
aoqi@1 | 1643 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@1 | 1644 | }; |
aoqi@1 | 1645 | #endif |
aoqi@0 | 1646 | |
aoqi@0 | 1647 | // LIR_OpRoundFP |
aoqi@0 | 1648 | class LIR_OpRoundFP : public LIR_Op1 { |
aoqi@0 | 1649 | friend class LIR_OpVisitState; |
aoqi@0 | 1650 | |
aoqi@0 | 1651 | private: |
aoqi@0 | 1652 | LIR_Opr _tmp; |
aoqi@0 | 1653 | |
aoqi@0 | 1654 | public: |
aoqi@0 | 1655 | LIR_OpRoundFP(LIR_Opr reg, LIR_Opr stack_loc_temp, LIR_Opr result) |
aoqi@0 | 1656 | : LIR_Op1(lir_roundfp, reg, result) |
aoqi@0 | 1657 | , _tmp(stack_loc_temp) {} |
aoqi@0 | 1658 | |
aoqi@0 | 1659 | LIR_Opr tmp() const { return _tmp; } |
aoqi@0 | 1660 | virtual LIR_OpRoundFP* as_OpRoundFP() { return this; } |
aoqi@0 | 1661 | void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1662 | }; |
aoqi@0 | 1663 | |
aoqi@0 | 1664 | // LIR_OpTypeCheck |
aoqi@0 | 1665 | class LIR_OpTypeCheck: public LIR_Op { |
aoqi@0 | 1666 | friend class LIR_OpVisitState; |
aoqi@0 | 1667 | |
aoqi@0 | 1668 | private: |
aoqi@0 | 1669 | LIR_Opr _object; |
aoqi@0 | 1670 | LIR_Opr _array; |
aoqi@0 | 1671 | ciKlass* _klass; |
aoqi@0 | 1672 | LIR_Opr _tmp1; |
aoqi@0 | 1673 | LIR_Opr _tmp2; |
aoqi@0 | 1674 | LIR_Opr _tmp3; |
aoqi@0 | 1675 | bool _fast_check; |
aoqi@0 | 1676 | CodeEmitInfo* _info_for_patch; |
aoqi@0 | 1677 | CodeEmitInfo* _info_for_exception; |
aoqi@0 | 1678 | CodeStub* _stub; |
aoqi@0 | 1679 | ciMethod* _profiled_method; |
aoqi@0 | 1680 | int _profiled_bci; |
aoqi@0 | 1681 | bool _should_profile; |
aoqi@0 | 1682 | |
aoqi@0 | 1683 | public: |
aoqi@0 | 1684 | LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, |
aoqi@0 | 1685 | LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, |
aoqi@0 | 1686 | CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub); |
aoqi@0 | 1687 | LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, |
aoqi@0 | 1688 | LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception); |
aoqi@0 | 1689 | |
aoqi@0 | 1690 | LIR_Opr object() const { return _object; } |
aoqi@0 | 1691 | LIR_Opr array() const { assert(code() == lir_store_check, "not valid"); return _array; } |
aoqi@0 | 1692 | LIR_Opr tmp1() const { return _tmp1; } |
aoqi@0 | 1693 | LIR_Opr tmp2() const { return _tmp2; } |
aoqi@0 | 1694 | LIR_Opr tmp3() const { return _tmp3; } |
aoqi@0 | 1695 | ciKlass* klass() const { assert(code() == lir_instanceof || code() == lir_checkcast, "not valid"); return _klass; } |
aoqi@0 | 1696 | bool fast_check() const { assert(code() == lir_instanceof || code() == lir_checkcast, "not valid"); return _fast_check; } |
aoqi@0 | 1697 | CodeEmitInfo* info_for_patch() const { return _info_for_patch; } |
aoqi@0 | 1698 | CodeEmitInfo* info_for_exception() const { return _info_for_exception; } |
aoqi@0 | 1699 | CodeStub* stub() const { return _stub; } |
aoqi@0 | 1700 | |
aoqi@0 | 1701 | // MethodData* profiling |
aoqi@0 | 1702 | void set_profiled_method(ciMethod *method) { _profiled_method = method; } |
aoqi@0 | 1703 | void set_profiled_bci(int bci) { _profiled_bci = bci; } |
aoqi@0 | 1704 | void set_should_profile(bool b) { _should_profile = b; } |
aoqi@0 | 1705 | ciMethod* profiled_method() const { return _profiled_method; } |
aoqi@0 | 1706 | int profiled_bci() const { return _profiled_bci; } |
aoqi@0 | 1707 | bool should_profile() const { return _should_profile; } |
aoqi@0 | 1708 | |
aoqi@0 | 1709 | virtual bool is_patching() { return _info_for_patch != NULL; } |
aoqi@0 | 1710 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1711 | virtual LIR_OpTypeCheck* as_OpTypeCheck() { return this; } |
aoqi@0 | 1712 | void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1713 | }; |
aoqi@1 | 1714 | #ifndef MIPS64 |
aoqi@0 | 1715 | // LIR_Op2 |
aoqi@0 | 1716 | class LIR_Op2: public LIR_Op { |
aoqi@0 | 1717 | friend class LIR_OpVisitState; |
aoqi@0 | 1718 | |
aoqi@0 | 1719 | int _fpu_stack_size; // for sin/cos implementation on Intel |
aoqi@0 | 1720 | |
aoqi@0 | 1721 | protected: |
aoqi@0 | 1722 | LIR_Opr _opr1; |
aoqi@0 | 1723 | LIR_Opr _opr2; |
aoqi@0 | 1724 | BasicType _type; |
aoqi@0 | 1725 | LIR_Opr _tmp1; |
aoqi@0 | 1726 | LIR_Opr _tmp2; |
aoqi@0 | 1727 | LIR_Opr _tmp3; |
aoqi@0 | 1728 | LIR_Opr _tmp4; |
aoqi@0 | 1729 | LIR_Opr _tmp5; |
aoqi@0 | 1730 | LIR_Condition _condition; |
aoqi@0 | 1731 | |
aoqi@0 | 1732 | void verify() const; |
aoqi@0 | 1733 | |
aoqi@0 | 1734 | public: |
aoqi@0 | 1735 | LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, CodeEmitInfo* info = NULL) |
aoqi@0 | 1736 | : LIR_Op(code, LIR_OprFact::illegalOpr, info) |
aoqi@0 | 1737 | , _opr1(opr1) |
aoqi@0 | 1738 | , _opr2(opr2) |
aoqi@0 | 1739 | , _type(T_ILLEGAL) |
aoqi@0 | 1740 | , _condition(condition) |
aoqi@0 | 1741 | , _fpu_stack_size(0) |
aoqi@0 | 1742 | , _tmp1(LIR_OprFact::illegalOpr) |
aoqi@0 | 1743 | , _tmp2(LIR_OprFact::illegalOpr) |
aoqi@0 | 1744 | , _tmp3(LIR_OprFact::illegalOpr) |
aoqi@0 | 1745 | , _tmp4(LIR_OprFact::illegalOpr) |
aoqi@0 | 1746 | , _tmp5(LIR_OprFact::illegalOpr) { |
aoqi@0 | 1747 | assert(code == lir_cmp || code == lir_assert, "code check"); |
aoqi@0 | 1748 | } |
aoqi@0 | 1749 | |
aoqi@0 | 1750 | LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) |
aoqi@0 | 1751 | : LIR_Op(code, result, NULL) |
aoqi@0 | 1752 | , _opr1(opr1) |
aoqi@0 | 1753 | , _opr2(opr2) |
aoqi@0 | 1754 | , _type(type) |
aoqi@0 | 1755 | , _condition(condition) |
aoqi@0 | 1756 | , _fpu_stack_size(0) |
aoqi@0 | 1757 | , _tmp1(LIR_OprFact::illegalOpr) |
aoqi@0 | 1758 | , _tmp2(LIR_OprFact::illegalOpr) |
aoqi@0 | 1759 | , _tmp3(LIR_OprFact::illegalOpr) |
aoqi@0 | 1760 | , _tmp4(LIR_OprFact::illegalOpr) |
aoqi@0 | 1761 | , _tmp5(LIR_OprFact::illegalOpr) { |
aoqi@0 | 1762 | assert(code == lir_cmove, "code check"); |
aoqi@0 | 1763 | assert(type != T_ILLEGAL, "cmove should have type"); |
aoqi@0 | 1764 | } |
aoqi@0 | 1765 | |
aoqi@0 | 1766 | LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result = LIR_OprFact::illegalOpr, |
aoqi@0 | 1767 | CodeEmitInfo* info = NULL, BasicType type = T_ILLEGAL) |
aoqi@0 | 1768 | : LIR_Op(code, result, info) |
aoqi@0 | 1769 | , _opr1(opr1) |
aoqi@0 | 1770 | , _opr2(opr2) |
aoqi@0 | 1771 | , _type(type) |
aoqi@0 | 1772 | , _condition(lir_cond_unknown) |
aoqi@0 | 1773 | , _fpu_stack_size(0) |
aoqi@0 | 1774 | , _tmp1(LIR_OprFact::illegalOpr) |
aoqi@0 | 1775 | , _tmp2(LIR_OprFact::illegalOpr) |
aoqi@0 | 1776 | , _tmp3(LIR_OprFact::illegalOpr) |
aoqi@0 | 1777 | , _tmp4(LIR_OprFact::illegalOpr) |
aoqi@0 | 1778 | , _tmp5(LIR_OprFact::illegalOpr) { |
aoqi@0 | 1779 | assert(code != lir_cmp && is_in_range(code, begin_op2, end_op2), "code check"); |
aoqi@0 | 1780 | } |
aoqi@0 | 1781 | |
aoqi@0 | 1782 | LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, LIR_Opr tmp1, LIR_Opr tmp2 = LIR_OprFact::illegalOpr, |
aoqi@0 | 1783 | LIR_Opr tmp3 = LIR_OprFact::illegalOpr, LIR_Opr tmp4 = LIR_OprFact::illegalOpr, LIR_Opr tmp5 = LIR_OprFact::illegalOpr) |
aoqi@0 | 1784 | : LIR_Op(code, result, NULL) |
aoqi@0 | 1785 | , _opr1(opr1) |
aoqi@0 | 1786 | , _opr2(opr2) |
aoqi@0 | 1787 | , _type(T_ILLEGAL) |
aoqi@0 | 1788 | , _condition(lir_cond_unknown) |
aoqi@0 | 1789 | , _fpu_stack_size(0) |
aoqi@0 | 1790 | , _tmp1(tmp1) |
aoqi@0 | 1791 | , _tmp2(tmp2) |
aoqi@0 | 1792 | , _tmp3(tmp3) |
aoqi@0 | 1793 | , _tmp4(tmp4) |
aoqi@0 | 1794 | , _tmp5(tmp5) { |
aoqi@0 | 1795 | assert(code != lir_cmp && is_in_range(code, begin_op2, end_op2), "code check"); |
aoqi@0 | 1796 | } |
aoqi@0 | 1797 | |
aoqi@0 | 1798 | LIR_Opr in_opr1() const { return _opr1; } |
aoqi@0 | 1799 | LIR_Opr in_opr2() const { return _opr2; } |
aoqi@0 | 1800 | BasicType type() const { return _type; } |
aoqi@0 | 1801 | LIR_Opr tmp1_opr() const { return _tmp1; } |
aoqi@0 | 1802 | LIR_Opr tmp2_opr() const { return _tmp2; } |
aoqi@0 | 1803 | LIR_Opr tmp3_opr() const { return _tmp3; } |
aoqi@0 | 1804 | LIR_Opr tmp4_opr() const { return _tmp4; } |
aoqi@0 | 1805 | LIR_Opr tmp5_opr() const { return _tmp5; } |
aoqi@0 | 1806 | LIR_Condition condition() const { |
aoqi@0 | 1807 | assert(code() == lir_cmp || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); return _condition; |
aoqi@0 | 1808 | } |
aoqi@0 | 1809 | void set_condition(LIR_Condition condition) { |
aoqi@0 | 1810 | assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); _condition = condition; |
aoqi@0 | 1811 | } |
aoqi@0 | 1812 | |
aoqi@0 | 1813 | void set_fpu_stack_size(int size) { _fpu_stack_size = size; } |
aoqi@0 | 1814 | int fpu_stack_size() const { return _fpu_stack_size; } |
aoqi@0 | 1815 | |
aoqi@0 | 1816 | void set_in_opr1(LIR_Opr opr) { _opr1 = opr; } |
aoqi@0 | 1817 | void set_in_opr2(LIR_Opr opr) { _opr2 = opr; } |
aoqi@0 | 1818 | |
aoqi@0 | 1819 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1820 | virtual LIR_Op2* as_Op2() { return this; } |
aoqi@0 | 1821 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1822 | }; |
aoqi@1 | 1823 | #else |
aoqi@1 | 1824 | class LIR_Op2: public LIR_Op { |
aoqi@1 | 1825 | //friend class LIR_Optimizer; |
aoqi@1 | 1826 | friend class LIR_OpVisitState; |
aoqi@1 | 1827 | protected: |
aoqi@1 | 1828 | LIR_Opr _opr1; |
aoqi@1 | 1829 | LIR_Opr _opr2; |
aoqi@1 | 1830 | BasicType _type; |
aoqi@1 | 1831 | LIR_Opr _tmp1; |
aoqi@1 | 1832 | LIR_Opr _tmp2; |
aoqi@1 | 1833 | LIR_Opr _tmp3; |
aoqi@1 | 1834 | LIR_Opr _tmp4; |
aoqi@1 | 1835 | LIR_Opr _tmp5; |
aoqi@1 | 1836 | |
aoqi@1 | 1837 | virtual void verify() const; |
aoqi@1 | 1838 | public: |
aoqi@1 | 1839 | LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, |
aoqi@1 | 1840 | CodeEmitInfo* info = NULL, BasicType type = T_ILLEGAL) |
aoqi@1 | 1841 | : LIR_Op(code, LIR_OprFact::illegalOpr, info), |
aoqi@1 | 1842 | _opr1(opr1), _opr2(opr2), |
aoqi@1 | 1843 | _type(type), |
aoqi@1 | 1844 | _tmp1(LIR_OprFact::illegalOpr), |
aoqi@1 | 1845 | _tmp2(LIR_OprFact::illegalOpr), |
aoqi@1 | 1846 | _tmp3(LIR_OprFact::illegalOpr), |
aoqi@1 | 1847 | _tmp4(LIR_OprFact::illegalOpr), |
aoqi@1 | 1848 | _tmp5(LIR_OprFact::illegalOpr) { |
aoqi@1 | 1849 | } |
aoqi@1 | 1850 | |
aoqi@1 | 1851 | LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result = LIR_OprFact::illegalOpr, |
aoqi@1 | 1852 | CodeEmitInfo* info = NULL, BasicType type = T_ILLEGAL) |
aoqi@1 | 1853 | : LIR_Op(code, result, info), |
aoqi@1 | 1854 | _opr1(opr1), _opr2(opr2), |
aoqi@1 | 1855 | _type(type), |
aoqi@1 | 1856 | _tmp1(LIR_OprFact::illegalOpr), |
aoqi@1 | 1857 | _tmp2(LIR_OprFact::illegalOpr), |
aoqi@1 | 1858 | _tmp3(LIR_OprFact::illegalOpr), |
aoqi@1 | 1859 | _tmp4(LIR_OprFact::illegalOpr), |
aoqi@1 | 1860 | _tmp5(LIR_OprFact::illegalOpr) { |
aoqi@1 | 1861 | |
aoqi@1 | 1862 | assert(is_in_range(code, begin_op2, end_op2), "code check"); |
aoqi@1 | 1863 | } |
aoqi@1 | 1864 | |
aoqi@1 | 1865 | |
aoqi@1 | 1866 | LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, LIR_Opr tmp1, LIR_Opr tmp2 = LIR_OprFact::illegalOpr, LIR_Opr tmp3 = LIR_OprFact::illegalOpr, LIR_Opr tmp4 = LIR_OprFact::illegalOpr, LIR_Opr tmp5 = LIR_OprFact::illegalOpr) |
aoqi@1 | 1867 | : LIR_Op(code, result, NULL), |
aoqi@1 | 1868 | _opr1(opr1), _opr2(opr2), |
aoqi@1 | 1869 | _type(T_ILLEGAL), |
aoqi@1 | 1870 | _tmp1(tmp1), |
aoqi@1 | 1871 | _tmp2(tmp2), |
aoqi@1 | 1872 | _tmp3(tmp3), |
aoqi@1 | 1873 | _tmp4(tmp4), |
aoqi@1 | 1874 | _tmp5(tmp5) { |
aoqi@1 | 1875 | assert(is_in_range(code, begin_op2, end_op2), "code check"); |
aoqi@1 | 1876 | } |
aoqi@1 | 1877 | |
aoqi@1 | 1878 | LIR_Opr in_opr1() const { return _opr1; } |
aoqi@1 | 1879 | LIR_Opr in_opr2() const { return _opr2; } |
aoqi@1 | 1880 | BasicType type() const { return _type; } |
aoqi@1 | 1881 | LIR_Opr tmp1_opr() const { return _tmp1; } |
aoqi@1 | 1882 | LIR_Opr tmp2_opr() const { return _tmp2; } |
aoqi@1 | 1883 | LIR_Opr tmp3_opr() const { return _tmp3; } |
aoqi@1 | 1884 | LIR_Opr tmp4_opr() const { return _tmp4; } |
aoqi@1 | 1885 | LIR_Opr tmp5_opr() const { return _tmp5; } |
aoqi@1 | 1886 | |
aoqi@1 | 1887 | |
aoqi@1 | 1888 | void set_in_opr1(LIR_Opr opr) { _opr1 = opr; } |
aoqi@1 | 1889 | void set_in_opr2(LIR_Opr opr) { _opr2 = opr; } |
aoqi@1 | 1890 | // where is the defination of LIR_AbstractAssembler?, 12/21,2006, jerome |
aoqi@1 | 1891 | //virtual void emit_code(LIR_AbstractAssembler* masm); |
aoqi@1 | 1892 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@1 | 1893 | virtual LIR_Op2* as_Op2() { return this; } |
aoqi@1 | 1894 | |
aoqi@1 | 1895 | // virtual void print_instr() const PRODUCT_RETURN; |
aoqi@1 | 1896 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@1 | 1897 | }; |
aoqi@1 | 1898 | |
aoqi@1 | 1899 | |
aoqi@1 | 1900 | class LIR_OpBranch: public LIR_Op2 { |
aoqi@1 | 1901 | friend class LIR_OpVisitState; |
aoqi@1 | 1902 | public: |
aoqi@1 | 1903 | |
aoqi@1 | 1904 | private: |
aoqi@1 | 1905 | LIR_Condition _cond; |
aoqi@1 | 1906 | BasicType _type; |
aoqi@1 | 1907 | Label* _label; |
aoqi@1 | 1908 | BlockBegin* _block; // if this is a branch to a block, this is the block |
aoqi@1 | 1909 | BlockBegin* _ublock; // if this is a float branch , this is the unorder block |
aoqi@1 | 1910 | CodeStub* _stub; // if this is a branch to a stub, this is the stub |
aoqi@1 | 1911 | |
aoqi@1 | 1912 | public: |
aoqi@1 | 1913 | // these are temporary constructors until we start using the conditional register |
aoqi@1 | 1914 | LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, Label* lbl) |
aoqi@1 | 1915 | : LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo*)(NULL)), |
aoqi@1 | 1916 | _cond(cond), _label(lbl), _block(NULL), _ublock(NULL),_stub(NULL) |
aoqi@1 | 1917 | { |
aoqi@1 | 1918 | } |
aoqi@1 | 1919 | |
aoqi@1 | 1920 | LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, BlockBegin* block); |
aoqi@1 | 1921 | |
aoqi@1 | 1922 | LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, CodeStub* stub); |
aoqi@1 | 1923 | |
aoqi@1 | 1924 | //LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub); |
aoqi@1 | 1925 | |
aoqi@1 | 1926 | LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, |
aoqi@1 | 1927 | BlockBegin *block,BlockBegin *ublock); |
aoqi@1 | 1928 | |
aoqi@1 | 1929 | LIR_Condition cond() const { return _cond; } |
aoqi@1 | 1930 | BasicType type() const { return _type; } |
aoqi@1 | 1931 | LIR_Opr left() const { return in_opr1(); } |
aoqi@1 | 1932 | LIR_Opr right() const { return in_opr2(); } |
aoqi@1 | 1933 | Label* label() const { return _label; } |
aoqi@1 | 1934 | BlockBegin* block() const { return _block; } |
aoqi@1 | 1935 | BlockBegin* ublock() const { return _ublock; } |
aoqi@1 | 1936 | CodeStub* stub() const { return _stub; } |
aoqi@1 | 1937 | |
aoqi@1 | 1938 | |
aoqi@1 | 1939 | void change_block(BlockBegin* b); |
aoqi@1 | 1940 | void change_ublock(BlockBegin* b); |
aoqi@1 | 1941 | void negate_cond(); |
aoqi@1 | 1942 | |
aoqi@1 | 1943 | |
aoqi@1 | 1944 | // 12/21,06,jerome |
aoqi@1 | 1945 | //virtual void emit_code(LIR_AbstractAssembler* masm); |
aoqi@1 | 1946 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@1 | 1947 | virtual LIR_OpBranch* as_OpBranch() { return this; } |
aoqi@1 | 1948 | //virtual void print_instr() const PRODUCT_RETURN; |
aoqi@1 | 1949 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@1 | 1950 | |
aoqi@1 | 1951 | }; |
aoqi@1 | 1952 | #endif |
aoqi@1 | 1953 | |
aoqi@1 | 1954 | #ifndef MIPS64 |
aoqi@0 | 1955 | |
aoqi@0 | 1956 | class LIR_OpAllocArray : public LIR_Op { |
aoqi@0 | 1957 | friend class LIR_OpVisitState; |
aoqi@0 | 1958 | |
aoqi@0 | 1959 | private: |
aoqi@0 | 1960 | LIR_Opr _klass; |
aoqi@0 | 1961 | LIR_Opr _len; |
aoqi@0 | 1962 | LIR_Opr _tmp1; |
aoqi@0 | 1963 | LIR_Opr _tmp2; |
aoqi@0 | 1964 | LIR_Opr _tmp3; |
aoqi@0 | 1965 | LIR_Opr _tmp4; |
aoqi@0 | 1966 | BasicType _type; |
aoqi@0 | 1967 | CodeStub* _stub; |
aoqi@0 | 1968 | |
aoqi@0 | 1969 | public: |
aoqi@0 | 1970 | LIR_OpAllocArray(LIR_Opr klass, LIR_Opr len, LIR_Opr result, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, BasicType type, CodeStub* stub) |
aoqi@0 | 1971 | : LIR_Op(lir_alloc_array, result, NULL) |
aoqi@0 | 1972 | , _klass(klass) |
aoqi@0 | 1973 | , _len(len) |
aoqi@0 | 1974 | , _tmp1(t1) |
aoqi@0 | 1975 | , _tmp2(t2) |
aoqi@0 | 1976 | , _tmp3(t3) |
aoqi@0 | 1977 | , _tmp4(t4) |
aoqi@0 | 1978 | , _type(type) |
aoqi@0 | 1979 | , _stub(stub) {} |
aoqi@0 | 1980 | |
aoqi@0 | 1981 | LIR_Opr klass() const { return _klass; } |
aoqi@0 | 1982 | LIR_Opr len() const { return _len; } |
aoqi@0 | 1983 | LIR_Opr obj() const { return result_opr(); } |
aoqi@0 | 1984 | LIR_Opr tmp1() const { return _tmp1; } |
aoqi@0 | 1985 | LIR_Opr tmp2() const { return _tmp2; } |
aoqi@0 | 1986 | LIR_Opr tmp3() const { return _tmp3; } |
aoqi@0 | 1987 | LIR_Opr tmp4() const { return _tmp4; } |
aoqi@0 | 1988 | BasicType type() const { return _type; } |
aoqi@0 | 1989 | CodeStub* stub() const { return _stub; } |
aoqi@0 | 1990 | |
aoqi@0 | 1991 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 1992 | virtual LIR_OpAllocArray * as_OpAllocArray () { return this; } |
aoqi@0 | 1993 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 1994 | }; |
aoqi@1 | 1995 | #else |
aoqi@1 | 1996 | class LIR_OpAllocArray : public LIR_Op { |
aoqi@1 | 1997 | friend class LIR_OpVisitState; |
aoqi@1 | 1998 | |
aoqi@1 | 1999 | private: |
aoqi@1 | 2000 | LIR_Opr _klass; |
aoqi@1 | 2001 | LIR_Opr _len; |
aoqi@1 | 2002 | LIR_Opr _tmp1; |
aoqi@1 | 2003 | LIR_Opr _tmp2; |
aoqi@1 | 2004 | LIR_Opr _tmp3; |
aoqi@1 | 2005 | LIR_Opr _tmp4; |
aoqi@1 | 2006 | LIR_Opr _tmp5; |
aoqi@1 | 2007 | BasicType _type; |
aoqi@1 | 2008 | CodeStub* _stub; |
aoqi@1 | 2009 | |
aoqi@1 | 2010 | public: |
aoqi@1 | 2011 | LIR_OpAllocArray(LIR_Opr klass, LIR_Opr len, LIR_Opr result, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, BasicType type, CodeStub* stub) |
aoqi@1 | 2012 | : LIR_Op(lir_alloc_array, result, NULL) |
aoqi@1 | 2013 | , _klass(klass) |
aoqi@1 | 2014 | , _len(len) |
aoqi@1 | 2015 | , _tmp1(t1) |
aoqi@1 | 2016 | , _tmp2(t2) |
aoqi@1 | 2017 | , _tmp3(t3) |
aoqi@1 | 2018 | , _tmp4(t4) |
aoqi@1 | 2019 | , _tmp5(t5) |
aoqi@1 | 2020 | , _type(type) |
aoqi@1 | 2021 | , _stub(stub) {} |
aoqi@1 | 2022 | |
aoqi@1 | 2023 | LIR_Opr klass() const { return _klass; } |
aoqi@1 | 2024 | LIR_Opr len() const { return _len; } |
aoqi@1 | 2025 | LIR_Opr obj() const { return result_opr(); } |
aoqi@1 | 2026 | LIR_Opr tmp1() const { return _tmp1; } |
aoqi@1 | 2027 | LIR_Opr tmp2() const { return _tmp2; } |
aoqi@1 | 2028 | LIR_Opr tmp3() const { return _tmp3; } |
aoqi@1 | 2029 | LIR_Opr tmp4() const { return _tmp4; } |
aoqi@1 | 2030 | LIR_Opr tmp5() const { return _tmp5; } |
aoqi@1 | 2031 | BasicType type() const { return _type; } |
aoqi@1 | 2032 | CodeStub* stub() const { return _stub; } |
aoqi@1 | 2033 | |
aoqi@1 | 2034 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@1 | 2035 | virtual LIR_OpAllocArray * as_OpAllocArray () { return this; } |
aoqi@1 | 2036 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@1 | 2037 | }; |
aoqi@1 | 2038 | #endif |
aoqi@0 | 2039 | |
aoqi@0 | 2040 | |
aoqi@0 | 2041 | class LIR_Op3: public LIR_Op { |
aoqi@0 | 2042 | friend class LIR_OpVisitState; |
aoqi@0 | 2043 | |
aoqi@0 | 2044 | private: |
aoqi@0 | 2045 | LIR_Opr _opr1; |
aoqi@0 | 2046 | LIR_Opr _opr2; |
aoqi@0 | 2047 | LIR_Opr _opr3; |
aoqi@0 | 2048 | public: |
aoqi@0 | 2049 | LIR_Op3(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr opr3, LIR_Opr result, CodeEmitInfo* info = NULL) |
aoqi@0 | 2050 | : LIR_Op(code, result, info) |
aoqi@0 | 2051 | , _opr1(opr1) |
aoqi@0 | 2052 | , _opr2(opr2) |
aoqi@0 | 2053 | , _opr3(opr3) { assert(is_in_range(code, begin_op3, end_op3), "code check"); } |
aoqi@0 | 2054 | LIR_Opr in_opr1() const { return _opr1; } |
aoqi@0 | 2055 | LIR_Opr in_opr2() const { return _opr2; } |
aoqi@0 | 2056 | LIR_Opr in_opr3() const { return _opr3; } |
aoqi@0 | 2057 | |
aoqi@0 | 2058 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 2059 | virtual LIR_Op3* as_Op3() { return this; } |
aoqi@0 | 2060 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 2061 | }; |
aoqi@0 | 2062 | |
aoqi@0 | 2063 | |
aoqi@0 | 2064 | //-------------------------------- |
aoqi@0 | 2065 | class LabelObj: public CompilationResourceObj { |
aoqi@0 | 2066 | private: |
aoqi@0 | 2067 | Label _label; |
aoqi@0 | 2068 | public: |
aoqi@0 | 2069 | LabelObj() {} |
aoqi@0 | 2070 | Label* label() { return &_label; } |
aoqi@0 | 2071 | }; |
aoqi@0 | 2072 | |
aoqi@0 | 2073 | |
aoqi@0 | 2074 | class LIR_OpLock: public LIR_Op { |
aoqi@0 | 2075 | friend class LIR_OpVisitState; |
aoqi@0 | 2076 | |
aoqi@0 | 2077 | private: |
aoqi@0 | 2078 | LIR_Opr _hdr; |
aoqi@0 | 2079 | LIR_Opr _obj; |
aoqi@0 | 2080 | LIR_Opr _lock; |
aoqi@0 | 2081 | LIR_Opr _scratch; |
aoqi@0 | 2082 | CodeStub* _stub; |
aoqi@0 | 2083 | public: |
aoqi@0 | 2084 | LIR_OpLock(LIR_Code code, LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) |
aoqi@0 | 2085 | : LIR_Op(code, LIR_OprFact::illegalOpr, info) |
aoqi@0 | 2086 | , _hdr(hdr) |
aoqi@0 | 2087 | , _obj(obj) |
aoqi@0 | 2088 | , _lock(lock) |
aoqi@0 | 2089 | , _scratch(scratch) |
aoqi@0 | 2090 | , _stub(stub) {} |
aoqi@0 | 2091 | |
aoqi@0 | 2092 | LIR_Opr hdr_opr() const { return _hdr; } |
aoqi@0 | 2093 | LIR_Opr obj_opr() const { return _obj; } |
aoqi@0 | 2094 | LIR_Opr lock_opr() const { return _lock; } |
aoqi@0 | 2095 | LIR_Opr scratch_opr() const { return _scratch; } |
aoqi@0 | 2096 | CodeStub* stub() const { return _stub; } |
aoqi@0 | 2097 | |
aoqi@0 | 2098 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 2099 | virtual LIR_OpLock* as_OpLock() { return this; } |
aoqi@0 | 2100 | void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 2101 | }; |
aoqi@0 | 2102 | |
aoqi@0 | 2103 | |
aoqi@0 | 2104 | class LIR_OpDelay: public LIR_Op { |
aoqi@0 | 2105 | friend class LIR_OpVisitState; |
aoqi@0 | 2106 | |
aoqi@0 | 2107 | private: |
aoqi@0 | 2108 | LIR_Op* _op; |
aoqi@0 | 2109 | |
aoqi@0 | 2110 | public: |
aoqi@0 | 2111 | LIR_OpDelay(LIR_Op* op, CodeEmitInfo* info): |
aoqi@0 | 2112 | LIR_Op(lir_delay_slot, LIR_OprFact::illegalOpr, info), |
aoqi@0 | 2113 | _op(op) { |
aoqi@0 | 2114 | assert(op->code() == lir_nop || LIRFillDelaySlots, "should be filling with nops"); |
aoqi@0 | 2115 | } |
aoqi@0 | 2116 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 2117 | virtual LIR_OpDelay* as_OpDelay() { return this; } |
aoqi@0 | 2118 | void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 2119 | LIR_Op* delay_op() const { return _op; } |
aoqi@0 | 2120 | CodeEmitInfo* call_info() const { return info(); } |
aoqi@0 | 2121 | }; |
aoqi@0 | 2122 | |
aoqi@0 | 2123 | #ifdef ASSERT |
aoqi@0 | 2124 | // LIR_OpAssert |
aoqi@0 | 2125 | class LIR_OpAssert : public LIR_Op2 { |
aoqi@0 | 2126 | friend class LIR_OpVisitState; |
aoqi@0 | 2127 | |
aoqi@0 | 2128 | private: |
aoqi@0 | 2129 | const char* _msg; |
aoqi@0 | 2130 | bool _halt; |
aoqi@0 | 2131 | |
aoqi@0 | 2132 | public: |
aoqi@0 | 2133 | LIR_OpAssert(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, const char* msg, bool halt) |
aoqi@0 | 2134 | : LIR_Op2(lir_assert, condition, opr1, opr2) |
aoqi@0 | 2135 | , _halt(halt) |
aoqi@0 | 2136 | , _msg(msg) { |
aoqi@0 | 2137 | } |
aoqi@0 | 2138 | |
aoqi@0 | 2139 | const char* msg() const { return _msg; } |
aoqi@0 | 2140 | bool halt() const { return _halt; } |
aoqi@0 | 2141 | |
aoqi@0 | 2142 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 2143 | virtual LIR_OpAssert* as_OpAssert() { return this; } |
aoqi@0 | 2144 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 2145 | }; |
aoqi@0 | 2146 | #endif |
aoqi@0 | 2147 | |
aoqi@0 | 2148 | // LIR_OpCompareAndSwap |
aoqi@0 | 2149 | class LIR_OpCompareAndSwap : public LIR_Op { |
aoqi@0 | 2150 | friend class LIR_OpVisitState; |
aoqi@0 | 2151 | |
aoqi@0 | 2152 | private: |
aoqi@0 | 2153 | LIR_Opr _addr; |
aoqi@0 | 2154 | LIR_Opr _cmp_value; |
aoqi@0 | 2155 | LIR_Opr _new_value; |
aoqi@0 | 2156 | LIR_Opr _tmp1; |
aoqi@0 | 2157 | LIR_Opr _tmp2; |
aoqi@0 | 2158 | |
aoqi@0 | 2159 | public: |
aoqi@0 | 2160 | LIR_OpCompareAndSwap(LIR_Code code, LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
aoqi@0 | 2161 | LIR_Opr t1, LIR_Opr t2, LIR_Opr result) |
aoqi@0 | 2162 | : LIR_Op(code, result, NULL) // no result, no info |
aoqi@0 | 2163 | , _addr(addr) |
aoqi@0 | 2164 | , _cmp_value(cmp_value) |
aoqi@0 | 2165 | , _new_value(new_value) |
aoqi@0 | 2166 | , _tmp1(t1) |
aoqi@0 | 2167 | , _tmp2(t2) { } |
aoqi@0 | 2168 | |
aoqi@0 | 2169 | LIR_Opr addr() const { return _addr; } |
aoqi@0 | 2170 | LIR_Opr cmp_value() const { return _cmp_value; } |
aoqi@0 | 2171 | LIR_Opr new_value() const { return _new_value; } |
aoqi@0 | 2172 | LIR_Opr tmp1() const { return _tmp1; } |
aoqi@0 | 2173 | LIR_Opr tmp2() const { return _tmp2; } |
aoqi@0 | 2174 | |
aoqi@0 | 2175 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 2176 | virtual LIR_OpCompareAndSwap * as_OpCompareAndSwap () { return this; } |
aoqi@0 | 2177 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 2178 | }; |
aoqi@0 | 2179 | |
aoqi@0 | 2180 | // LIR_OpProfileCall |
aoqi@0 | 2181 | class LIR_OpProfileCall : public LIR_Op { |
aoqi@0 | 2182 | friend class LIR_OpVisitState; |
aoqi@0 | 2183 | |
aoqi@0 | 2184 | private: |
aoqi@0 | 2185 | ciMethod* _profiled_method; |
aoqi@0 | 2186 | int _profiled_bci; |
aoqi@0 | 2187 | ciMethod* _profiled_callee; |
aoqi@0 | 2188 | LIR_Opr _mdo; |
aoqi@0 | 2189 | LIR_Opr _recv; |
aoqi@0 | 2190 | LIR_Opr _tmp1; |
aoqi@0 | 2191 | ciKlass* _known_holder; |
aoqi@0 | 2192 | |
aoqi@0 | 2193 | public: |
aoqi@0 | 2194 | // Destroys recv |
aoqi@0 | 2195 | LIR_OpProfileCall(ciMethod* profiled_method, int profiled_bci, ciMethod* profiled_callee, LIR_Opr mdo, LIR_Opr recv, LIR_Opr t1, ciKlass* known_holder) |
aoqi@0 | 2196 | : LIR_Op(lir_profile_call, LIR_OprFact::illegalOpr, NULL) // no result, no info |
aoqi@0 | 2197 | , _profiled_method(profiled_method) |
aoqi@0 | 2198 | , _profiled_bci(profiled_bci) |
aoqi@0 | 2199 | , _profiled_callee(profiled_callee) |
aoqi@0 | 2200 | , _mdo(mdo) |
aoqi@0 | 2201 | , _recv(recv) |
aoqi@0 | 2202 | , _tmp1(t1) |
aoqi@0 | 2203 | , _known_holder(known_holder) { } |
aoqi@0 | 2204 | |
aoqi@0 | 2205 | ciMethod* profiled_method() const { return _profiled_method; } |
aoqi@0 | 2206 | int profiled_bci() const { return _profiled_bci; } |
aoqi@0 | 2207 | ciMethod* profiled_callee() const { return _profiled_callee; } |
aoqi@0 | 2208 | LIR_Opr mdo() const { return _mdo; } |
aoqi@0 | 2209 | LIR_Opr recv() const { return _recv; } |
aoqi@0 | 2210 | LIR_Opr tmp1() const { return _tmp1; } |
aoqi@0 | 2211 | ciKlass* known_holder() const { return _known_holder; } |
aoqi@0 | 2212 | |
aoqi@0 | 2213 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 2214 | virtual LIR_OpProfileCall* as_OpProfileCall() { return this; } |
aoqi@0 | 2215 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 2216 | }; |
aoqi@0 | 2217 | |
aoqi@0 | 2218 | // LIR_OpProfileType |
aoqi@0 | 2219 | class LIR_OpProfileType : public LIR_Op { |
aoqi@0 | 2220 | friend class LIR_OpVisitState; |
aoqi@0 | 2221 | |
aoqi@0 | 2222 | private: |
aoqi@0 | 2223 | LIR_Opr _mdp; |
aoqi@0 | 2224 | LIR_Opr _obj; |
aoqi@0 | 2225 | LIR_Opr _tmp; |
aoqi@0 | 2226 | ciKlass* _exact_klass; // non NULL if we know the klass statically (no need to load it from _obj) |
aoqi@0 | 2227 | intptr_t _current_klass; // what the profiling currently reports |
aoqi@0 | 2228 | bool _not_null; // true if we know statically that _obj cannot be null |
aoqi@0 | 2229 | bool _no_conflict; // true if we're profling parameters, _exact_klass is not NULL and we know |
aoqi@0 | 2230 | // _exact_klass it the only possible type for this parameter in any context. |
aoqi@0 | 2231 | |
aoqi@0 | 2232 | public: |
aoqi@0 | 2233 | // Destroys recv |
aoqi@0 | 2234 | LIR_OpProfileType(LIR_Opr mdp, LIR_Opr obj, ciKlass* exact_klass, intptr_t current_klass, LIR_Opr tmp, bool not_null, bool no_conflict) |
aoqi@0 | 2235 | : LIR_Op(lir_profile_type, LIR_OprFact::illegalOpr, NULL) // no result, no info |
aoqi@0 | 2236 | , _mdp(mdp) |
aoqi@0 | 2237 | , _obj(obj) |
aoqi@0 | 2238 | , _exact_klass(exact_klass) |
aoqi@0 | 2239 | , _current_klass(current_klass) |
aoqi@0 | 2240 | , _tmp(tmp) |
aoqi@0 | 2241 | , _not_null(not_null) |
aoqi@0 | 2242 | , _no_conflict(no_conflict) { } |
aoqi@0 | 2243 | |
aoqi@0 | 2244 | LIR_Opr mdp() const { return _mdp; } |
aoqi@0 | 2245 | LIR_Opr obj() const { return _obj; } |
aoqi@0 | 2246 | LIR_Opr tmp() const { return _tmp; } |
aoqi@0 | 2247 | ciKlass* exact_klass() const { return _exact_klass; } |
aoqi@0 | 2248 | intptr_t current_klass() const { return _current_klass; } |
aoqi@0 | 2249 | bool not_null() const { return _not_null; } |
aoqi@0 | 2250 | bool no_conflict() const { return _no_conflict; } |
aoqi@0 | 2251 | |
aoqi@0 | 2252 | virtual void emit_code(LIR_Assembler* masm); |
aoqi@0 | 2253 | virtual LIR_OpProfileType* as_OpProfileType() { return this; } |
aoqi@0 | 2254 | virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
aoqi@0 | 2255 | }; |
aoqi@0 | 2256 | |
aoqi@0 | 2257 | class LIR_InsertionBuffer; |
aoqi@0 | 2258 | |
aoqi@0 | 2259 | //--------------------------------LIR_List--------------------------------------------------- |
aoqi@0 | 2260 | // Maintains a list of LIR instructions (one instance of LIR_List per basic block) |
aoqi@0 | 2261 | // The LIR instructions are appended by the LIR_List class itself; |
aoqi@0 | 2262 | // |
aoqi@0 | 2263 | // Notes: |
aoqi@0 | 2264 | // - all offsets are(should be) in bytes |
aoqi@0 | 2265 | // - local positions are specified with an offset, with offset 0 being local 0 |
aoqi@0 | 2266 | |
aoqi@0 | 2267 | class LIR_List: public CompilationResourceObj { |
aoqi@0 | 2268 | private: |
aoqi@0 | 2269 | LIR_OpList _operations; |
aoqi@0 | 2270 | |
aoqi@0 | 2271 | Compilation* _compilation; |
aoqi@0 | 2272 | #ifndef PRODUCT |
aoqi@0 | 2273 | BlockBegin* _block; |
aoqi@0 | 2274 | #endif |
aoqi@0 | 2275 | #ifdef ASSERT |
aoqi@0 | 2276 | const char * _file; |
aoqi@0 | 2277 | int _line; |
aoqi@0 | 2278 | #endif |
aoqi@0 | 2279 | |
aoqi@0 | 2280 | void append(LIR_Op* op) { |
aoqi@0 | 2281 | if (op->source() == NULL) |
aoqi@0 | 2282 | op->set_source(_compilation->current_instruction()); |
aoqi@0 | 2283 | #ifndef PRODUCT |
aoqi@0 | 2284 | if (PrintIRWithLIR) { |
aoqi@0 | 2285 | _compilation->maybe_print_current_instruction(); |
aoqi@0 | 2286 | op->print(); tty->cr(); |
aoqi@0 | 2287 | } |
aoqi@0 | 2288 | #endif // PRODUCT |
aoqi@0 | 2289 | |
aoqi@0 | 2290 | _operations.append(op); |
aoqi@0 | 2291 | |
aoqi@0 | 2292 | #ifdef ASSERT |
aoqi@0 | 2293 | op->verify(); |
aoqi@0 | 2294 | op->set_file_and_line(_file, _line); |
aoqi@0 | 2295 | _file = NULL; |
aoqi@0 | 2296 | _line = 0; |
aoqi@0 | 2297 | #endif |
aoqi@0 | 2298 | } |
aoqi@0 | 2299 | |
aoqi@0 | 2300 | public: |
aoqi@0 | 2301 | LIR_List(Compilation* compilation, BlockBegin* block = NULL); |
aoqi@0 | 2302 | |
aoqi@0 | 2303 | #ifdef ASSERT |
aoqi@0 | 2304 | void set_file_and_line(const char * file, int line); |
aoqi@0 | 2305 | #endif |
aoqi@0 | 2306 | |
aoqi@0 | 2307 | //---------- accessors --------------- |
aoqi@0 | 2308 | LIR_OpList* instructions_list() { return &_operations; } |
aoqi@0 | 2309 | int length() const { return _operations.length(); } |
aoqi@0 | 2310 | LIR_Op* at(int i) const { return _operations.at(i); } |
aoqi@0 | 2311 | |
aoqi@0 | 2312 | NOT_PRODUCT(BlockBegin* block() const { return _block; }); |
aoqi@0 | 2313 | |
aoqi@0 | 2314 | // insert LIR_Ops in buffer to right places in LIR_List |
aoqi@0 | 2315 | void append(LIR_InsertionBuffer* buffer); |
aoqi@0 | 2316 | |
aoqi@0 | 2317 | //---------- mutators --------------- |
aoqi@0 | 2318 | void insert_before(int i, LIR_List* op_list) { _operations.insert_before(i, op_list->instructions_list()); } |
aoqi@0 | 2319 | void insert_before(int i, LIR_Op* op) { _operations.insert_before(i, op); } |
aoqi@0 | 2320 | void remove_at(int i) { _operations.remove_at(i); } |
aoqi@0 | 2321 | |
aoqi@0 | 2322 | //---------- printing ------------- |
aoqi@0 | 2323 | void print_instructions() PRODUCT_RETURN; |
aoqi@0 | 2324 | |
aoqi@0 | 2325 | |
aoqi@0 | 2326 | //---------- instructions ------------- |
aoqi@0 | 2327 | void call_opt_virtual(ciMethod* method, LIR_Opr receiver, LIR_Opr result, |
aoqi@0 | 2328 | address dest, LIR_OprList* arguments, |
aoqi@0 | 2329 | CodeEmitInfo* info) { |
aoqi@0 | 2330 | append(new LIR_OpJavaCall(lir_optvirtual_call, method, receiver, result, dest, arguments, info)); |
aoqi@0 | 2331 | } |
aoqi@0 | 2332 | void call_static(ciMethod* method, LIR_Opr result, |
aoqi@0 | 2333 | address dest, LIR_OprList* arguments, CodeEmitInfo* info) { |
aoqi@0 | 2334 | append(new LIR_OpJavaCall(lir_static_call, method, LIR_OprFact::illegalOpr, result, dest, arguments, info)); |
aoqi@0 | 2335 | } |
aoqi@0 | 2336 | void call_icvirtual(ciMethod* method, LIR_Opr receiver, LIR_Opr result, |
aoqi@0 | 2337 | address dest, LIR_OprList* arguments, CodeEmitInfo* info) { |
aoqi@0 | 2338 | append(new LIR_OpJavaCall(lir_icvirtual_call, method, receiver, result, dest, arguments, info)); |
aoqi@0 | 2339 | } |
aoqi@0 | 2340 | void call_virtual(ciMethod* method, LIR_Opr receiver, LIR_Opr result, |
aoqi@0 | 2341 | intptr_t vtable_offset, LIR_OprList* arguments, CodeEmitInfo* info) { |
aoqi@0 | 2342 | append(new LIR_OpJavaCall(lir_virtual_call, method, receiver, result, vtable_offset, arguments, info)); |
aoqi@0 | 2343 | } |
aoqi@0 | 2344 | void call_dynamic(ciMethod* method, LIR_Opr receiver, LIR_Opr result, |
aoqi@0 | 2345 | address dest, LIR_OprList* arguments, CodeEmitInfo* info) { |
aoqi@0 | 2346 | append(new LIR_OpJavaCall(lir_dynamic_call, method, receiver, result, dest, arguments, info)); |
aoqi@0 | 2347 | } |
aoqi@0 | 2348 | |
aoqi@0 | 2349 | void get_thread(LIR_Opr result) { append(new LIR_Op0(lir_get_thread, result)); } |
aoqi@0 | 2350 | void word_align() { append(new LIR_Op0(lir_word_align)); } |
aoqi@0 | 2351 | void membar() { append(new LIR_Op0(lir_membar)); } |
aoqi@0 | 2352 | void membar_acquire() { append(new LIR_Op0(lir_membar_acquire)); } |
aoqi@0 | 2353 | void membar_release() { append(new LIR_Op0(lir_membar_release)); } |
aoqi@0 | 2354 | void membar_loadload() { append(new LIR_Op0(lir_membar_loadload)); } |
aoqi@0 | 2355 | void membar_storestore() { append(new LIR_Op0(lir_membar_storestore)); } |
aoqi@0 | 2356 | void membar_loadstore() { append(new LIR_Op0(lir_membar_loadstore)); } |
aoqi@0 | 2357 | void membar_storeload() { append(new LIR_Op0(lir_membar_storeload)); } |
aoqi@0 | 2358 | |
aoqi@0 | 2359 | void nop() { append(new LIR_Op0(lir_nop)); } |
aoqi@0 | 2360 | void build_frame() { append(new LIR_Op0(lir_build_frame)); } |
aoqi@0 | 2361 | |
aoqi@0 | 2362 | void std_entry(LIR_Opr receiver) { append(new LIR_Op0(lir_std_entry, receiver)); } |
aoqi@0 | 2363 | void osr_entry(LIR_Opr osrPointer) { append(new LIR_Op0(lir_osr_entry, osrPointer)); } |
aoqi@0 | 2364 | |
aoqi@0 | 2365 | void branch_destination(Label* lbl) { append(new LIR_OpLabel(lbl)); } |
aoqi@0 | 2366 | |
aoqi@0 | 2367 | void negate(LIR_Opr from, LIR_Opr to) { append(new LIR_Op1(lir_neg, from, to)); } |
aoqi@0 | 2368 | void leal(LIR_Opr from, LIR_Opr result_reg) { append(new LIR_Op1(lir_leal, from, result_reg)); } |
aoqi@0 | 2369 | |
aoqi@0 | 2370 | // result is a stack location for old backend and vreg for UseLinearScan |
aoqi@0 | 2371 | // stack_loc_temp is an illegal register for old backend |
aoqi@0 | 2372 | void roundfp(LIR_Opr reg, LIR_Opr stack_loc_temp, LIR_Opr result) { append(new LIR_OpRoundFP(reg, stack_loc_temp, result)); } |
aoqi@0 | 2373 | void unaligned_move(LIR_Address* src, LIR_Opr dst) { append(new LIR_Op1(lir_move, LIR_OprFact::address(src), dst, dst->type(), lir_patch_none, NULL, lir_move_unaligned)); } |
aoqi@0 | 2374 | void unaligned_move(LIR_Opr src, LIR_Address* dst) { append(new LIR_Op1(lir_move, src, LIR_OprFact::address(dst), src->type(), lir_patch_none, NULL, lir_move_unaligned)); } |
aoqi@0 | 2375 | void unaligned_move(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_move, src, dst, dst->type(), lir_patch_none, NULL, lir_move_unaligned)); } |
aoqi@0 | 2376 | void move(LIR_Opr src, LIR_Opr dst, CodeEmitInfo* info = NULL) { append(new LIR_Op1(lir_move, src, dst, dst->type(), lir_patch_none, info)); } |
aoqi@0 | 2377 | void move(LIR_Address* src, LIR_Opr dst, CodeEmitInfo* info = NULL) { append(new LIR_Op1(lir_move, LIR_OprFact::address(src), dst, src->type(), lir_patch_none, info)); } |
aoqi@0 | 2378 | void move(LIR_Opr src, LIR_Address* dst, CodeEmitInfo* info = NULL) { append(new LIR_Op1(lir_move, src, LIR_OprFact::address(dst), dst->type(), lir_patch_none, info)); } |
aoqi@0 | 2379 | void move_wide(LIR_Address* src, LIR_Opr dst, CodeEmitInfo* info = NULL) { |
aoqi@0 | 2380 | if (UseCompressedOops) { |
aoqi@0 | 2381 | append(new LIR_Op1(lir_move, LIR_OprFact::address(src), dst, src->type(), lir_patch_none, info, lir_move_wide)); |
aoqi@0 | 2382 | } else { |
aoqi@0 | 2383 | move(src, dst, info); |
aoqi@0 | 2384 | } |
aoqi@0 | 2385 | } |
aoqi@0 | 2386 | void move_wide(LIR_Opr src, LIR_Address* dst, CodeEmitInfo* info = NULL) { |
aoqi@0 | 2387 | if (UseCompressedOops) { |
aoqi@0 | 2388 | append(new LIR_Op1(lir_move, src, LIR_OprFact::address(dst), dst->type(), lir_patch_none, info, lir_move_wide)); |
aoqi@0 | 2389 | } else { |
aoqi@0 | 2390 | move(src, dst, info); |
aoqi@0 | 2391 | } |
aoqi@0 | 2392 | } |
aoqi@0 | 2393 | void volatile_move(LIR_Opr src, LIR_Opr dst, BasicType type, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none) { append(new LIR_Op1(lir_move, src, dst, type, patch_code, info, lir_move_volatile)); } |
aoqi@0 | 2394 | |
aoqi@0 | 2395 | void oop2reg (jobject o, LIR_Opr reg) { assert(reg->type() == T_OBJECT, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg)); } |
aoqi@0 | 2396 | void oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info); |
aoqi@0 | 2397 | |
aoqi@0 | 2398 | void metadata2reg (Metadata* o, LIR_Opr reg) { assert(reg->type() == T_METADATA, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg)); } |
aoqi@0 | 2399 | void klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info); |
aoqi@0 | 2400 | |
aoqi@0 | 2401 | void return_op(LIR_Opr result) { append(new LIR_Op1(lir_return, result)); } |
aoqi@0 | 2402 | |
aoqi@0 | 2403 | void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); } |
aoqi@0 | 2404 | |
aoqi@0 | 2405 | #ifdef PPC |
aoqi@0 | 2406 | void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); } |
aoqi@0 | 2407 | #endif |
aoqi@0 | 2408 | void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); } |
aoqi@0 | 2409 | |
aoqi@0 | 2410 | void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); } |
aoqi@0 | 2411 | void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); } |
aoqi@0 | 2412 | void logical_xor (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_xor, left, right, dst)); } |
aoqi@0 | 2413 | |
aoqi@0 | 2414 | void pack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_pack64, src, dst, T_LONG, lir_patch_none, NULL)); } |
aoqi@0 | 2415 | void unpack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_unpack64, src, dst, T_LONG, lir_patch_none, NULL)); } |
aoqi@0 | 2416 | |
aoqi@0 | 2417 | void null_check(LIR_Opr opr, CodeEmitInfo* info) { append(new LIR_Op1(lir_null_check, opr, info)); } |
aoqi@0 | 2418 | void throw_exception(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
aoqi@0 | 2419 | append(new LIR_Op2(lir_throw, exceptionPC, exceptionOop, LIR_OprFact::illegalOpr, info)); |
aoqi@0 | 2420 | } |
aoqi@0 | 2421 | void unwind_exception(LIR_Opr exceptionOop) { |
aoqi@0 | 2422 | append(new LIR_Op1(lir_unwind, exceptionOop)); |
aoqi@0 | 2423 | } |
aoqi@0 | 2424 | |
aoqi@0 | 2425 | void compare_to (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { |
aoqi@0 | 2426 | append(new LIR_Op2(lir_compare_to, left, right, dst)); |
aoqi@0 | 2427 | } |
aoqi@0 | 2428 | |
aoqi@0 | 2429 | void push(LIR_Opr opr) { append(new LIR_Op1(lir_push, opr)); } |
aoqi@0 | 2430 | void pop(LIR_Opr reg) { append(new LIR_Op1(lir_pop, reg)); } |
aoqi@0 | 2431 | |
aoqi@1 | 2432 | #ifndef MIPS64 |
aoqi@0 | 2433 | void cmp(LIR_Condition condition, LIR_Opr left, LIR_Opr right, CodeEmitInfo* info = NULL) { |
aoqi@0 | 2434 | append(new LIR_Op2(lir_cmp, condition, left, right, info)); |
aoqi@0 | 2435 | } |
aoqi@0 | 2436 | void cmp(LIR_Condition condition, LIR_Opr left, int right, CodeEmitInfo* info = NULL) { |
aoqi@0 | 2437 | cmp(condition, left, LIR_OprFact::intConst(right), info); |
aoqi@0 | 2438 | } |
aoqi@0 | 2439 | |
aoqi@0 | 2440 | void cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info); |
aoqi@0 | 2441 | void cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info); |
aoqi@0 | 2442 | |
aoqi@0 | 2443 | void cmove(LIR_Condition condition, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { |
aoqi@0 | 2444 | append(new LIR_Op2(lir_cmove, condition, src1, src2, dst, type)); |
aoqi@0 | 2445 | } |
aoqi@0 | 2446 | |
aoqi@1 | 2447 | #else |
aoqi@1 | 2448 | void null_check_for_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, |
aoqi@1 | 2449 | CodeEmitInfo* info = NULL) { |
aoqi@1 | 2450 | append(new LIR_Op2(lir_null_check_for_branch, condition, left, right, info)); |
aoqi@1 | 2451 | } |
aoqi@1 | 2452 | |
aoqi@1 | 2453 | void null_check_for_branch(LIR_Condition condition, LIR_Opr left, int right, |
aoqi@1 | 2454 | CodeEmitInfo* info = NULL) { |
aoqi@1 | 2455 | append(new LIR_Op2(lir_null_check_for_branch, condition, left, LIR_OprFact::intConst(right), info)); |
aoqi@1 | 2456 | } |
aoqi@1 | 2457 | |
aoqi@1 | 2458 | void null_check_for_branch(LIR_Condition condition, LIR_Opr base, int disp, int c, |
aoqi@1 | 2459 | CodeEmitInfo* info) { |
aoqi@1 | 2460 | append(new LIR_Op2(lir_null_check_for_branch, condition, |
aoqi@1 | 2461 | LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), |
aoqi@1 | 2462 | LIR_OprFact::intConst(c), |
aoqi@1 | 2463 | info, T_INT)); |
aoqi@1 | 2464 | } |
aoqi@1 | 2465 | |
aoqi@1 | 2466 | void null_check_branch(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, |
aoqi@1 | 2467 | CodeEmitInfo* info) { |
aoqi@1 | 2468 | append(new LIR_Op2(lir_null_check_for_branch, condition, |
aoqi@1 | 2469 | reg, |
aoqi@1 | 2470 | LIR_OprFact::address(addr), |
aoqi@1 | 2471 | info)); |
aoqi@1 | 2472 | } |
aoqi@1 | 2473 | |
aoqi@1 | 2474 | #endif |
aoqi@1 | 2475 | #ifndef MIPS64 |
aoqi@0 | 2476 | void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
aoqi@0 | 2477 | LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); |
aoqi@0 | 2478 | void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
aoqi@0 | 2479 | LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); |
aoqi@0 | 2480 | void cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
aoqi@0 | 2481 | LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); |
aoqi@1 | 2482 | #else |
aoqi@1 | 2483 | void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result); |
aoqi@1 | 2484 | void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result); |
aoqi@1 | 2485 | void cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result); |
aoqi@1 | 2486 | #endif |
aoqi@0 | 2487 | |
aoqi@0 | 2488 | void abs (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_abs , from, tmp, to)); } |
aoqi@0 | 2489 | void sqrt(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_sqrt, from, tmp, to)); } |
aoqi@0 | 2490 | void log (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_log, from, LIR_OprFact::illegalOpr, to, tmp)); } |
aoqi@0 | 2491 | void log10 (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_log10, from, LIR_OprFact::illegalOpr, to, tmp)); } |
aoqi@0 | 2492 | void sin (LIR_Opr from, LIR_Opr to, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_Op2(lir_sin , from, tmp1, to, tmp2)); } |
aoqi@0 | 2493 | void cos (LIR_Opr from, LIR_Opr to, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_Op2(lir_cos , from, tmp1, to, tmp2)); } |
aoqi@0 | 2494 | void tan (LIR_Opr from, LIR_Opr to, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_Op2(lir_tan , from, tmp1, to, tmp2)); } |
aoqi@0 | 2495 | void exp (LIR_Opr from, LIR_Opr to, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, LIR_Opr tmp4, LIR_Opr tmp5) { append(new LIR_Op2(lir_exp , from, tmp1, to, tmp2, tmp3, tmp4, tmp5)); } |
aoqi@0 | 2496 | void pow (LIR_Opr arg1, LIR_Opr arg2, LIR_Opr res, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, LIR_Opr tmp4, LIR_Opr tmp5) { append(new LIR_Op2(lir_pow, arg1, arg2, res, tmp1, tmp2, tmp3, tmp4, tmp5)); } |
aoqi@0 | 2497 | |
aoqi@0 | 2498 | void add (LIR_Opr left, LIR_Opr right, LIR_Opr res) { append(new LIR_Op2(lir_add, left, right, res)); } |
aoqi@0 | 2499 | void sub (LIR_Opr left, LIR_Opr right, LIR_Opr res, CodeEmitInfo* info = NULL) { append(new LIR_Op2(lir_sub, left, right, res, info)); } |
aoqi@0 | 2500 | void mul (LIR_Opr left, LIR_Opr right, LIR_Opr res) { append(new LIR_Op2(lir_mul, left, right, res)); } |
aoqi@0 | 2501 | void mul_strictfp (LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp) { append(new LIR_Op2(lir_mul_strictfp, left, right, res, tmp)); } |
aoqi@0 | 2502 | void div (LIR_Opr left, LIR_Opr right, LIR_Opr res, CodeEmitInfo* info = NULL) { append(new LIR_Op2(lir_div, left, right, res, info)); } |
aoqi@0 | 2503 | void div_strictfp (LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp) { append(new LIR_Op2(lir_div_strictfp, left, right, res, tmp)); } |
aoqi@0 | 2504 | void rem (LIR_Opr left, LIR_Opr right, LIR_Opr res, CodeEmitInfo* info = NULL) { append(new LIR_Op2(lir_rem, left, right, res, info)); } |
aoqi@0 | 2505 | |
aoqi@0 | 2506 | void volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none); |
aoqi@0 | 2507 | void volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code); |
aoqi@0 | 2508 | |
aoqi@0 | 2509 | void load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none); |
aoqi@0 | 2510 | |
aoqi@0 | 2511 | void prefetch(LIR_Address* addr, bool is_store); |
aoqi@0 | 2512 | |
aoqi@0 | 2513 | void store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none); |
aoqi@0 | 2514 | void store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none); |
aoqi@0 | 2515 | void store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none); |
aoqi@0 | 2516 | void volatile_store_mem_reg(LIR_Opr src, LIR_Address* address, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none); |
aoqi@0 | 2517 | void volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code); |
aoqi@0 | 2518 | |
aoqi@1 | 2519 | #ifdef MIPS64 |
aoqi@1 | 2520 | void frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info = NULL); |
aoqi@1 | 2521 | #endif |
aoqi@1 | 2522 | |
aoqi@0 | 2523 | void idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info); |
aoqi@0 | 2524 | void idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info); |
aoqi@0 | 2525 | void irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info); |
aoqi@0 | 2526 | void irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info); |
aoqi@1 | 2527 | #ifndef MIPS64 |
aoqi@0 | 2528 | void allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub); |
aoqi@0 | 2529 | void allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub); |
aoqi@1 | 2530 | #else |
aoqi@1 | 2531 | void allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub); |
aoqi@1 | 2532 | void allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,BasicType type, LIR_Opr klass, CodeStub* stub); |
aoqi@1 | 2533 | #endif |
aoqi@0 | 2534 | |
aoqi@0 | 2535 | // jump is an unconditional branch |
aoqi@0 | 2536 | void jump(BlockBegin* block) { |
aoqi@1 | 2537 | #ifndef MIPS64 |
aoqi@0 | 2538 | append(new LIR_OpBranch(lir_cond_always, T_ILLEGAL, block)); |
aoqi@1 | 2539 | #else |
aoqi@1 | 2540 | append(new LIR_OpBranch(lir_cond_always, LIR_OprFact::illegalOpr,LIR_OprFact::illegalOpr,T_ILLEGAL, block)); |
aoqi@1 | 2541 | #endif |
aoqi@1 | 2542 | |
aoqi@0 | 2543 | } |
aoqi@0 | 2544 | void jump(CodeStub* stub) { |
aoqi@1 | 2545 | #ifndef MIPS64 |
aoqi@0 | 2546 | append(new LIR_OpBranch(lir_cond_always, T_ILLEGAL, stub)); |
aoqi@1 | 2547 | #else |
aoqi@1 | 2548 | append(new LIR_OpBranch(lir_cond_always, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr,T_ILLEGAL, stub)); |
aoqi@1 | 2549 | #endif |
aoqi@1 | 2550 | |
aoqi@0 | 2551 | } |
aoqi@1 | 2552 | #ifndef MIPS64 |
aoqi@0 | 2553 | void branch(LIR_Condition cond, BasicType type, Label* lbl) { append(new LIR_OpBranch(cond, type, lbl)); } |
aoqi@0 | 2554 | void branch(LIR_Condition cond, BasicType type, BlockBegin* block) { |
aoqi@0 | 2555 | assert(type != T_FLOAT && type != T_DOUBLE, "no fp comparisons"); |
aoqi@0 | 2556 | append(new LIR_OpBranch(cond, type, block)); |
aoqi@0 | 2557 | } |
aoqi@0 | 2558 | void branch(LIR_Condition cond, BasicType type, CodeStub* stub) { |
aoqi@0 | 2559 | assert(type != T_FLOAT && type != T_DOUBLE, "no fp comparisons"); |
aoqi@0 | 2560 | append(new LIR_OpBranch(cond, type, stub)); |
aoqi@0 | 2561 | } |
aoqi@0 | 2562 | void branch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* unordered) { |
aoqi@0 | 2563 | assert(type == T_FLOAT || type == T_DOUBLE, "fp comparisons only"); |
aoqi@0 | 2564 | append(new LIR_OpBranch(cond, type, block, unordered)); |
aoqi@0 | 2565 | } |
aoqi@1 | 2566 | #else |
aoqi@1 | 2567 | void branch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, Label* lbl) { |
aoqi@1 | 2568 | append(new LIR_OpBranch(cond, left, right, lbl)); |
aoqi@1 | 2569 | } |
aoqi@1 | 2570 | |
aoqi@1 | 2571 | void branch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, BlockBegin* block) { |
aoqi@1 | 2572 | append(new LIR_OpBranch(cond, left, right, type, block)); |
aoqi@1 | 2573 | } |
aoqi@1 | 2574 | |
aoqi@1 | 2575 | void branch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, CodeStub* stub) { |
aoqi@1 | 2576 | append(new LIR_OpBranch(cond, left, right, type, stub)); |
aoqi@1 | 2577 | } |
aoqi@1 | 2578 | |
aoqi@1 | 2579 | void branch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type, |
aoqi@1 | 2580 | BlockBegin* block, BlockBegin* unordered) { |
aoqi@1 | 2581 | append(new LIR_OpBranch(cond, left, right, type, block, unordered)); |
aoqi@1 | 2582 | } |
aoqi@1 | 2583 | |
aoqi@1 | 2584 | #endif |
aoqi@0 | 2585 | |
aoqi@0 | 2586 | void shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp); |
aoqi@0 | 2587 | void shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp); |
aoqi@0 | 2588 | void unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp); |
aoqi@0 | 2589 | |
aoqi@0 | 2590 | void shift_left(LIR_Opr value, int count, LIR_Opr dst) { shift_left(value, LIR_OprFact::intConst(count), dst, LIR_OprFact::illegalOpr); } |
aoqi@0 | 2591 | void shift_right(LIR_Opr value, int count, LIR_Opr dst) { shift_right(value, LIR_OprFact::intConst(count), dst, LIR_OprFact::illegalOpr); } |
aoqi@0 | 2592 | void unsigned_shift_right(LIR_Opr value, int count, LIR_Opr dst) { unsigned_shift_right(value, LIR_OprFact::intConst(count), dst, LIR_OprFact::illegalOpr); } |
aoqi@0 | 2593 | |
aoqi@0 | 2594 | void lcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_cmp_l2i, left, right, dst)); } |
aoqi@0 | 2595 | void fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less); |
aoqi@0 | 2596 | |
aoqi@0 | 2597 | void call_runtime_leaf(address routine, LIR_Opr tmp, LIR_Opr result, LIR_OprList* arguments) { |
aoqi@0 | 2598 | append(new LIR_OpRTCall(routine, tmp, result, arguments)); |
aoqi@0 | 2599 | } |
aoqi@0 | 2600 | |
aoqi@0 | 2601 | void call_runtime(address routine, LIR_Opr tmp, LIR_Opr result, |
aoqi@0 | 2602 | LIR_OprList* arguments, CodeEmitInfo* info) { |
aoqi@0 | 2603 | append(new LIR_OpRTCall(routine, tmp, result, arguments, info)); |
aoqi@0 | 2604 | } |
aoqi@0 | 2605 | |
aoqi@0 | 2606 | void load_stack_address_monitor(int monitor_ix, LIR_Opr dst) { append(new LIR_Op1(lir_monaddr, LIR_OprFact::intConst(monitor_ix), dst)); } |
aoqi@0 | 2607 | void unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub); |
aoqi@0 | 2608 | void lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info); |
aoqi@0 | 2609 | |
aoqi@0 | 2610 | void set_24bit_fpu() { append(new LIR_Op0(lir_24bit_FPU )); } |
aoqi@0 | 2611 | void restore_fpu() { append(new LIR_Op0(lir_reset_FPU )); } |
aoqi@0 | 2612 | void breakpoint() { append(new LIR_Op0(lir_breakpoint)); } |
aoqi@0 | 2613 | |
aoqi@0 | 2614 | void arraycopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) { append(new LIR_OpArrayCopy(src, src_pos, dst, dst_pos, length, tmp, expected_type, flags, info)); } |
aoqi@0 | 2615 | |
aoqi@0 | 2616 | void update_crc32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) { append(new LIR_OpUpdateCRC32(crc, val, res)); } |
aoqi@0 | 2617 | |
aoqi@0 | 2618 | void fpop_raw() { append(new LIR_Op0(lir_fpop_raw)); } |
aoqi@0 | 2619 | |
aoqi@0 | 2620 | void instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci); |
aoqi@0 | 2621 | void store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci); |
aoqi@0 | 2622 | |
aoqi@0 | 2623 | void checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, |
aoqi@0 | 2624 | LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, |
aoqi@0 | 2625 | CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, |
aoqi@0 | 2626 | ciMethod* profiled_method, int profiled_bci); |
aoqi@0 | 2627 | // MethodData* profiling |
aoqi@0 | 2628 | void profile_call(ciMethod* method, int bci, ciMethod* callee, LIR_Opr mdo, LIR_Opr recv, LIR_Opr t1, ciKlass* cha_klass) { |
aoqi@0 | 2629 | append(new LIR_OpProfileCall(method, bci, callee, mdo, recv, t1, cha_klass)); |
aoqi@0 | 2630 | } |
aoqi@0 | 2631 | void profile_type(LIR_Address* mdp, LIR_Opr obj, ciKlass* exact_klass, intptr_t current_klass, LIR_Opr tmp, bool not_null, bool no_conflict) { |
aoqi@0 | 2632 | append(new LIR_OpProfileType(LIR_OprFact::address(mdp), obj, exact_klass, current_klass, tmp, not_null, no_conflict)); |
aoqi@0 | 2633 | } |
aoqi@0 | 2634 | |
aoqi@0 | 2635 | void xadd(LIR_Opr src, LIR_Opr add, LIR_Opr res, LIR_Opr tmp) { append(new LIR_Op2(lir_xadd, src, add, res, tmp)); } |
aoqi@0 | 2636 | void xchg(LIR_Opr src, LIR_Opr set, LIR_Opr res, LIR_Opr tmp) { append(new LIR_Op2(lir_xchg, src, set, res, tmp)); } |
aoqi@0 | 2637 | #ifdef ASSERT |
aoqi@0 | 2638 | void lir_assert(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, const char* msg, bool halt) { append(new LIR_OpAssert(condition, opr1, opr2, msg, halt)); } |
aoqi@0 | 2639 | #endif |
aoqi@0 | 2640 | }; |
aoqi@0 | 2641 | |
aoqi@0 | 2642 | void print_LIR(BlockList* blocks); |
aoqi@0 | 2643 | |
aoqi@0 | 2644 | class LIR_InsertionBuffer : public CompilationResourceObj { |
aoqi@0 | 2645 | private: |
aoqi@0 | 2646 | LIR_List* _lir; // the lir list where ops of this buffer should be inserted later (NULL when uninitialized) |
aoqi@0 | 2647 | |
aoqi@0 | 2648 | // list of insertion points. index and count are stored alternately: |
aoqi@0 | 2649 | // _index_and_count[i * 2]: the index into lir list where "count" ops should be inserted |
aoqi@0 | 2650 | // _index_and_count[i * 2 + 1]: the number of ops to be inserted at index |
aoqi@0 | 2651 | intStack _index_and_count; |
aoqi@0 | 2652 | |
aoqi@0 | 2653 | // the LIR_Ops to be inserted |
aoqi@0 | 2654 | LIR_OpList _ops; |
aoqi@0 | 2655 | |
aoqi@0 | 2656 | void append_new(int index, int count) { _index_and_count.append(index); _index_and_count.append(count); } |
aoqi@0 | 2657 | void set_index_at(int i, int value) { _index_and_count.at_put((i << 1), value); } |
aoqi@0 | 2658 | void set_count_at(int i, int value) { _index_and_count.at_put((i << 1) + 1, value); } |
aoqi@0 | 2659 | |
aoqi@0 | 2660 | #ifdef ASSERT |
aoqi@0 | 2661 | void verify(); |
aoqi@0 | 2662 | #endif |
aoqi@0 | 2663 | public: |
aoqi@0 | 2664 | LIR_InsertionBuffer() : _lir(NULL), _index_and_count(8), _ops(8) { } |
aoqi@0 | 2665 | |
aoqi@0 | 2666 | // must be called before using the insertion buffer |
aoqi@0 | 2667 | void init(LIR_List* lir) { assert(!initialized(), "already initialized"); _lir = lir; _index_and_count.clear(); _ops.clear(); } |
aoqi@0 | 2668 | bool initialized() const { return _lir != NULL; } |
aoqi@0 | 2669 | // called automatically when the buffer is appended to the LIR_List |
aoqi@0 | 2670 | void finish() { _lir = NULL; } |
aoqi@0 | 2671 | |
aoqi@0 | 2672 | // accessors |
aoqi@0 | 2673 | LIR_List* lir_list() const { return _lir; } |
aoqi@0 | 2674 | int number_of_insertion_points() const { return _index_and_count.length() >> 1; } |
aoqi@0 | 2675 | int index_at(int i) const { return _index_and_count.at((i << 1)); } |
aoqi@0 | 2676 | int count_at(int i) const { return _index_and_count.at((i << 1) + 1); } |
aoqi@0 | 2677 | |
aoqi@0 | 2678 | int number_of_ops() const { return _ops.length(); } |
aoqi@0 | 2679 | LIR_Op* op_at(int i) const { return _ops.at(i); } |
aoqi@0 | 2680 | |
aoqi@0 | 2681 | // append an instruction to the buffer |
aoqi@0 | 2682 | void append(int index, LIR_Op* op); |
aoqi@0 | 2683 | |
aoqi@0 | 2684 | // instruction |
aoqi@0 | 2685 | void move(int index, LIR_Opr src, LIR_Opr dst, CodeEmitInfo* info = NULL) { append(index, new LIR_Op1(lir_move, src, dst, dst->type(), lir_patch_none, info)); } |
aoqi@0 | 2686 | }; |
aoqi@0 | 2687 | |
aoqi@0 | 2688 | |
aoqi@0 | 2689 | // |
aoqi@0 | 2690 | // LIR_OpVisitState is used for manipulating LIR_Ops in an abstract way. |
aoqi@0 | 2691 | // Calling a LIR_Op's visit function with a LIR_OpVisitState causes |
aoqi@0 | 2692 | // information about the input, output and temporaries used by the |
aoqi@0 | 2693 | // op to be recorded. It also records whether the op has call semantics |
aoqi@0 | 2694 | // and also records all the CodeEmitInfos used by this op. |
aoqi@0 | 2695 | // |
aoqi@0 | 2696 | |
aoqi@0 | 2697 | |
aoqi@0 | 2698 | class LIR_OpVisitState: public StackObj { |
aoqi@0 | 2699 | public: |
aoqi@0 | 2700 | typedef enum { inputMode, firstMode = inputMode, tempMode, outputMode, numModes, invalidMode = -1 } OprMode; |
aoqi@0 | 2701 | |
aoqi@0 | 2702 | enum { |
aoqi@0 | 2703 | maxNumberOfOperands = 20, |
aoqi@0 | 2704 | maxNumberOfInfos = 4 |
aoqi@0 | 2705 | }; |
aoqi@0 | 2706 | |
aoqi@0 | 2707 | private: |
aoqi@0 | 2708 | LIR_Op* _op; |
aoqi@0 | 2709 | |
aoqi@0 | 2710 | // optimization: the operands and infos are not stored in a variable-length |
aoqi@0 | 2711 | // list, but in a fixed-size array to save time of size checks and resizing |
aoqi@0 | 2712 | int _oprs_len[numModes]; |
aoqi@0 | 2713 | LIR_Opr* _oprs_new[numModes][maxNumberOfOperands]; |
aoqi@0 | 2714 | int _info_len; |
aoqi@0 | 2715 | CodeEmitInfo* _info_new[maxNumberOfInfos]; |
aoqi@0 | 2716 | |
aoqi@0 | 2717 | bool _has_call; |
aoqi@0 | 2718 | bool _has_slow_case; |
aoqi@0 | 2719 | |
aoqi@0 | 2720 | |
aoqi@0 | 2721 | // only include register operands |
aoqi@0 | 2722 | // addresses are decomposed to the base and index registers |
aoqi@0 | 2723 | // constants and stack operands are ignored |
aoqi@0 | 2724 | void append(LIR_Opr& opr, OprMode mode) { |
aoqi@0 | 2725 | assert(opr->is_valid(), "should not call this otherwise"); |
aoqi@0 | 2726 | assert(mode >= 0 && mode < numModes, "bad mode"); |
aoqi@0 | 2727 | |
aoqi@0 | 2728 | if (opr->is_register()) { |
aoqi@0 | 2729 | assert(_oprs_len[mode] < maxNumberOfOperands, "array overflow"); |
aoqi@0 | 2730 | _oprs_new[mode][_oprs_len[mode]++] = &opr; |
aoqi@0 | 2731 | |
aoqi@0 | 2732 | } else if (opr->is_pointer()) { |
aoqi@0 | 2733 | LIR_Address* address = opr->as_address_ptr(); |
aoqi@0 | 2734 | if (address != NULL) { |
aoqi@0 | 2735 | // special handling for addresses: add base and index register of the address |
aoqi@0 | 2736 | // both are always input operands or temp if we want to extend |
aoqi@0 | 2737 | // their liveness! |
aoqi@0 | 2738 | if (mode == outputMode) { |
aoqi@0 | 2739 | mode = inputMode; |
aoqi@0 | 2740 | } |
aoqi@0 | 2741 | assert (mode == inputMode || mode == tempMode, "input or temp only for addresses"); |
aoqi@0 | 2742 | if (address->_base->is_valid()) { |
aoqi@0 | 2743 | assert(address->_base->is_register(), "must be"); |
aoqi@0 | 2744 | assert(_oprs_len[mode] < maxNumberOfOperands, "array overflow"); |
aoqi@0 | 2745 | _oprs_new[mode][_oprs_len[mode]++] = &address->_base; |
aoqi@0 | 2746 | } |
aoqi@0 | 2747 | if (address->_index->is_valid()) { |
aoqi@0 | 2748 | assert(address->_index->is_register(), "must be"); |
aoqi@0 | 2749 | assert(_oprs_len[mode] < maxNumberOfOperands, "array overflow"); |
aoqi@0 | 2750 | _oprs_new[mode][_oprs_len[mode]++] = &address->_index; |
aoqi@0 | 2751 | } |
aoqi@0 | 2752 | |
aoqi@0 | 2753 | } else { |
aoqi@0 | 2754 | assert(opr->is_constant(), "constant operands are not processed"); |
aoqi@0 | 2755 | } |
aoqi@0 | 2756 | } else { |
aoqi@0 | 2757 | assert(opr->is_stack(), "stack operands are not processed"); |
aoqi@0 | 2758 | } |
aoqi@0 | 2759 | } |
aoqi@0 | 2760 | |
aoqi@0 | 2761 | void append(CodeEmitInfo* info) { |
aoqi@0 | 2762 | assert(info != NULL, "should not call this otherwise"); |
aoqi@0 | 2763 | assert(_info_len < maxNumberOfInfos, "array overflow"); |
aoqi@0 | 2764 | _info_new[_info_len++] = info; |
aoqi@0 | 2765 | } |
aoqi@0 | 2766 | |
aoqi@0 | 2767 | public: |
aoqi@0 | 2768 | LIR_OpVisitState() { reset(); } |
aoqi@0 | 2769 | |
aoqi@0 | 2770 | LIR_Op* op() const { return _op; } |
aoqi@0 | 2771 | void set_op(LIR_Op* op) { reset(); _op = op; } |
aoqi@0 | 2772 | |
aoqi@0 | 2773 | bool has_call() const { return _has_call; } |
aoqi@0 | 2774 | bool has_slow_case() const { return _has_slow_case; } |
aoqi@0 | 2775 | |
aoqi@0 | 2776 | void reset() { |
aoqi@0 | 2777 | _op = NULL; |
aoqi@0 | 2778 | _has_call = false; |
aoqi@0 | 2779 | _has_slow_case = false; |
aoqi@0 | 2780 | |
aoqi@0 | 2781 | _oprs_len[inputMode] = 0; |
aoqi@0 | 2782 | _oprs_len[tempMode] = 0; |
aoqi@0 | 2783 | _oprs_len[outputMode] = 0; |
aoqi@0 | 2784 | _info_len = 0; |
aoqi@0 | 2785 | } |
aoqi@0 | 2786 | |
aoqi@0 | 2787 | |
aoqi@0 | 2788 | int opr_count(OprMode mode) const { |
aoqi@0 | 2789 | assert(mode >= 0 && mode < numModes, "bad mode"); |
aoqi@0 | 2790 | return _oprs_len[mode]; |
aoqi@0 | 2791 | } |
aoqi@0 | 2792 | |
aoqi@0 | 2793 | LIR_Opr opr_at(OprMode mode, int index) const { |
aoqi@0 | 2794 | assert(mode >= 0 && mode < numModes, "bad mode"); |
aoqi@0 | 2795 | assert(index >= 0 && index < _oprs_len[mode], "index out of bound"); |
aoqi@0 | 2796 | return *_oprs_new[mode][index]; |
aoqi@0 | 2797 | } |
aoqi@0 | 2798 | |
aoqi@0 | 2799 | void set_opr_at(OprMode mode, int index, LIR_Opr opr) const { |
aoqi@0 | 2800 | assert(mode >= 0 && mode < numModes, "bad mode"); |
aoqi@0 | 2801 | assert(index >= 0 && index < _oprs_len[mode], "index out of bound"); |
aoqi@0 | 2802 | *_oprs_new[mode][index] = opr; |
aoqi@0 | 2803 | } |
aoqi@0 | 2804 | |
aoqi@0 | 2805 | int info_count() const { |
aoqi@0 | 2806 | return _info_len; |
aoqi@0 | 2807 | } |
aoqi@0 | 2808 | |
aoqi@0 | 2809 | CodeEmitInfo* info_at(int index) const { |
aoqi@0 | 2810 | assert(index < _info_len, "index out of bounds"); |
aoqi@0 | 2811 | return _info_new[index]; |
aoqi@0 | 2812 | } |
aoqi@0 | 2813 | |
aoqi@0 | 2814 | XHandlers* all_xhandler(); |
aoqi@0 | 2815 | |
aoqi@0 | 2816 | // collects all register operands of the instruction |
aoqi@0 | 2817 | void visit(LIR_Op* op); |
aoqi@0 | 2818 | |
aoqi@0 | 2819 | #ifdef ASSERT |
aoqi@0 | 2820 | // check that an operation has no operands |
aoqi@0 | 2821 | bool no_operands(LIR_Op* op); |
aoqi@0 | 2822 | #endif |
aoqi@0 | 2823 | |
aoqi@0 | 2824 | // LIR_Op visitor functions use these to fill in the state |
aoqi@0 | 2825 | void do_input(LIR_Opr& opr) { append(opr, LIR_OpVisitState::inputMode); } |
aoqi@0 | 2826 | void do_output(LIR_Opr& opr) { append(opr, LIR_OpVisitState::outputMode); } |
aoqi@0 | 2827 | void do_temp(LIR_Opr& opr) { append(opr, LIR_OpVisitState::tempMode); } |
aoqi@0 | 2828 | void do_info(CodeEmitInfo* info) { append(info); } |
aoqi@0 | 2829 | |
aoqi@0 | 2830 | void do_stub(CodeStub* stub); |
aoqi@0 | 2831 | void do_call() { _has_call = true; } |
aoqi@0 | 2832 | void do_slow_case() { _has_slow_case = true; } |
aoqi@0 | 2833 | void do_slow_case(CodeEmitInfo* info) { |
aoqi@0 | 2834 | _has_slow_case = true; |
aoqi@0 | 2835 | append(info); |
aoqi@0 | 2836 | } |
aoqi@0 | 2837 | }; |
aoqi@0 | 2838 | |
aoqi@0 | 2839 | |
aoqi@0 | 2840 | inline LIR_Opr LIR_OprDesc::illegalOpr() { return LIR_OprFact::illegalOpr; }; |
aoqi@0 | 2841 | |
aoqi@0 | 2842 | #endif // SHARE_VM_C1_C1_LIR_HPP |