Tue, 21 Apr 2009 11:16:30 -0700
6822110: Add AddressLiteral class on SPARC
Summary: The Address class on SPARC currently handles both, addresses and address literals, what makes the Address class more complicated than it has to be.
Reviewed-by: never, kvn
duke@435 | 1 | /* |
twisti@1162 | 2 | * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | # include "incls/_precompiled.incl" |
duke@435 | 26 | # include "incls/_nativeInst_sparc.cpp.incl" |
duke@435 | 27 | |
duke@435 | 28 | |
kamg@551 | 29 | bool NativeInstruction::is_dtrace_trap() { |
kamg@551 | 30 | return !is_nop(); |
kamg@551 | 31 | } |
kamg@551 | 32 | |
duke@435 | 33 | void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) { |
duke@435 | 34 | ResourceMark rm; |
duke@435 | 35 | CodeBuffer buf(instaddr, 10 * BytesPerInstWord ); |
duke@435 | 36 | MacroAssembler* _masm = new MacroAssembler(&buf); |
duke@435 | 37 | Register destreg; |
duke@435 | 38 | |
duke@435 | 39 | destreg = inv_rd(*(unsigned int *)instaddr); |
duke@435 | 40 | // Generate a the new sequence |
twisti@1162 | 41 | _masm->patchable_sethi(x, destreg); |
duke@435 | 42 | ICache::invalidate_range(instaddr, 7 * BytesPerInstWord); |
duke@435 | 43 | } |
duke@435 | 44 | |
duke@435 | 45 | void NativeInstruction::verify() { |
duke@435 | 46 | // make sure code pattern is actually an instruction address |
duke@435 | 47 | address addr = addr_at(0); |
duke@435 | 48 | if (addr == 0 || ((intptr_t)addr & 3) != 0) { |
duke@435 | 49 | fatal("not an instruction address"); |
duke@435 | 50 | } |
duke@435 | 51 | } |
duke@435 | 52 | |
duke@435 | 53 | void NativeInstruction::print() { |
duke@435 | 54 | tty->print_cr(INTPTR_FORMAT ": 0x%x", addr_at(0), long_at(0)); |
duke@435 | 55 | } |
duke@435 | 56 | |
duke@435 | 57 | void NativeInstruction::set_long_at(int offset, int i) { |
duke@435 | 58 | address addr = addr_at(offset); |
duke@435 | 59 | *(int*)addr = i; |
duke@435 | 60 | ICache::invalidate_word(addr); |
duke@435 | 61 | } |
duke@435 | 62 | |
duke@435 | 63 | void NativeInstruction::set_jlong_at(int offset, jlong i) { |
duke@435 | 64 | address addr = addr_at(offset); |
duke@435 | 65 | *(jlong*)addr = i; |
duke@435 | 66 | // Don't need to invalidate 2 words here, because |
duke@435 | 67 | // the flush instruction operates on doublewords. |
duke@435 | 68 | ICache::invalidate_word(addr); |
duke@435 | 69 | } |
duke@435 | 70 | |
duke@435 | 71 | void NativeInstruction::set_addr_at(int offset, address x) { |
duke@435 | 72 | address addr = addr_at(offset); |
duke@435 | 73 | assert( ((intptr_t)addr & (wordSize-1)) == 0, "set_addr_at bad address alignment"); |
duke@435 | 74 | *(uintptr_t*)addr = (uintptr_t)x; |
duke@435 | 75 | // Don't need to invalidate 2 words here in the 64-bit case, |
duke@435 | 76 | // because the flush instruction operates on doublewords. |
duke@435 | 77 | ICache::invalidate_word(addr); |
duke@435 | 78 | // The Intel code has this assertion for NativeCall::set_destination, |
duke@435 | 79 | // NativeMovConstReg::set_data, NativeMovRegMem::set_offset, |
duke@435 | 80 | // NativeJump::set_jump_destination, and NativePushImm32::set_data |
duke@435 | 81 | //assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction") |
duke@435 | 82 | } |
duke@435 | 83 | |
duke@435 | 84 | bool NativeInstruction::is_zero_test(Register ®) { |
duke@435 | 85 | int x = long_at(0); |
duke@435 | 86 | Assembler::op3s temp = (Assembler::op3s) (Assembler::sub_op3 | Assembler::cc_bit_op3); |
duke@435 | 87 | if (is_op3(x, temp, Assembler::arith_op) && |
duke@435 | 88 | inv_immed(x) && inv_rd(x) == G0) { |
duke@435 | 89 | if (inv_rs1(x) == G0) { |
duke@435 | 90 | reg = inv_rs2(x); |
duke@435 | 91 | return true; |
duke@435 | 92 | } else if (inv_rs2(x) == G0) { |
duke@435 | 93 | reg = inv_rs1(x); |
duke@435 | 94 | return true; |
duke@435 | 95 | } |
duke@435 | 96 | } |
duke@435 | 97 | return false; |
duke@435 | 98 | } |
duke@435 | 99 | |
duke@435 | 100 | bool NativeInstruction::is_load_store_with_small_offset(Register reg) { |
duke@435 | 101 | int x = long_at(0); |
duke@435 | 102 | if (is_op(x, Assembler::ldst_op) && |
duke@435 | 103 | inv_rs1(x) == reg && inv_immed(x)) { |
duke@435 | 104 | return true; |
duke@435 | 105 | } |
duke@435 | 106 | return false; |
duke@435 | 107 | } |
duke@435 | 108 | |
duke@435 | 109 | void NativeCall::verify() { |
duke@435 | 110 | NativeInstruction::verify(); |
duke@435 | 111 | // make sure code pattern is actually a call instruction |
duke@435 | 112 | if (!is_op(long_at(0), Assembler::call_op)) { |
duke@435 | 113 | fatal("not a call"); |
duke@435 | 114 | } |
duke@435 | 115 | } |
duke@435 | 116 | |
duke@435 | 117 | void NativeCall::print() { |
duke@435 | 118 | tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination()); |
duke@435 | 119 | } |
duke@435 | 120 | |
duke@435 | 121 | |
duke@435 | 122 | // MT-safe patching of a call instruction (and following word). |
duke@435 | 123 | // First patches the second word, and then atomicly replaces |
duke@435 | 124 | // the first word with the first new instruction word. |
duke@435 | 125 | // Other processors might briefly see the old first word |
duke@435 | 126 | // followed by the new second word. This is OK if the old |
duke@435 | 127 | // second word is harmless, and the new second word may be |
duke@435 | 128 | // harmlessly executed in the delay slot of the call. |
duke@435 | 129 | void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) { |
duke@435 | 130 | assert(Patching_lock->is_locked() || |
duke@435 | 131 | SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); |
duke@435 | 132 | assert (instr_addr != NULL, "illegal address for code patching"); |
duke@435 | 133 | NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call |
duke@435 | 134 | assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8"); |
duke@435 | 135 | int i0 = ((int*)code_buffer)[0]; |
duke@435 | 136 | int i1 = ((int*)code_buffer)[1]; |
duke@435 | 137 | int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord); |
duke@435 | 138 | assert(inv_op(*contention_addr) == Assembler::arith_op || |
duke@435 | 139 | *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(), |
duke@435 | 140 | "must not interfere with original call"); |
duke@435 | 141 | // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order |
duke@435 | 142 | n_call->set_long_at(1*BytesPerInstWord, i1); |
duke@435 | 143 | n_call->set_long_at(0*BytesPerInstWord, i0); |
duke@435 | 144 | // NOTE: It is possible that another thread T will execute |
duke@435 | 145 | // only the second patched word. |
duke@435 | 146 | // In other words, since the original instruction is this |
duke@435 | 147 | // call patching_stub; nop (NativeCall) |
duke@435 | 148 | // and the new sequence from the buffer is this: |
duke@435 | 149 | // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg) |
duke@435 | 150 | // what T will execute is this: |
duke@435 | 151 | // call patching_stub; add %r, %lo(K), %r |
duke@435 | 152 | // thereby putting garbage into %r before calling the patching stub. |
duke@435 | 153 | // This is OK, because the patching stub ignores the value of %r. |
duke@435 | 154 | |
duke@435 | 155 | // Make sure the first-patched instruction, which may co-exist |
duke@435 | 156 | // briefly with the call, will do something harmless. |
duke@435 | 157 | assert(inv_op(*contention_addr) == Assembler::arith_op || |
duke@435 | 158 | *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(), |
duke@435 | 159 | "must not interfere with original call"); |
duke@435 | 160 | } |
duke@435 | 161 | |
duke@435 | 162 | // Similar to replace_mt_safe, but just changes the destination. The |
duke@435 | 163 | // important thing is that free-running threads are able to execute this |
duke@435 | 164 | // call instruction at all times. Thus, the displacement field must be |
duke@435 | 165 | // instruction-word-aligned. This is always true on SPARC. |
duke@435 | 166 | // |
duke@435 | 167 | // Used in the runtime linkage of calls; see class CompiledIC. |
duke@435 | 168 | void NativeCall::set_destination_mt_safe(address dest) { |
duke@435 | 169 | assert(Patching_lock->is_locked() || |
duke@435 | 170 | SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); |
duke@435 | 171 | // set_destination uses set_long_at which does the ICache::invalidate |
duke@435 | 172 | set_destination(dest); |
duke@435 | 173 | } |
duke@435 | 174 | |
duke@435 | 175 | // Code for unit testing implementation of NativeCall class |
duke@435 | 176 | void NativeCall::test() { |
duke@435 | 177 | #ifdef ASSERT |
duke@435 | 178 | ResourceMark rm; |
duke@435 | 179 | CodeBuffer cb("test", 100, 100); |
duke@435 | 180 | MacroAssembler* a = new MacroAssembler(&cb); |
duke@435 | 181 | NativeCall *nc; |
duke@435 | 182 | uint idx; |
duke@435 | 183 | int offsets[] = { |
duke@435 | 184 | 0x0, |
duke@435 | 185 | 0xfffffff0, |
duke@435 | 186 | 0x7ffffff0, |
duke@435 | 187 | 0x80000000, |
duke@435 | 188 | 0x20, |
duke@435 | 189 | 0x4000, |
duke@435 | 190 | }; |
duke@435 | 191 | |
duke@435 | 192 | VM_Version::allow_all(); |
duke@435 | 193 | |
duke@435 | 194 | a->call( a->pc(), relocInfo::none ); |
duke@435 | 195 | a->delayed()->nop(); |
duke@435 | 196 | nc = nativeCall_at( cb.code_begin() ); |
duke@435 | 197 | nc->print(); |
duke@435 | 198 | |
duke@435 | 199 | nc = nativeCall_overwriting_at( nc->next_instruction_address() ); |
duke@435 | 200 | for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { |
duke@435 | 201 | nc->set_destination( cb.code_begin() + offsets[idx] ); |
duke@435 | 202 | assert(nc->destination() == (cb.code_begin() + offsets[idx]), "check unit test"); |
duke@435 | 203 | nc->print(); |
duke@435 | 204 | } |
duke@435 | 205 | |
duke@435 | 206 | nc = nativeCall_before( cb.code_begin() + 8 ); |
duke@435 | 207 | nc->print(); |
duke@435 | 208 | |
duke@435 | 209 | VM_Version::revert(); |
duke@435 | 210 | #endif |
duke@435 | 211 | } |
duke@435 | 212 | // End code for unit testing implementation of NativeCall class |
duke@435 | 213 | |
duke@435 | 214 | //------------------------------------------------------------------- |
duke@435 | 215 | |
duke@435 | 216 | #ifdef _LP64 |
duke@435 | 217 | |
duke@435 | 218 | void NativeFarCall::set_destination(address dest) { |
duke@435 | 219 | // Address materialized in the instruction stream, so nothing to do. |
duke@435 | 220 | return; |
duke@435 | 221 | #if 0 // What we'd do if we really did want to change the destination |
duke@435 | 222 | if (destination() == dest) { |
duke@435 | 223 | return; |
duke@435 | 224 | } |
duke@435 | 225 | ResourceMark rm; |
duke@435 | 226 | CodeBuffer buf(addr_at(0), instruction_size + 1); |
duke@435 | 227 | MacroAssembler* _masm = new MacroAssembler(&buf); |
duke@435 | 228 | // Generate the new sequence |
twisti@1162 | 229 | AddressLiteral(dest); |
twisti@1162 | 230 | _masm->jumpl_to(dest, O7, O7); |
duke@435 | 231 | ICache::invalidate_range(addr_at(0), instruction_size ); |
duke@435 | 232 | #endif |
duke@435 | 233 | } |
duke@435 | 234 | |
duke@435 | 235 | void NativeFarCall::verify() { |
duke@435 | 236 | // make sure code pattern is actually a jumpl_to instruction |
duke@435 | 237 | assert((int)instruction_size == (int)NativeJump::instruction_size, "same as jump_to"); |
duke@435 | 238 | assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); |
duke@435 | 239 | nativeJump_at(addr_at(0))->verify(); |
duke@435 | 240 | } |
duke@435 | 241 | |
duke@435 | 242 | bool NativeFarCall::is_call_at(address instr) { |
duke@435 | 243 | return nativeInstruction_at(instr)->is_sethi(); |
duke@435 | 244 | } |
duke@435 | 245 | |
duke@435 | 246 | void NativeFarCall::print() { |
duke@435 | 247 | tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination()); |
duke@435 | 248 | } |
duke@435 | 249 | |
duke@435 | 250 | bool NativeFarCall::destination_is_compiled_verified_entry_point() { |
duke@435 | 251 | nmethod* callee = CodeCache::find_nmethod(destination()); |
duke@435 | 252 | if (callee == NULL) { |
duke@435 | 253 | return false; |
duke@435 | 254 | } else { |
duke@435 | 255 | return destination() == callee->verified_entry_point(); |
duke@435 | 256 | } |
duke@435 | 257 | } |
duke@435 | 258 | |
duke@435 | 259 | // MT-safe patching of a far call. |
duke@435 | 260 | void NativeFarCall::replace_mt_safe(address instr_addr, address code_buffer) { |
duke@435 | 261 | Unimplemented(); |
duke@435 | 262 | } |
duke@435 | 263 | |
duke@435 | 264 | // Code for unit testing implementation of NativeFarCall class |
duke@435 | 265 | void NativeFarCall::test() { |
duke@435 | 266 | Unimplemented(); |
duke@435 | 267 | } |
duke@435 | 268 | // End code for unit testing implementation of NativeFarCall class |
duke@435 | 269 | |
duke@435 | 270 | #endif // _LP64 |
duke@435 | 271 | |
duke@435 | 272 | //------------------------------------------------------------------- |
duke@435 | 273 | |
duke@435 | 274 | |
duke@435 | 275 | void NativeMovConstReg::verify() { |
duke@435 | 276 | NativeInstruction::verify(); |
duke@435 | 277 | // make sure code pattern is actually a "set_oop" synthetic instruction |
duke@435 | 278 | // see MacroAssembler::set_oop() |
duke@435 | 279 | int i0 = long_at(sethi_offset); |
duke@435 | 280 | int i1 = long_at(add_offset); |
duke@435 | 281 | |
duke@435 | 282 | // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg" |
duke@435 | 283 | Register rd = inv_rd(i0); |
duke@435 | 284 | #ifndef _LP64 |
duke@435 | 285 | if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 && |
duke@435 | 286 | is_op3(i1, Assembler::add_op3, Assembler::arith_op) && |
duke@435 | 287 | inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) && |
duke@435 | 288 | rd == inv_rs1(i1) && rd == inv_rd(i1))) { |
duke@435 | 289 | fatal("not a set_oop"); |
duke@435 | 290 | } |
duke@435 | 291 | #else |
duke@435 | 292 | if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { |
duke@435 | 293 | fatal("not a set_oop"); |
duke@435 | 294 | } |
duke@435 | 295 | #endif |
duke@435 | 296 | } |
duke@435 | 297 | |
duke@435 | 298 | |
duke@435 | 299 | void NativeMovConstReg::print() { |
duke@435 | 300 | tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data()); |
duke@435 | 301 | } |
duke@435 | 302 | |
duke@435 | 303 | |
duke@435 | 304 | #ifdef _LP64 |
duke@435 | 305 | intptr_t NativeMovConstReg::data() const { |
duke@435 | 306 | return data64(addr_at(sethi_offset), long_at(add_offset)); |
duke@435 | 307 | } |
duke@435 | 308 | #else |
duke@435 | 309 | intptr_t NativeMovConstReg::data() const { |
duke@435 | 310 | return data32(long_at(sethi_offset), long_at(add_offset)); |
duke@435 | 311 | } |
duke@435 | 312 | #endif |
duke@435 | 313 | |
duke@435 | 314 | |
duke@435 | 315 | void NativeMovConstReg::set_data(intptr_t x) { |
duke@435 | 316 | #ifdef _LP64 |
duke@435 | 317 | set_data64_sethi(addr_at(sethi_offset), x); |
duke@435 | 318 | #else |
duke@435 | 319 | set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x)); |
duke@435 | 320 | #endif |
duke@435 | 321 | set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x)); |
duke@435 | 322 | |
duke@435 | 323 | // also store the value into an oop_Relocation cell, if any |
duke@435 | 324 | CodeBlob* nm = CodeCache::find_blob(instruction_address()); |
duke@435 | 325 | if (nm != NULL) { |
duke@435 | 326 | RelocIterator iter(nm, instruction_address(), next_instruction_address()); |
duke@435 | 327 | oop* oop_addr = NULL; |
duke@435 | 328 | while (iter.next()) { |
duke@435 | 329 | if (iter.type() == relocInfo::oop_type) { |
duke@435 | 330 | oop_Relocation *r = iter.oop_reloc(); |
duke@435 | 331 | if (oop_addr == NULL) { |
duke@435 | 332 | oop_addr = r->oop_addr(); |
duke@435 | 333 | *oop_addr = (oop)x; |
duke@435 | 334 | } else { |
duke@435 | 335 | assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); |
duke@435 | 336 | } |
duke@435 | 337 | } |
duke@435 | 338 | } |
duke@435 | 339 | } |
duke@435 | 340 | } |
duke@435 | 341 | |
duke@435 | 342 | |
duke@435 | 343 | // Code for unit testing implementation of NativeMovConstReg class |
duke@435 | 344 | void NativeMovConstReg::test() { |
duke@435 | 345 | #ifdef ASSERT |
duke@435 | 346 | ResourceMark rm; |
duke@435 | 347 | CodeBuffer cb("test", 100, 100); |
duke@435 | 348 | MacroAssembler* a = new MacroAssembler(&cb); |
duke@435 | 349 | NativeMovConstReg* nm; |
duke@435 | 350 | uint idx; |
duke@435 | 351 | int offsets[] = { |
duke@435 | 352 | 0x0, |
duke@435 | 353 | 0x7fffffff, |
duke@435 | 354 | 0x80000000, |
duke@435 | 355 | 0xffffffff, |
duke@435 | 356 | 0x20, |
duke@435 | 357 | 4096, |
duke@435 | 358 | 4097, |
duke@435 | 359 | }; |
duke@435 | 360 | |
duke@435 | 361 | VM_Version::allow_all(); |
duke@435 | 362 | |
twisti@1162 | 363 | AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type); |
twisti@1162 | 364 | a->sethi(al1, I3); |
twisti@1162 | 365 | a->add(I3, al1.low10(), I3); |
twisti@1162 | 366 | AddressLiteral al2(0xccccdddd, relocInfo::external_word_type); |
twisti@1162 | 367 | a->sethi(al2, O2); |
twisti@1162 | 368 | a->add(O2, al2.low10(), O2); |
duke@435 | 369 | |
duke@435 | 370 | nm = nativeMovConstReg_at( cb.code_begin() ); |
duke@435 | 371 | nm->print(); |
duke@435 | 372 | |
duke@435 | 373 | nm = nativeMovConstReg_at( nm->next_instruction_address() ); |
duke@435 | 374 | for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { |
duke@435 | 375 | nm->set_data( offsets[idx] ); |
duke@435 | 376 | assert(nm->data() == offsets[idx], "check unit test"); |
duke@435 | 377 | } |
duke@435 | 378 | nm->print(); |
duke@435 | 379 | |
duke@435 | 380 | VM_Version::revert(); |
duke@435 | 381 | #endif |
duke@435 | 382 | } |
duke@435 | 383 | // End code for unit testing implementation of NativeMovConstReg class |
duke@435 | 384 | |
duke@435 | 385 | //------------------------------------------------------------------- |
duke@435 | 386 | |
duke@435 | 387 | void NativeMovConstRegPatching::verify() { |
duke@435 | 388 | NativeInstruction::verify(); |
duke@435 | 389 | // Make sure code pattern is sethi/nop/add. |
duke@435 | 390 | int i0 = long_at(sethi_offset); |
duke@435 | 391 | int i1 = long_at(nop_offset); |
duke@435 | 392 | int i2 = long_at(add_offset); |
duke@435 | 393 | assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); |
duke@435 | 394 | |
duke@435 | 395 | // Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg" |
duke@435 | 396 | // The casual reader should note that on Sparc a nop is a special case if sethi |
duke@435 | 397 | // in which the destination register is %g0. |
duke@435 | 398 | Register rd0 = inv_rd(i0); |
duke@435 | 399 | Register rd1 = inv_rd(i1); |
duke@435 | 400 | if (!(is_op2(i0, Assembler::sethi_op2) && rd0 != G0 && |
duke@435 | 401 | is_op2(i1, Assembler::sethi_op2) && rd1 == G0 && // nop is a special case of sethi |
duke@435 | 402 | is_op3(i2, Assembler::add_op3, Assembler::arith_op) && |
duke@435 | 403 | inv_immed(i2) && (unsigned)get_simm13(i2) < (1 << 10) && |
duke@435 | 404 | rd0 == inv_rs1(i2) && rd0 == inv_rd(i2))) { |
duke@435 | 405 | fatal("not a set_oop"); |
duke@435 | 406 | } |
duke@435 | 407 | } |
duke@435 | 408 | |
duke@435 | 409 | |
duke@435 | 410 | void NativeMovConstRegPatching::print() { |
duke@435 | 411 | tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data()); |
duke@435 | 412 | } |
duke@435 | 413 | |
duke@435 | 414 | |
duke@435 | 415 | int NativeMovConstRegPatching::data() const { |
duke@435 | 416 | #ifdef _LP64 |
duke@435 | 417 | return data64(addr_at(sethi_offset), long_at(add_offset)); |
duke@435 | 418 | #else |
duke@435 | 419 | return data32(long_at(sethi_offset), long_at(add_offset)); |
duke@435 | 420 | #endif |
duke@435 | 421 | } |
duke@435 | 422 | |
duke@435 | 423 | |
duke@435 | 424 | void NativeMovConstRegPatching::set_data(int x) { |
duke@435 | 425 | #ifdef _LP64 |
duke@435 | 426 | set_data64_sethi(addr_at(sethi_offset), x); |
duke@435 | 427 | #else |
duke@435 | 428 | set_long_at(sethi_offset, set_data32_sethi(long_at(sethi_offset), x)); |
duke@435 | 429 | #endif |
duke@435 | 430 | set_long_at(add_offset, set_data32_simm13(long_at(add_offset), x)); |
duke@435 | 431 | |
duke@435 | 432 | // also store the value into an oop_Relocation cell, if any |
duke@435 | 433 | CodeBlob* nm = CodeCache::find_blob(instruction_address()); |
duke@435 | 434 | if (nm != NULL) { |
duke@435 | 435 | RelocIterator iter(nm, instruction_address(), next_instruction_address()); |
duke@435 | 436 | oop* oop_addr = NULL; |
duke@435 | 437 | while (iter.next()) { |
duke@435 | 438 | if (iter.type() == relocInfo::oop_type) { |
duke@435 | 439 | oop_Relocation *r = iter.oop_reloc(); |
duke@435 | 440 | if (oop_addr == NULL) { |
duke@435 | 441 | oop_addr = r->oop_addr(); |
duke@435 | 442 | *oop_addr = (oop)x; |
duke@435 | 443 | } else { |
duke@435 | 444 | assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); |
duke@435 | 445 | } |
duke@435 | 446 | } |
duke@435 | 447 | } |
duke@435 | 448 | } |
duke@435 | 449 | } |
duke@435 | 450 | |
duke@435 | 451 | |
duke@435 | 452 | // Code for unit testing implementation of NativeMovConstRegPatching class |
duke@435 | 453 | void NativeMovConstRegPatching::test() { |
duke@435 | 454 | #ifdef ASSERT |
duke@435 | 455 | ResourceMark rm; |
duke@435 | 456 | CodeBuffer cb("test", 100, 100); |
duke@435 | 457 | MacroAssembler* a = new MacroAssembler(&cb); |
duke@435 | 458 | NativeMovConstRegPatching* nm; |
duke@435 | 459 | uint idx; |
duke@435 | 460 | int offsets[] = { |
duke@435 | 461 | 0x0, |
duke@435 | 462 | 0x7fffffff, |
duke@435 | 463 | 0x80000000, |
duke@435 | 464 | 0xffffffff, |
duke@435 | 465 | 0x20, |
duke@435 | 466 | 4096, |
duke@435 | 467 | 4097, |
duke@435 | 468 | }; |
duke@435 | 469 | |
duke@435 | 470 | VM_Version::allow_all(); |
duke@435 | 471 | |
twisti@1162 | 472 | AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type); |
twisti@1162 | 473 | a->sethi(al1, I3); |
duke@435 | 474 | a->nop(); |
twisti@1162 | 475 | a->add(I3, al1.low10(), I3); |
twisti@1162 | 476 | AddressLiteral al2(0xccccdddd, relocInfo::external_word_type); |
twisti@1162 | 477 | a->sethi(al2, O2); |
duke@435 | 478 | a->nop(); |
twisti@1162 | 479 | a->add(O2, al2.low10(), O2); |
duke@435 | 480 | |
duke@435 | 481 | nm = nativeMovConstRegPatching_at( cb.code_begin() ); |
duke@435 | 482 | nm->print(); |
duke@435 | 483 | |
duke@435 | 484 | nm = nativeMovConstRegPatching_at( nm->next_instruction_address() ); |
duke@435 | 485 | for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { |
duke@435 | 486 | nm->set_data( offsets[idx] ); |
duke@435 | 487 | assert(nm->data() == offsets[idx], "check unit test"); |
duke@435 | 488 | } |
duke@435 | 489 | nm->print(); |
duke@435 | 490 | |
duke@435 | 491 | VM_Version::revert(); |
duke@435 | 492 | #endif // ASSERT |
duke@435 | 493 | } |
duke@435 | 494 | // End code for unit testing implementation of NativeMovConstRegPatching class |
duke@435 | 495 | |
duke@435 | 496 | |
duke@435 | 497 | //------------------------------------------------------------------- |
duke@435 | 498 | |
duke@435 | 499 | |
duke@435 | 500 | void NativeMovRegMem::copy_instruction_to(address new_instruction_address) { |
duke@435 | 501 | Untested("copy_instruction_to"); |
duke@435 | 502 | int instruction_size = next_instruction_address() - instruction_address(); |
duke@435 | 503 | for (int i = 0; i < instruction_size; i += BytesPerInstWord) { |
duke@435 | 504 | *(int*)(new_instruction_address + i) = *(int*)(address(this) + i); |
duke@435 | 505 | } |
duke@435 | 506 | } |
duke@435 | 507 | |
duke@435 | 508 | |
duke@435 | 509 | void NativeMovRegMem::verify() { |
duke@435 | 510 | NativeInstruction::verify(); |
duke@435 | 511 | // make sure code pattern is actually a "ld" or "st" of some sort. |
duke@435 | 512 | int i0 = long_at(0); |
duke@435 | 513 | int op3 = inv_op3(i0); |
duke@435 | 514 | |
duke@435 | 515 | assert((int)add_offset == NativeMovConstReg::add_offset, "sethi size ok"); |
duke@435 | 516 | |
duke@435 | 517 | if (!(is_op(i0, Assembler::ldst_op) && |
duke@435 | 518 | inv_immed(i0) && |
duke@435 | 519 | 0 != (op3 < op3_ldst_int_limit |
duke@435 | 520 | ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) |
duke@435 | 521 | : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) |
duke@435 | 522 | { |
duke@435 | 523 | int i1 = long_at(ldst_offset); |
duke@435 | 524 | Register rd = inv_rd(i0); |
duke@435 | 525 | |
duke@435 | 526 | op3 = inv_op3(i1); |
duke@435 | 527 | if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) && |
duke@435 | 528 | 0 != (op3 < op3_ldst_int_limit |
duke@435 | 529 | ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) |
duke@435 | 530 | : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) { |
duke@435 | 531 | fatal("not a ld* or st* op"); |
duke@435 | 532 | } |
duke@435 | 533 | } |
duke@435 | 534 | } |
duke@435 | 535 | |
duke@435 | 536 | |
duke@435 | 537 | void NativeMovRegMem::print() { |
duke@435 | 538 | if (is_immediate()) { |
duke@435 | 539 | tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset()); |
duke@435 | 540 | } else { |
duke@435 | 541 | tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address()); |
duke@435 | 542 | } |
duke@435 | 543 | } |
duke@435 | 544 | |
duke@435 | 545 | |
duke@435 | 546 | // Code for unit testing implementation of NativeMovRegMem class |
duke@435 | 547 | void NativeMovRegMem::test() { |
duke@435 | 548 | #ifdef ASSERT |
duke@435 | 549 | ResourceMark rm; |
duke@435 | 550 | CodeBuffer cb("test", 1000, 1000); |
duke@435 | 551 | MacroAssembler* a = new MacroAssembler(&cb); |
duke@435 | 552 | NativeMovRegMem* nm; |
duke@435 | 553 | uint idx = 0; |
duke@435 | 554 | uint idx1; |
duke@435 | 555 | int offsets[] = { |
duke@435 | 556 | 0x0, |
duke@435 | 557 | 0xffffffff, |
duke@435 | 558 | 0x7fffffff, |
duke@435 | 559 | 0x80000000, |
duke@435 | 560 | 4096, |
duke@435 | 561 | 4097, |
duke@435 | 562 | 0x20, |
duke@435 | 563 | 0x4000, |
duke@435 | 564 | }; |
duke@435 | 565 | |
duke@435 | 566 | VM_Version::allow_all(); |
duke@435 | 567 | |
twisti@1162 | 568 | AddressLiteral al1(0xffffffff, relocInfo::external_word_type); |
twisti@1162 | 569 | AddressLiteral al2(0xaaaabbbb, relocInfo::external_word_type); |
twisti@1162 | 570 | a->ldsw( G5, al1.low10(), G4 ); idx++; |
twisti@1162 | 571 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 572 | a->ldsw( G5, I3, G4 ); idx++; |
twisti@1162 | 573 | a->ldsb( G5, al1.low10(), G4 ); idx++; |
twisti@1162 | 574 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 575 | a->ldsb( G5, I3, G4 ); idx++; |
twisti@1162 | 576 | a->ldsh( G5, al1.low10(), G4 ); idx++; |
twisti@1162 | 577 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 578 | a->ldsh( G5, I3, G4 ); idx++; |
twisti@1162 | 579 | a->lduw( G5, al1.low10(), G4 ); idx++; |
twisti@1162 | 580 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 581 | a->lduw( G5, I3, G4 ); idx++; |
twisti@1162 | 582 | a->ldub( G5, al1.low10(), G4 ); idx++; |
twisti@1162 | 583 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 584 | a->ldub( G5, I3, G4 ); idx++; |
twisti@1162 | 585 | a->lduh( G5, al1.low10(), G4 ); idx++; |
twisti@1162 | 586 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 587 | a->lduh( G5, I3, G4 ); idx++; |
twisti@1162 | 588 | a->ldx( G5, al1.low10(), G4 ); idx++; |
twisti@1162 | 589 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 590 | a->ldx( G5, I3, G4 ); idx++; |
twisti@1162 | 591 | a->ldd( G5, al1.low10(), G4 ); idx++; |
twisti@1162 | 592 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 593 | a->ldd( G5, I3, G4 ); idx++; |
duke@435 | 594 | a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++; |
twisti@1162 | 595 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 596 | a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++; |
duke@435 | 597 | |
twisti@1162 | 598 | a->stw( G5, G4, al1.low10() ); idx++; |
twisti@1162 | 599 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 600 | a->stw( G5, G4, I3 ); idx++; |
twisti@1162 | 601 | a->stb( G5, G4, al1.low10() ); idx++; |
twisti@1162 | 602 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 603 | a->stb( G5, G4, I3 ); idx++; |
twisti@1162 | 604 | a->sth( G5, G4, al1.low10() ); idx++; |
twisti@1162 | 605 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 606 | a->sth( G5, G4, I3 ); idx++; |
twisti@1162 | 607 | a->stx( G5, G4, al1.low10() ); idx++; |
twisti@1162 | 608 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 609 | a->stx( G5, G4, I3 ); idx++; |
twisti@1162 | 610 | a->std( G5, G4, al1.low10() ); idx++; |
twisti@1162 | 611 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 612 | a->std( G5, G4, I3 ); idx++; |
duke@435 | 613 | a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++; |
twisti@1162 | 614 | a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
duke@435 | 615 | a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++; |
duke@435 | 616 | |
duke@435 | 617 | nm = nativeMovRegMem_at( cb.code_begin() ); |
duke@435 | 618 | nm->print(); |
duke@435 | 619 | nm->set_offset( low10(0) ); |
duke@435 | 620 | nm->print(); |
duke@435 | 621 | nm->add_offset_in_bytes( low10(0xbb) * wordSize ); |
duke@435 | 622 | nm->print(); |
duke@435 | 623 | |
duke@435 | 624 | while (--idx) { |
duke@435 | 625 | nm = nativeMovRegMem_at( nm->next_instruction_address() ); |
duke@435 | 626 | nm->print(); |
duke@435 | 627 | for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) { |
duke@435 | 628 | nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] ); |
duke@435 | 629 | assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]), |
duke@435 | 630 | "check unit test"); |
duke@435 | 631 | nm->print(); |
duke@435 | 632 | } |
duke@435 | 633 | nm->add_offset_in_bytes( low10(0xbb) * wordSize ); |
duke@435 | 634 | nm->print(); |
duke@435 | 635 | } |
duke@435 | 636 | |
duke@435 | 637 | VM_Version::revert(); |
duke@435 | 638 | #endif // ASSERT |
duke@435 | 639 | } |
duke@435 | 640 | |
duke@435 | 641 | // End code for unit testing implementation of NativeMovRegMem class |
duke@435 | 642 | |
duke@435 | 643 | //-------------------------------------------------------------------------------- |
duke@435 | 644 | |
duke@435 | 645 | |
duke@435 | 646 | void NativeMovRegMemPatching::copy_instruction_to(address new_instruction_address) { |
duke@435 | 647 | Untested("copy_instruction_to"); |
duke@435 | 648 | int instruction_size = next_instruction_address() - instruction_address(); |
duke@435 | 649 | for (int i = 0; i < instruction_size; i += wordSize) { |
duke@435 | 650 | *(long*)(new_instruction_address + i) = *(long*)(address(this) + i); |
duke@435 | 651 | } |
duke@435 | 652 | } |
duke@435 | 653 | |
duke@435 | 654 | |
duke@435 | 655 | void NativeMovRegMemPatching::verify() { |
duke@435 | 656 | NativeInstruction::verify(); |
duke@435 | 657 | // make sure code pattern is actually a "ld" or "st" of some sort. |
duke@435 | 658 | int i0 = long_at(0); |
duke@435 | 659 | int op3 = inv_op3(i0); |
duke@435 | 660 | |
duke@435 | 661 | assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); |
duke@435 | 662 | |
duke@435 | 663 | if (!(is_op(i0, Assembler::ldst_op) && |
duke@435 | 664 | inv_immed(i0) && |
duke@435 | 665 | 0 != (op3 < op3_ldst_int_limit |
duke@435 | 666 | ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) |
duke@435 | 667 | : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) { |
duke@435 | 668 | int i1 = long_at(ldst_offset); |
duke@435 | 669 | Register rd = inv_rd(i0); |
duke@435 | 670 | |
duke@435 | 671 | op3 = inv_op3(i1); |
duke@435 | 672 | if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) && |
duke@435 | 673 | 0 != (op3 < op3_ldst_int_limit |
duke@435 | 674 | ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) |
duke@435 | 675 | : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) { |
duke@435 | 676 | fatal("not a ld* or st* op"); |
duke@435 | 677 | } |
duke@435 | 678 | } |
duke@435 | 679 | } |
duke@435 | 680 | |
duke@435 | 681 | |
duke@435 | 682 | void NativeMovRegMemPatching::print() { |
duke@435 | 683 | if (is_immediate()) { |
duke@435 | 684 | tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset()); |
duke@435 | 685 | } else { |
duke@435 | 686 | tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address()); |
duke@435 | 687 | } |
duke@435 | 688 | } |
duke@435 | 689 | |
duke@435 | 690 | |
duke@435 | 691 | // Code for unit testing implementation of NativeMovRegMemPatching class |
duke@435 | 692 | void NativeMovRegMemPatching::test() { |
duke@435 | 693 | #ifdef ASSERT |
duke@435 | 694 | ResourceMark rm; |
duke@435 | 695 | CodeBuffer cb("test", 1000, 1000); |
duke@435 | 696 | MacroAssembler* a = new MacroAssembler(&cb); |
duke@435 | 697 | NativeMovRegMemPatching* nm; |
duke@435 | 698 | uint idx = 0; |
duke@435 | 699 | uint idx1; |
duke@435 | 700 | int offsets[] = { |
duke@435 | 701 | 0x0, |
duke@435 | 702 | 0xffffffff, |
duke@435 | 703 | 0x7fffffff, |
duke@435 | 704 | 0x80000000, |
duke@435 | 705 | 4096, |
duke@435 | 706 | 4097, |
duke@435 | 707 | 0x20, |
duke@435 | 708 | 0x4000, |
duke@435 | 709 | }; |
duke@435 | 710 | |
duke@435 | 711 | VM_Version::allow_all(); |
duke@435 | 712 | |
twisti@1162 | 713 | AddressLiteral al(0xffffffff, relocInfo::external_word_type); |
twisti@1162 | 714 | a->ldsw( G5, al.low10(), G4); idx++; |
twisti@1162 | 715 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 716 | a->ldsw( G5, I3, G4 ); idx++; |
twisti@1162 | 717 | a->ldsb( G5, al.low10(), G4); idx++; |
twisti@1162 | 718 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 719 | a->ldsb( G5, I3, G4 ); idx++; |
twisti@1162 | 720 | a->ldsh( G5, al.low10(), G4); idx++; |
twisti@1162 | 721 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 722 | a->ldsh( G5, I3, G4 ); idx++; |
twisti@1162 | 723 | a->lduw( G5, al.low10(), G4); idx++; |
twisti@1162 | 724 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 725 | a->lduw( G5, I3, G4 ); idx++; |
twisti@1162 | 726 | a->ldub( G5, al.low10(), G4); idx++; |
twisti@1162 | 727 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 728 | a->ldub( G5, I3, G4 ); idx++; |
twisti@1162 | 729 | a->lduh( G5, al.low10(), G4); idx++; |
twisti@1162 | 730 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 731 | a->lduh( G5, I3, G4 ); idx++; |
twisti@1162 | 732 | a->ldx( G5, al.low10(), G4); idx++; |
twisti@1162 | 733 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
twisti@1162 | 734 | a->ldx( G5, I3, G4 ); idx++; |
twisti@1162 | 735 | a->ldd( G5, al.low10(), G4); idx++; |
twisti@1162 | 736 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
twisti@1162 | 737 | a->ldd( G5, I3, G4 ); idx++; |
twisti@1162 | 738 | a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++; |
twisti@1162 | 739 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
twisti@1162 | 740 | a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++; |
duke@435 | 741 | |
twisti@1162 | 742 | a->stw( G5, G4, al.low10()); idx++; |
twisti@1162 | 743 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 744 | a->stw( G5, G4, I3 ); idx++; |
twisti@1162 | 745 | a->stb( G5, G4, al.low10()); idx++; |
twisti@1162 | 746 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 747 | a->stb( G5, G4, I3 ); idx++; |
twisti@1162 | 748 | a->sth( G5, G4, al.low10()); idx++; |
twisti@1162 | 749 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 750 | a->sth( G5, G4, I3 ); idx++; |
twisti@1162 | 751 | a->stx( G5, G4, al.low10()); idx++; |
twisti@1162 | 752 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 753 | a->stx( G5, G4, I3 ); idx++; |
twisti@1162 | 754 | a->std( G5, G4, al.low10()); idx++; |
twisti@1162 | 755 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 756 | a->std( G5, G4, I3 ); idx++; |
duke@435 | 757 | a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++; |
twisti@1162 | 758 | a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
duke@435 | 759 | a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++; |
duke@435 | 760 | |
duke@435 | 761 | nm = nativeMovRegMemPatching_at( cb.code_begin() ); |
duke@435 | 762 | nm->print(); |
duke@435 | 763 | nm->set_offset( low10(0) ); |
duke@435 | 764 | nm->print(); |
duke@435 | 765 | nm->add_offset_in_bytes( low10(0xbb) * wordSize ); |
duke@435 | 766 | nm->print(); |
duke@435 | 767 | |
duke@435 | 768 | while (--idx) { |
duke@435 | 769 | nm = nativeMovRegMemPatching_at( nm->next_instruction_address() ); |
duke@435 | 770 | nm->print(); |
duke@435 | 771 | for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) { |
duke@435 | 772 | nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] ); |
duke@435 | 773 | assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]), |
duke@435 | 774 | "check unit test"); |
duke@435 | 775 | nm->print(); |
duke@435 | 776 | } |
duke@435 | 777 | nm->add_offset_in_bytes( low10(0xbb) * wordSize ); |
duke@435 | 778 | nm->print(); |
duke@435 | 779 | } |
duke@435 | 780 | |
duke@435 | 781 | VM_Version::revert(); |
duke@435 | 782 | #endif // ASSERT |
duke@435 | 783 | } |
duke@435 | 784 | // End code for unit testing implementation of NativeMovRegMemPatching class |
duke@435 | 785 | |
duke@435 | 786 | |
duke@435 | 787 | //-------------------------------------------------------------------------------- |
duke@435 | 788 | |
duke@435 | 789 | |
duke@435 | 790 | void NativeJump::verify() { |
duke@435 | 791 | NativeInstruction::verify(); |
duke@435 | 792 | int i0 = long_at(sethi_offset); |
duke@435 | 793 | int i1 = long_at(jmpl_offset); |
duke@435 | 794 | assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); |
duke@435 | 795 | // verify the pattern "sethi %hi22(imm), treg ; jmpl treg, %lo10(imm), lreg" |
duke@435 | 796 | Register rd = inv_rd(i0); |
duke@435 | 797 | #ifndef _LP64 |
duke@435 | 798 | if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 && |
duke@435 | 799 | (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op) || |
duke@435 | 800 | (TraceJumps && is_op3(i1, Assembler::add_op3, Assembler::arith_op))) && |
duke@435 | 801 | inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) && |
duke@435 | 802 | rd == inv_rs1(i1))) { |
duke@435 | 803 | fatal("not a jump_to instruction"); |
duke@435 | 804 | } |
duke@435 | 805 | #else |
duke@435 | 806 | // In LP64, the jump instruction location varies for non relocatable |
duke@435 | 807 | // jumps, for example is could be sethi, xor, jmp instead of the |
duke@435 | 808 | // 7 instructions for sethi. So let's check sethi only. |
duke@435 | 809 | if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { |
duke@435 | 810 | fatal("not a jump_to instruction"); |
duke@435 | 811 | } |
duke@435 | 812 | #endif |
duke@435 | 813 | } |
duke@435 | 814 | |
duke@435 | 815 | |
duke@435 | 816 | void NativeJump::print() { |
duke@435 | 817 | tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, instruction_address(), jump_destination()); |
duke@435 | 818 | } |
duke@435 | 819 | |
duke@435 | 820 | |
duke@435 | 821 | // Code for unit testing implementation of NativeJump class |
duke@435 | 822 | void NativeJump::test() { |
duke@435 | 823 | #ifdef ASSERT |
duke@435 | 824 | ResourceMark rm; |
duke@435 | 825 | CodeBuffer cb("test", 100, 100); |
duke@435 | 826 | MacroAssembler* a = new MacroAssembler(&cb); |
duke@435 | 827 | NativeJump* nj; |
duke@435 | 828 | uint idx; |
duke@435 | 829 | int offsets[] = { |
duke@435 | 830 | 0x0, |
duke@435 | 831 | 0xffffffff, |
duke@435 | 832 | 0x7fffffff, |
duke@435 | 833 | 0x80000000, |
duke@435 | 834 | 4096, |
duke@435 | 835 | 4097, |
duke@435 | 836 | 0x20, |
duke@435 | 837 | 0x4000, |
duke@435 | 838 | }; |
duke@435 | 839 | |
duke@435 | 840 | VM_Version::allow_all(); |
duke@435 | 841 | |
twisti@1162 | 842 | AddressLiteral al(0x7fffbbbb, relocInfo::external_word_type); |
twisti@1162 | 843 | a->sethi(al, I3); |
twisti@1162 | 844 | a->jmpl(I3, al.low10(), G0, RelocationHolder::none); |
duke@435 | 845 | a->delayed()->nop(); |
twisti@1162 | 846 | a->sethi(al, I3); |
twisti@1162 | 847 | a->jmpl(I3, al.low10(), L3, RelocationHolder::none); |
duke@435 | 848 | a->delayed()->nop(); |
duke@435 | 849 | |
duke@435 | 850 | nj = nativeJump_at( cb.code_begin() ); |
duke@435 | 851 | nj->print(); |
duke@435 | 852 | |
duke@435 | 853 | nj = nativeJump_at( nj->next_instruction_address() ); |
duke@435 | 854 | for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { |
duke@435 | 855 | nj->set_jump_destination( nj->instruction_address() + offsets[idx] ); |
duke@435 | 856 | assert(nj->jump_destination() == (nj->instruction_address() + offsets[idx]), "check unit test"); |
duke@435 | 857 | nj->print(); |
duke@435 | 858 | } |
duke@435 | 859 | |
duke@435 | 860 | VM_Version::revert(); |
duke@435 | 861 | #endif // ASSERT |
duke@435 | 862 | } |
duke@435 | 863 | // End code for unit testing implementation of NativeJump class |
duke@435 | 864 | |
duke@435 | 865 | |
duke@435 | 866 | void NativeJump::insert(address code_pos, address entry) { |
duke@435 | 867 | Unimplemented(); |
duke@435 | 868 | } |
duke@435 | 869 | |
duke@435 | 870 | // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie) |
duke@435 | 871 | // The problem: jump_to <dest> is a 3-word instruction (including its delay slot). |
duke@435 | 872 | // Atomic write can be only with 1 word. |
duke@435 | 873 | void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) { |
duke@435 | 874 | // Here's one way to do it: Pre-allocate a three-word jump sequence somewhere |
duke@435 | 875 | // in the header of the nmethod, within a short branch's span of the patch point. |
duke@435 | 876 | // Set up the jump sequence using NativeJump::insert, and then use an annulled |
duke@435 | 877 | // unconditional branch at the target site (an atomic 1-word update). |
duke@435 | 878 | // Limitations: You can only patch nmethods, with any given nmethod patched at |
duke@435 | 879 | // most once, and the patch must be in the nmethod's header. |
duke@435 | 880 | // It's messy, but you can ask the CodeCache for the nmethod containing the |
duke@435 | 881 | // target address. |
duke@435 | 882 | |
duke@435 | 883 | // %%%%% For now, do something MT-stupid: |
duke@435 | 884 | ResourceMark rm; |
duke@435 | 885 | int code_size = 1 * BytesPerInstWord; |
duke@435 | 886 | CodeBuffer cb(verified_entry, code_size + 1); |
duke@435 | 887 | MacroAssembler* a = new MacroAssembler(&cb); |
duke@435 | 888 | if (VM_Version::v9_instructions_work()) { |
duke@435 | 889 | a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler |
duke@435 | 890 | } else { |
duke@435 | 891 | a->lduw(G0, 0, O7); // "ld" must agree with code in the signal handler |
duke@435 | 892 | } |
duke@435 | 893 | ICache::invalidate_range(verified_entry, code_size); |
duke@435 | 894 | } |
duke@435 | 895 | |
duke@435 | 896 | |
duke@435 | 897 | void NativeIllegalInstruction::insert(address code_pos) { |
duke@435 | 898 | NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos); |
duke@435 | 899 | nii->set_long_at(0, illegal_instruction()); |
duke@435 | 900 | } |
duke@435 | 901 | |
duke@435 | 902 | static int illegal_instruction_bits = 0; |
duke@435 | 903 | |
duke@435 | 904 | int NativeInstruction::illegal_instruction() { |
duke@435 | 905 | if (illegal_instruction_bits == 0) { |
duke@435 | 906 | ResourceMark rm; |
duke@435 | 907 | char buf[40]; |
duke@435 | 908 | CodeBuffer cbuf((address)&buf[0], 20); |
duke@435 | 909 | MacroAssembler* a = new MacroAssembler(&cbuf); |
duke@435 | 910 | address ia = a->pc(); |
duke@435 | 911 | a->trap(ST_RESERVED_FOR_USER_0 + 1); |
duke@435 | 912 | int bits = *(int*)ia; |
duke@435 | 913 | assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction"); |
duke@435 | 914 | illegal_instruction_bits = bits; |
duke@435 | 915 | assert(illegal_instruction_bits != 0, "oops"); |
duke@435 | 916 | } |
duke@435 | 917 | return illegal_instruction_bits; |
duke@435 | 918 | } |
duke@435 | 919 | |
duke@435 | 920 | static int ic_miss_trap_bits = 0; |
duke@435 | 921 | |
duke@435 | 922 | bool NativeInstruction::is_ic_miss_trap() { |
duke@435 | 923 | if (ic_miss_trap_bits == 0) { |
duke@435 | 924 | ResourceMark rm; |
duke@435 | 925 | char buf[40]; |
duke@435 | 926 | CodeBuffer cbuf((address)&buf[0], 20); |
duke@435 | 927 | MacroAssembler* a = new MacroAssembler(&cbuf); |
duke@435 | 928 | address ia = a->pc(); |
duke@435 | 929 | a->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0 + 2); |
duke@435 | 930 | int bits = *(int*)ia; |
duke@435 | 931 | assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction"); |
duke@435 | 932 | ic_miss_trap_bits = bits; |
duke@435 | 933 | assert(ic_miss_trap_bits != 0, "oops"); |
duke@435 | 934 | } |
duke@435 | 935 | return long_at(0) == ic_miss_trap_bits; |
duke@435 | 936 | } |
duke@435 | 937 | |
duke@435 | 938 | |
duke@435 | 939 | bool NativeInstruction::is_illegal() { |
duke@435 | 940 | if (illegal_instruction_bits == 0) { |
duke@435 | 941 | return false; |
duke@435 | 942 | } |
duke@435 | 943 | return long_at(0) == illegal_instruction_bits; |
duke@435 | 944 | } |
duke@435 | 945 | |
duke@435 | 946 | |
duke@435 | 947 | void NativeGeneralJump::verify() { |
duke@435 | 948 | assert(((NativeInstruction *)this)->is_jump() || |
duke@435 | 949 | ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction"); |
duke@435 | 950 | } |
duke@435 | 951 | |
duke@435 | 952 | |
duke@435 | 953 | void NativeGeneralJump::insert_unconditional(address code_pos, address entry) { |
duke@435 | 954 | Assembler::Condition condition = Assembler::always; |
duke@435 | 955 | int x = Assembler::op2(Assembler::br_op2) | Assembler::annul(false) | |
duke@435 | 956 | Assembler::cond(condition) | Assembler::wdisp((intptr_t)entry, (intptr_t)code_pos, 22); |
duke@435 | 957 | NativeGeneralJump* ni = (NativeGeneralJump*) nativeInstruction_at(code_pos); |
duke@435 | 958 | ni->set_long_at(0, x); |
duke@435 | 959 | } |
duke@435 | 960 | |
duke@435 | 961 | |
duke@435 | 962 | // MT-safe patching of a jmp instruction (and following word). |
duke@435 | 963 | // First patches the second word, and then atomicly replaces |
duke@435 | 964 | // the first word with the first new instruction word. |
duke@435 | 965 | // Other processors might briefly see the old first word |
duke@435 | 966 | // followed by the new second word. This is OK if the old |
duke@435 | 967 | // second word is harmless, and the new second word may be |
duke@435 | 968 | // harmlessly executed in the delay slot of the call. |
duke@435 | 969 | void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) { |
duke@435 | 970 | assert(Patching_lock->is_locked() || |
duke@435 | 971 | SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); |
duke@435 | 972 | assert (instr_addr != NULL, "illegal address for code patching"); |
duke@435 | 973 | NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr); // checking that it is a call |
duke@435 | 974 | assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8"); |
duke@435 | 975 | int i0 = ((int*)code_buffer)[0]; |
duke@435 | 976 | int i1 = ((int*)code_buffer)[1]; |
duke@435 | 977 | int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord); |
duke@435 | 978 | assert(inv_op(*contention_addr) == Assembler::arith_op || |
duke@435 | 979 | *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(), |
duke@435 | 980 | "must not interfere with original call"); |
duke@435 | 981 | // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order |
duke@435 | 982 | h_jump->set_long_at(1*BytesPerInstWord, i1); |
duke@435 | 983 | h_jump->set_long_at(0*BytesPerInstWord, i0); |
duke@435 | 984 | // NOTE: It is possible that another thread T will execute |
duke@435 | 985 | // only the second patched word. |
duke@435 | 986 | // In other words, since the original instruction is this |
duke@435 | 987 | // jmp patching_stub; nop (NativeGeneralJump) |
duke@435 | 988 | // and the new sequence from the buffer is this: |
duke@435 | 989 | // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg) |
duke@435 | 990 | // what T will execute is this: |
duke@435 | 991 | // jmp patching_stub; add %r, %lo(K), %r |
duke@435 | 992 | // thereby putting garbage into %r before calling the patching stub. |
duke@435 | 993 | // This is OK, because the patching stub ignores the value of %r. |
duke@435 | 994 | |
duke@435 | 995 | // Make sure the first-patched instruction, which may co-exist |
duke@435 | 996 | // briefly with the call, will do something harmless. |
duke@435 | 997 | assert(inv_op(*contention_addr) == Assembler::arith_op || |
duke@435 | 998 | *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(), |
duke@435 | 999 | "must not interfere with original call"); |
duke@435 | 1000 | } |