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src/cpu/sparc/vm/vm_version_sparc.hpp@55fb97c4c58d (annotated)

src/cpu/sparc/vm/vm_version_sparc.hpp

Tue, 24 Dec 2013 11:48:39 -0800

author
mikael
date
Tue, 24 Dec 2013 11:48:39 -0800
changeset 6198
55fb97c4c58d
parent 6154
eae426d683f6
child 6312
04d32e7fad07
permissions
-rw-r--r--

8029233: Update copyright year to match last edit in jdk8 hotspot repository for 2013
Summary: Copyright year updated for files modified during 2013
Reviewed-by: twisti, iveresov

duke@435 1 /*
mikael@6198 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
duke@435 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435 4 *
duke@435 5 * This code is free software; you can redistribute it and/or modify it
duke@435 6 * under the terms of the GNU General Public License version 2 only, as
duke@435 7 * published by the Free Software Foundation.
duke@435 8 *
duke@435 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@435 13 * accompanied this code).
duke@435 14 *
duke@435 15 * You should have received a copy of the GNU General Public License version
duke@435 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@435 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435 18 *
trims@1907 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 20 * or visit www.oracle.com if you need additional information or have any
trims@1907 21 * questions.
duke@435 22 *
duke@435 23 */
duke@435 24
stefank@2314 25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
stefank@2314 26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
stefank@2314 27
stefank@2314 28 #include "runtime/globals_extension.hpp"
stefank@2314 29 #include "runtime/vm_version.hpp"
stefank@2314 30
duke@435 31 class VM_Version: public Abstract_VM_Version {
duke@435 32 protected:
duke@435 33 enum Feature_Flag {
kvn@3037 34 v8_instructions = 0,
kvn@3037 35 hardware_mul32 = 1,
kvn@3037 36 hardware_div32 = 2,
kvn@3037 37 hardware_fsmuld = 3,
kvn@3037 38 hardware_popc = 4,
kvn@3037 39 v9_instructions = 5,
kvn@3037 40 vis1_instructions = 6,
kvn@3037 41 vis2_instructions = 7,
kvn@3037 42 sun4v_instructions = 8,
kvn@2269 43 blk_init_instructions = 9,
kvn@3037 44 fmaf_instructions = 10,
kvn@3037 45 fmau_instructions = 11,
kvn@3037 46 vis3_instructions = 12,
kvn@3972 47 cbcond_instructions = 13,
kvn@3972 48 sparc64_family = 14,
kvn@3972 49 M_family = 15,
kvn@3972 50 T_family = 16,
kvn@3972 51 T1_model = 17
duke@435 52 };
duke@435 53
duke@435 54 enum Feature_Flag_Set {
twisti@1076 55 unknown_m = 0,
twisti@1076 56 all_features_m = -1,
duke@435 57
kvn@3037 58 v8_instructions_m = 1 << v8_instructions,
kvn@3037 59 hardware_mul32_m = 1 << hardware_mul32,
kvn@3037 60 hardware_div32_m = 1 << hardware_div32,
kvn@3037 61 hardware_fsmuld_m = 1 << hardware_fsmuld,
kvn@3037 62 hardware_popc_m = 1 << hardware_popc,
kvn@3037 63 v9_instructions_m = 1 << v9_instructions,
kvn@3037 64 vis1_instructions_m = 1 << vis1_instructions,
kvn@3037 65 vis2_instructions_m = 1 << vis2_instructions,
kvn@3037 66 sun4v_m = 1 << sun4v_instructions,
kvn@2269 67 blk_init_instructions_m = 1 << blk_init_instructions,
kvn@3037 68 fmaf_instructions_m = 1 << fmaf_instructions,
kvn@3037 69 fmau_instructions_m = 1 << fmau_instructions,
kvn@3037 70 vis3_instructions_m = 1 << vis3_instructions,
kvn@3972 71 cbcond_instructions_m = 1 << cbcond_instructions,
kvn@3037 72 sparc64_family_m = 1 << sparc64_family,
kvn@3972 73 M_family_m = 1 << M_family,
kvn@3037 74 T_family_m = 1 << T_family,
kvn@3037 75 T1_model_m = 1 << T1_model,
duke@435 76
twisti@1076 77 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
twisti@1076 78 generic_v9_m = generic_v8_m | v9_instructions_m,
twisti@1076 79 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
duke@435 80
duke@435 81 // Temporary until we have something more accurate
twisti@1076 82 niagara1_unique_m = sun4v_m,
twisti@1076 83 niagara1_m = generic_v9_m | niagara1_unique_m
duke@435 84 };
duke@435 85
duke@435 86 static int _features;
duke@435 87 static const char* _features_str;
duke@435 88
duke@435 89 static void print_features();
duke@435 90 static int determine_features();
duke@435 91 static int platform_features(int features);
duke@435 92
kvn@2403 93 // Returns true if the platform is in the niagara line (T series)
kvn@3972 94 static bool is_M_family(int features) { return (features & M_family_m) != 0; }
kvn@2403 95 static bool is_T_family(int features) { return (features & T_family_m) != 0; }
kvn@2403 96 static bool is_niagara() { return is_T_family(_features); }
simonis@6154 97 #ifdef ASSERT
simonis@6154 98 static bool is_niagara(int features) {
simonis@6154 99 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
simonis@6154 100 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
simonis@6154 101 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
simonis@6154 102 }
simonis@6154 103 #endif
kvn@2403 104
kvn@2403 105 // Returns true if it is niagara1 (T1).
kvn@2403 106 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
duke@435 107
jmasa@445 108 static int maximum_niagara1_processor_count() { return 32; }
jmasa@445 109
duke@435 110 public:
duke@435 111 // Initialization
duke@435 112 static void initialize();
duke@435 113
duke@435 114 // Instruction support
duke@435 115 static bool has_v8() { return (_features & v8_instructions_m) != 0; }
duke@435 116 static bool has_v9() { return (_features & v9_instructions_m) != 0; }
twisti@1076 117 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
twisti@1076 118 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
duke@435 119 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
twisti@1078 120 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
duke@435 121 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
duke@435 122 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
kvn@2403 123 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
kvn@2269 124 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
kvn@3037 125 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
duke@435 126
duke@435 127 static bool supports_compare_and_exchange()
duke@435 128 { return has_v9(); }
duke@435 129
kvn@2403 130 // Returns true if the platform is in the niagara line (T series)
kvn@2403 131 // and newer than the niagara1.
kvn@2403 132 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
twisti@4108 133
twisti@4108 134 static bool is_M_series() { return is_M_family(_features); }
kvn@3052 135 static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
kvn@3037 136
kvn@2403 137 // Fujitsu SPARC64
kvn@2403 138 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
duke@435 139
kvn@3037 140 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
kvn@3037 141 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
kvn@3037 142
kvn@2403 143 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
kvn@2403 144 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
kvn@3052 145
kvn@3037 146 // T4 and newer Sparc have fast RDPC instruction.
kvn@3052 147 static bool has_fast_rdpc() { return is_T4(); }
kvn@3052 148
kvn@3092 149 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
kvn@3092 150 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
duke@435 151
duke@435 152 static const char* cpu_features() { return _features_str; }
duke@435 153
kvn@3052 154 static intx prefetch_data_size() {
kvn@3052 155 return is_T4() ? 32 : 64; // default prefetch block size on sparc
duke@435 156 }
duke@435 157
duke@435 158 // Prefetch
duke@435 159 static intx prefetch_copy_interval_in_bytes() {
duke@435 160 intx interval = PrefetchCopyIntervalInBytes;
duke@435 161 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
duke@435 162 }
duke@435 163 static intx prefetch_scan_interval_in_bytes() {
duke@435 164 intx interval = PrefetchScanIntervalInBytes;
duke@435 165 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
duke@435 166 }
duke@435 167 static intx prefetch_fields_ahead() {
duke@435 168 intx count = PrefetchFieldsAhead;
duke@435 169 return count >= 0 ? count : (is_ultra3() ? 1 : 0);
duke@435 170 }
duke@435 171
duke@435 172 static intx allocate_prefetch_distance() {
duke@435 173 // This method should be called before allocate_prefetch_style().
duke@435 174 intx count = AllocatePrefetchDistance;
duke@435 175 if (count < 0) { // default is not defined ?
duke@435 176 count = 512;
duke@435 177 }
duke@435 178 return count;
duke@435 179 }
duke@435 180 static intx allocate_prefetch_style() {
duke@435 181 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
duke@435 182 // Return 0 if AllocatePrefetchDistance was not defined.
duke@435 183 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
duke@435 184 }
duke@435 185
duke@435 186 // Assembler testing
duke@435 187 static void allow_all();
duke@435 188 static void revert();
duke@435 189
duke@435 190 // Override the Abstract_VM_Version implementation.
duke@435 191 static uint page_size_count() { return is_sun4v() ? 4 : 2; }
jmasa@445 192
jmasa@445 193 // Calculates the number of parallel threads
jmasa@445 194 static unsigned int calc_parallel_worker_threads();
duke@435 195 };
stefank@2314 196
stefank@2314 197 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP

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