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src/cpu/mips/vm/globals_mips.hpp@4bfb40d1e17a (annotated)
src/cpu/mips/vm/globals_mips.hpp
Wed, 29 Mar 2017 09:41:51 +0800
- author
- aoqi
- date
- Wed, 29 Mar 2017 09:41:51 +0800
- changeset 392
- 4bfb40d1e17a
- parent 389
- 76857a2c3534
- child 397
- 1e8b8bc62356
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- -rw-r--r--
#4662 TieredCompilation is turned off.
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| aoqi@1 | 1 | /* |
| aoqi@1 | 2 | * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
| aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
| aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@1 | 5 | * |
| aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@1 | 8 | * published by the Free Software Foundation. |
| aoqi@1 | 9 | * |
| aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@1 | 14 | * accompanied this code). |
| aoqi@1 | 15 | * |
| aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@1 | 19 | * |
| aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@1 | 22 | * questions. |
| aoqi@1 | 23 | * |
| aoqi@1 | 24 | */ |
| aoqi@1 | 25 | |
| aoqi@1 | 26 | #ifndef CPU_MIPS_VM_GLOBALS_MIPS_HPP |
| aoqi@1 | 27 | #define CPU_MIPS_VM_GLOBALS_MIPS_HPP |
| aoqi@1 | 28 | |
| aoqi@1 | 29 | #include "utilities/globalDefinitions.hpp" |
| aoqi@1 | 30 | #include "utilities/macros.hpp" |
| aoqi@1 | 31 | |
| aoqi@1 | 32 | // |
| aoqi@1 | 33 | // Sets the default values for platform dependent flags used by the runtime system. |
| aoqi@1 | 34 | // (see globals.hpp) |
| aoqi@1 | 35 | // |
| aoqi@1 | 36 | #ifdef CORE |
| aoqi@1 | 37 | define_pd_global(bool, UseSSE, 0); |
| aoqi@1 | 38 | #endif /* CORE */ |
| aoqi@1 | 39 | define_pd_global(bool, ConvertSleepToYield, true); |
| aoqi@1 | 40 | define_pd_global(bool, ShareVtableStubs, true); |
| aoqi@1 | 41 | define_pd_global(bool, CountInterpCalls, true); |
| aoqi@1 | 42 | |
| aoqi@1 | 43 | define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks |
| aoqi@1 | 44 | define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86. |
| aoqi@1 | 45 | define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast |
| aoqi@1 | 46 | define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this |
| aoqi@1 | 47 | |
| aoqi@1 | 48 | // See 4827828 for this change. There is no globals_core_i486.hpp. I can't |
| aoqi@1 | 49 | // assign a different value for C2 without touching a number of files. Use |
| aoqi@1 | 50 | // #ifdef to minimize the change as it's late in Mantis. -- FIXME. |
| aoqi@1 | 51 | // c1 doesn't have this problem because the fix to 4858033 assures us |
| aoqi@1 | 52 | // the the vep is aligned at CodeEntryAlignment whereas c2 only aligns |
| aoqi@1 | 53 | // the uep and the vep doesn't get real alignment but just slops on by |
| aoqi@1 | 54 | // only assured that the entry instruction meets the 5 byte size requirement. |
| aoqi@1 | 55 | define_pd_global(intx, CodeEntryAlignment, 32); |
| aoqi@1 | 56 | define_pd_global(intx, OptoLoopAlignment, 16); |
| aoqi@1 | 57 | define_pd_global(intx, InlineFrequencyCount, 100); |
| Jin@10 | 58 | define_pd_global(intx, InlineSmallCode, 4000); // 2016/5/11 Jin: MIPS generates 3x instructions than X86 |
| aoqi@1 | 59 | |
| aoqi@1 | 60 | define_pd_global(uintx, TLABSize, 0); |
| aoqi@1 | 61 | define_pd_global(uintx, NewSize, 1024 * K); |
| aoqi@1 | 62 | define_pd_global(intx, PreInflateSpin, 10); |
| aoqi@1 | 63 | |
| aoqi@1 | 64 | define_pd_global(intx, PrefetchCopyIntervalInBytes, -1); |
| aoqi@1 | 65 | define_pd_global(intx, PrefetchScanIntervalInBytes, -1); |
| aoqi@1 | 66 | define_pd_global(intx, PrefetchFieldsAhead, -1); |
| aoqi@1 | 67 | |
| aoqi@1 | 68 | define_pd_global(intx, StackYellowPages, 2); |
| aoqi@1 | 69 | define_pd_global(intx, StackRedPages, 1); |
| aoqi@1 | 70 | define_pd_global(intx, StackShadowPages, 3 DEBUG_ONLY(+1)); |
| aoqi@1 | 71 | |
| aoqi@1 | 72 | define_pd_global(bool, RewriteBytecodes, true); |
| aoqi@1 | 73 | define_pd_global(bool, RewriteFrequentPairs, true); |
| aoqi@1 | 74 | #ifdef _ALLBSD_SOURCE |
| aoqi@1 | 75 | define_pd_global(bool, UseMembar, true); |
| aoqi@1 | 76 | #else |
| aoqi@1 | 77 | define_pd_global(bool, UseMembar, false); |
| aoqi@1 | 78 | #endif |
| aoqi@1 | 79 | // GC Ergo Flags |
| aoqi@1 | 80 | define_pd_global(intx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread |
| aoqi@1 | 81 | |
| aoqi@1 | 82 | define_pd_global(uintx, TypeProfileLevel, 111); |
| aoqi@1 | 83 | |
| aoqi@1 | 84 | // Only c2 cares about this at the moment |
| aoqi@1 | 85 | define_pd_global(intx, AllocatePrefetchStyle, 2); |
| aoqi@1 | 86 | define_pd_global(intx, AllocatePrefetchDistance, -1); |
| aoqi@1 | 87 | |
| aoqi@1 | 88 | #define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \ |
| aoqi@1 | 89 | \ |
| chenhaoxuan@358 | 90 | product(bool, UseLoongsonISA, false, \ |
| aoqi@180 | 91 | "Use LoongsonISA on Loongson CPUs") \ |
| aoqi@180 | 92 | \ |
| chenhaoxuan@358 | 93 | product(bool, Use3A2000, false, \ |
| aoqi@180 | 94 | "Use Loongson 3A2000 CPU") \ |
| aoqi@180 | 95 | \ |
| fujie@389 | 96 | product(bool, UseCodeCacheAllocOpt, true, \ |
| fujie@389 | 97 | "Allocate code cache within 32-bit memory address space") \ |
| fujie@389 | 98 | \ |
| fujie@382 | 99 | product(intx, UseSyncLevel, 1000, \ |
| fujie@336 | 100 | "The sync level on Loongson CPUs" \ |
| fujie@336 | 101 | "for GS464E, UseSyncLevel >= 2000" \ |
| fujie@336 | 102 | "others, UseSyncLevel <= 1000") \ |
| fujie@336 | 103 | \ |
| jiangshaofeng@362 | 104 | develop(bool, UseBoundCheckInstruction, false, \ |
| jiangshaofeng@362 | 105 | "Use bound check instruction") \ |
| jiangshaofeng@362 | 106 | \ |
| aoqi@179 | 107 | product(intx, SetFSFOFN, 999, \ |
| aoqi@179 | 108 | "Set the FS/FO/FN bits in FCSR" \ |
| aoqi@179 | 109 | "999 means FS/FO/FN will not be changed" \ |
| aoqi@179 | 110 | "=XYZ, with X:FS, Y:FO, Z:FN, X, Y and Z in 0=off, 1=on") \ |
| aoqi@179 | 111 | \ |
| aoqi@1 | 112 | develop(bool, IEEEPrecision, true, \ |
| aoqi@1 | 113 | "Enables IEEE precision (for INTEL only)") \ |
| aoqi@1 | 114 | \ |
| aoqi@1 | 115 | product(intx, FenceInstruction, 0, \ |
| aoqi@1 | 116 | "(Unsafe,Unstable) Experimental") \ |
| aoqi@1 | 117 | \ |
| aoqi@1 | 118 | product(intx, ReadPrefetchInstr, 0, \ |
| aoqi@1 | 119 | "Prefetch instruction to prefetch ahead") \ |
| aoqi@1 | 120 | \ |
| aoqi@1 | 121 | product(bool, UseStoreImmI16, true, \ |
| aoqi@1 | 122 | "Use store immediate 16-bits value instruction on x86") \ |
| aoqi@1 | 123 | \ |
| aoqi@1 | 124 | product(intx, UseAVX, 99, \ |
| aoqi@1 | 125 | "Highest supported AVX instructions set on x86/x64") \ |
| aoqi@1 | 126 | \ |
| aoqi@1 | 127 | diagnostic(bool, UseIncDec, true, \ |
| aoqi@1 | 128 | "Use INC, DEC instructions on x86") \ |
| aoqi@1 | 129 | \ |
| aoqi@1 | 130 | product(bool, UseNewLongLShift, false, \ |
| aoqi@1 | 131 | "Use optimized bitwise shift left") \ |
| aoqi@1 | 132 | \ |
| aoqi@1 | 133 | product(bool, UseAddressNop, false, \ |
| aoqi@1 | 134 | "Use '0F 1F [addr]' NOP instructions on x86 cpus") \ |
| aoqi@1 | 135 | \ |
| aoqi@1 | 136 | product(bool, UseXmmLoadAndClearUpper, true, \ |
| aoqi@1 | 137 | "Load low part of XMM register and clear upper part") \ |
| aoqi@1 | 138 | \ |
| aoqi@1 | 139 | product(bool, UseXmmRegToRegMoveAll, false, \ |
| aoqi@1 | 140 | "Copy all XMM register bits when moving value between registers") \ |
| aoqi@1 | 141 | \ |
| aoqi@1 | 142 | product(bool, UseXmmI2D, false, \ |
| aoqi@1 | 143 | "Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \ |
| aoqi@1 | 144 | \ |
| aoqi@1 | 145 | product(bool, UseXmmI2F, false, \ |
| aoqi@1 | 146 | "Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \ |
| aoqi@1 | 147 | \ |
| aoqi@1 | 148 | product(bool, UseUnalignedLoadStores, false, \ |
| aoqi@1 | 149 | "Use SSE2 MOVDQU instruction for Arraycopy") \ |
| aoqi@1 | 150 | \ |
| aoqi@1 | 151 | /* assembler */ \ |
| aoqi@1 | 152 | product(bool, Use486InstrsOnly, false, \ |
| aoqi@1 | 153 | "Use 80486 Compliant instruction subset") \ |
| aoqi@1 | 154 | \ |
| fujie@213 | 155 | product(bool, UseCountLeadingZerosInstruction, true, \ |
| aoqi@1 | 156 | "Use count leading zeros instruction") \ |
| aoqi@1 | 157 | \ |
| aoqi@1 | 158 | /* Use Restricted Transactional Memory for lock eliding */ \ |
| aoqi@1 | 159 | experimental(bool, UseRTMLocking, false, \ |
| aoqi@1 | 160 | "Enable RTM lock eliding for inflated locks in compiled code") \ |
| aoqi@1 | 161 | \ |
| aoqi@1 | 162 | experimental(bool, UseRTMForStackLocks, false, \ |
| aoqi@1 | 163 | "Enable RTM lock eliding for stack locks in compiled code") \ |
| aoqi@1 | 164 | \ |
| aoqi@1 | 165 | experimental(bool, UseRTMDeopt, false, \ |
| aoqi@1 | 166 | "Perform deopt and recompilation based on RTM abort ratio") \ |
| aoqi@1 | 167 | \ |
| aoqi@1 | 168 | experimental(uintx, RTMRetryCount, 5, \ |
| aoqi@1 | 169 | "Number of RTM retries on lock abort or busy") \ |
| aoqi@1 | 170 | \ |
| aoqi@1 | 171 | experimental(intx, RTMSpinLoopCount, 100, \ |
| aoqi@1 | 172 | "Spin count for lock to become free before RTM retry") \ |
| aoqi@1 | 173 | \ |
| aoqi@1 | 174 | experimental(intx, RTMAbortThreshold, 1000, \ |
| aoqi@1 | 175 | "Calculate abort ratio after this number of aborts") \ |
| aoqi@1 | 176 | \ |
| aoqi@1 | 177 | experimental(intx, RTMLockingThreshold, 10000, \ |
| aoqi@1 | 178 | "Lock count at which to do RTM lock eliding without " \ |
| aoqi@1 | 179 | "abort ratio calculation") \ |
| aoqi@1 | 180 | \ |
| aoqi@1 | 181 | experimental(intx, RTMAbortRatio, 50, \ |
| aoqi@1 | 182 | "Lock abort ratio at which to stop use RTM lock eliding") \ |
| aoqi@1 | 183 | \ |
| aoqi@1 | 184 | experimental(intx, RTMTotalCountIncrRate, 64, \ |
| aoqi@1 | 185 | "Increment total RTM attempted lock count once every n times") \ |
| aoqi@1 | 186 | \ |
| aoqi@1 | 187 | experimental(intx, RTMLockingCalculationDelay, 0, \ |
| aoqi@1 | 188 | "Number of milliseconds to wait before start calculating aborts " \ |
| aoqi@1 | 189 | "for RTM locking") \ |
| aoqi@1 | 190 | \ |
| aoqi@1 | 191 | experimental(bool, UseRTMXendForLockBusy, true, \ |
| aoqi@1 | 192 | "Use RTM Xend instead of Xabort when lock busy") \ |
| aoqi@1 | 193 | \ |
| aoqi@1 | 194 | product(bool, UseCountTrailingZerosInstruction, false, \ |
| aoqi@1 | 195 | "Use count trailing zeros instruction") \ |
| aoqi@1 | 196 | \ |
| aoqi@1 | 197 | product(bool, UseBMI1Instructions, false, \ |
| aoqi@1 | 198 | "Use BMI instructions") |
| aoqi@1 | 199 | |
| aoqi@1 | 200 | #endif // CPU_MIPS_VM_GLOBALS_MIPS_HPP |
| aoqi@1 | 201 |
