Wed, 19 Mar 2008 15:33:25 -0700
6662967: Optimize I2D conversion on new x86
Summary: Use CVTDQ2PS and CVTDQ2PD for integer values conversions to float and double values on new AMD cpu.
Reviewed-by: sgoldman, never
duke@435 | 1 | /* |
duke@435 | 2 | * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. |
duke@435 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
duke@435 | 4 | * |
duke@435 | 5 | * This code is free software; you can redistribute it and/or modify it |
duke@435 | 6 | * under the terms of the GNU General Public License version 2 only, as |
duke@435 | 7 | * published by the Free Software Foundation. |
duke@435 | 8 | * |
duke@435 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
duke@435 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
duke@435 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
duke@435 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
duke@435 | 13 | * accompanied this code). |
duke@435 | 14 | * |
duke@435 | 15 | * You should have received a copy of the GNU General Public License version |
duke@435 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
duke@435 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
duke@435 | 18 | * |
duke@435 | 19 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
duke@435 | 20 | * CA 95054 USA or visit www.sun.com if you need additional information or |
duke@435 | 21 | * have any questions. |
duke@435 | 22 | * |
duke@435 | 23 | */ |
duke@435 | 24 | |
duke@435 | 25 | # include "incls/_precompiled.incl" |
duke@435 | 26 | # include "incls/_vm_version_x86_32.cpp.incl" |
duke@435 | 27 | |
duke@435 | 28 | |
duke@435 | 29 | int VM_Version::_cpu; |
duke@435 | 30 | int VM_Version::_model; |
duke@435 | 31 | int VM_Version::_stepping; |
duke@435 | 32 | int VM_Version::_cpuFeatures; |
duke@435 | 33 | const char* VM_Version::_features_str = ""; |
duke@435 | 34 | VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
duke@435 | 35 | |
duke@435 | 36 | static BufferBlob* stub_blob; |
duke@435 | 37 | static const int stub_size = 300; |
duke@435 | 38 | |
duke@435 | 39 | extern "C" { |
duke@435 | 40 | typedef void (*getPsrInfo_stub_t)(void*); |
duke@435 | 41 | } |
duke@435 | 42 | static getPsrInfo_stub_t getPsrInfo_stub = NULL; |
duke@435 | 43 | |
duke@435 | 44 | |
duke@435 | 45 | class VM_Version_StubGenerator: public StubCodeGenerator { |
duke@435 | 46 | public: |
duke@435 | 47 | |
duke@435 | 48 | VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
duke@435 | 49 | |
duke@435 | 50 | address generate_getPsrInfo() { |
duke@435 | 51 | // Flags to test CPU type. |
duke@435 | 52 | const uint32_t EFL_AC = 0x40000; |
duke@435 | 53 | const uint32_t EFL_ID = 0x200000; |
duke@435 | 54 | // Values for when we don't have a CPUID instruction. |
duke@435 | 55 | const int CPU_FAMILY_SHIFT = 8; |
duke@435 | 56 | const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); |
duke@435 | 57 | const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); |
duke@435 | 58 | |
duke@435 | 59 | Label detect_486, cpu486, detect_586, std_cpuid1; |
duke@435 | 60 | Label ext_cpuid1, ext_cpuid5, done; |
duke@435 | 61 | |
duke@435 | 62 | StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); |
duke@435 | 63 | # define __ _masm-> |
duke@435 | 64 | |
duke@435 | 65 | address start = __ pc(); |
duke@435 | 66 | |
duke@435 | 67 | // |
duke@435 | 68 | // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); |
duke@435 | 69 | // |
duke@435 | 70 | __ pushl(rbp); |
duke@435 | 71 | __ movl(rbp, Address(rsp, 8)); // cpuid_info address |
duke@435 | 72 | __ pushl(rbx); |
duke@435 | 73 | __ pushl(rsi); |
duke@435 | 74 | __ pushfd(); // preserve rbx, and flags |
duke@435 | 75 | __ popl(rax); |
duke@435 | 76 | __ pushl(rax); |
duke@435 | 77 | __ movl(rcx, rax); |
duke@435 | 78 | // |
duke@435 | 79 | // if we are unable to change the AC flag, we have a 386 |
duke@435 | 80 | // |
duke@435 | 81 | __ xorl(rax, EFL_AC); |
duke@435 | 82 | __ pushl(rax); |
duke@435 | 83 | __ popfd(); |
duke@435 | 84 | __ pushfd(); |
duke@435 | 85 | __ popl(rax); |
duke@435 | 86 | __ cmpl(rax, rcx); |
duke@435 | 87 | __ jccb(Assembler::notEqual, detect_486); |
duke@435 | 88 | |
duke@435 | 89 | __ movl(rax, CPU_FAMILY_386); |
duke@435 | 90 | __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
duke@435 | 91 | __ jmp(done); |
duke@435 | 92 | |
duke@435 | 93 | // |
duke@435 | 94 | // If we are unable to change the ID flag, we have a 486 which does |
duke@435 | 95 | // not support the "cpuid" instruction. |
duke@435 | 96 | // |
duke@435 | 97 | __ bind(detect_486); |
duke@435 | 98 | __ movl(rax, rcx); |
duke@435 | 99 | __ xorl(rax, EFL_ID); |
duke@435 | 100 | __ pushl(rax); |
duke@435 | 101 | __ popfd(); |
duke@435 | 102 | __ pushfd(); |
duke@435 | 103 | __ popl(rax); |
duke@435 | 104 | __ cmpl(rcx, rax); |
duke@435 | 105 | __ jccb(Assembler::notEqual, detect_586); |
duke@435 | 106 | |
duke@435 | 107 | __ bind(cpu486); |
duke@435 | 108 | __ movl(rax, CPU_FAMILY_486); |
duke@435 | 109 | __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
duke@435 | 110 | __ jmp(done); |
duke@435 | 111 | |
duke@435 | 112 | // |
duke@435 | 113 | // at this point, we have a chip which supports the "cpuid" instruction |
duke@435 | 114 | // |
duke@435 | 115 | __ bind(detect_586); |
duke@435 | 116 | __ xorl(rax, rax); |
duke@435 | 117 | __ cpuid(); |
duke@435 | 118 | __ orl(rax, rax); |
duke@435 | 119 | __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input |
duke@435 | 120 | // value of at least 1, we give up and |
duke@435 | 121 | // assume a 486 |
duke@435 | 122 | __ leal(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
duke@435 | 123 | __ movl(Address(rsi, 0), rax); |
duke@435 | 124 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 125 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 126 | __ movl(Address(rsi,12), rdx); |
duke@435 | 127 | |
duke@435 | 128 | __ cmpl(rax, 3); // Is cpuid(0x4) supported? |
duke@435 | 129 | __ jccb(Assembler::belowEqual, std_cpuid1); |
duke@435 | 130 | |
duke@435 | 131 | // |
duke@435 | 132 | // cpuid(0x4) Deterministic cache params |
duke@435 | 133 | // |
duke@435 | 134 | __ movl(rax, 4); // and rcx already set to 0x0 |
duke@435 | 135 | __ xorl(rcx, rcx); |
duke@435 | 136 | __ cpuid(); |
duke@435 | 137 | __ pushl(rax); |
duke@435 | 138 | __ andl(rax, 0x1f); // Determine if valid cache parameters used |
duke@435 | 139 | __ orl(rax, rax); // rax,[4:0] == 0 indicates invalid cache |
duke@435 | 140 | __ popl(rax); |
duke@435 | 141 | __ jccb(Assembler::equal, std_cpuid1); |
duke@435 | 142 | |
duke@435 | 143 | __ leal(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
duke@435 | 144 | __ movl(Address(rsi, 0), rax); |
duke@435 | 145 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 146 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 147 | __ movl(Address(rsi,12), rdx); |
duke@435 | 148 | |
duke@435 | 149 | // |
duke@435 | 150 | // Standard cpuid(0x1) |
duke@435 | 151 | // |
duke@435 | 152 | __ bind(std_cpuid1); |
duke@435 | 153 | __ movl(rax, 1); |
duke@435 | 154 | __ cpuid(); |
duke@435 | 155 | __ leal(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
duke@435 | 156 | __ movl(Address(rsi, 0), rax); |
duke@435 | 157 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 158 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 159 | __ movl(Address(rsi,12), rdx); |
duke@435 | 160 | |
duke@435 | 161 | __ movl(rax, 0x80000000); |
duke@435 | 162 | __ cpuid(); |
duke@435 | 163 | __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
duke@435 | 164 | __ jcc(Assembler::belowEqual, done); |
duke@435 | 165 | __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
duke@435 | 166 | __ jccb(Assembler::belowEqual, ext_cpuid1); |
duke@435 | 167 | __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
duke@435 | 168 | __ jccb(Assembler::belowEqual, ext_cpuid5); |
duke@435 | 169 | // |
duke@435 | 170 | // Extended cpuid(0x80000008) |
duke@435 | 171 | // |
duke@435 | 172 | __ movl(rax, 0x80000008); |
duke@435 | 173 | __ cpuid(); |
duke@435 | 174 | __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
duke@435 | 175 | __ movl(Address(rsi, 0), rax); |
duke@435 | 176 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 177 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 178 | __ movl(Address(rsi,12), rdx); |
duke@435 | 179 | |
duke@435 | 180 | // |
duke@435 | 181 | // Extended cpuid(0x80000005) |
duke@435 | 182 | // |
duke@435 | 183 | __ bind(ext_cpuid5); |
duke@435 | 184 | __ movl(rax, 0x80000005); |
duke@435 | 185 | __ cpuid(); |
duke@435 | 186 | __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
duke@435 | 187 | __ movl(Address(rsi, 0), rax); |
duke@435 | 188 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 189 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 190 | __ movl(Address(rsi,12), rdx); |
duke@435 | 191 | |
duke@435 | 192 | // |
duke@435 | 193 | // Extended cpuid(0x80000001) |
duke@435 | 194 | // |
duke@435 | 195 | __ bind(ext_cpuid1); |
duke@435 | 196 | __ movl(rax, 0x80000001); |
duke@435 | 197 | __ cpuid(); |
duke@435 | 198 | __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
duke@435 | 199 | __ movl(Address(rsi, 0), rax); |
duke@435 | 200 | __ movl(Address(rsi, 4), rbx); |
duke@435 | 201 | __ movl(Address(rsi, 8), rcx); |
duke@435 | 202 | __ movl(Address(rsi,12), rdx); |
duke@435 | 203 | |
duke@435 | 204 | // |
duke@435 | 205 | // return |
duke@435 | 206 | // |
duke@435 | 207 | __ bind(done); |
duke@435 | 208 | __ popfd(); |
duke@435 | 209 | __ popl(rsi); |
duke@435 | 210 | __ popl(rbx); |
duke@435 | 211 | __ popl(rbp); |
duke@435 | 212 | __ ret(0); |
duke@435 | 213 | |
duke@435 | 214 | # undef __ |
duke@435 | 215 | |
duke@435 | 216 | return start; |
duke@435 | 217 | }; |
duke@435 | 218 | }; |
duke@435 | 219 | |
duke@435 | 220 | |
duke@435 | 221 | void VM_Version::get_processor_features() { |
duke@435 | 222 | |
duke@435 | 223 | _cpu = 4; // 486 by default |
duke@435 | 224 | _model = 0; |
duke@435 | 225 | _stepping = 0; |
duke@435 | 226 | _cpuFeatures = 0; |
duke@435 | 227 | _logical_processors_per_package = 1; |
duke@435 | 228 | if (!Use486InstrsOnly) { |
duke@435 | 229 | // Get raw processor info |
duke@435 | 230 | getPsrInfo_stub(&_cpuid_info); |
duke@435 | 231 | assert_is_initialized(); |
duke@435 | 232 | _cpu = extended_cpu_family(); |
duke@435 | 233 | _model = extended_cpu_model(); |
duke@435 | 234 | _stepping = cpu_stepping(); |
duke@435 | 235 | if (cpu_family() > 4) { // it supports CPUID |
duke@435 | 236 | _cpuFeatures = feature_flags(); |
duke@435 | 237 | // Logical processors are only available on P4s and above, |
duke@435 | 238 | // and only if hyperthreading is available. |
duke@435 | 239 | _logical_processors_per_package = logical_processor_count(); |
duke@435 | 240 | } |
duke@435 | 241 | } |
duke@435 | 242 | _supports_cx8 = supports_cmpxchg8(); |
duke@435 | 243 | // if the OS doesn't support SSE, we can't use this feature even if the HW does |
duke@435 | 244 | if( !os::supports_sse()) |
duke@435 | 245 | _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4|CPU_SSE4A); |
duke@435 | 246 | if (UseSSE < 4) |
duke@435 | 247 | _cpuFeatures &= ~CPU_SSE4; |
duke@435 | 248 | if (UseSSE < 3) { |
duke@435 | 249 | _cpuFeatures &= ~CPU_SSE3; |
duke@435 | 250 | _cpuFeatures &= ~CPU_SSSE3; |
duke@435 | 251 | _cpuFeatures &= ~CPU_SSE4A; |
duke@435 | 252 | } |
duke@435 | 253 | if (UseSSE < 2) |
duke@435 | 254 | _cpuFeatures &= ~CPU_SSE2; |
duke@435 | 255 | if (UseSSE < 1) |
duke@435 | 256 | _cpuFeatures &= ~CPU_SSE; |
duke@435 | 257 | |
duke@435 | 258 | if (logical_processors_per_package() == 1) { |
duke@435 | 259 | // HT processor could be installed on a system which doesn't support HT. |
duke@435 | 260 | _cpuFeatures &= ~CPU_HT; |
duke@435 | 261 | } |
duke@435 | 262 | |
duke@435 | 263 | char buf[256]; |
duke@435 | 264 | jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
duke@435 | 265 | cores_per_cpu(), threads_per_core(), |
duke@435 | 266 | cpu_family(), _model, _stepping, |
duke@435 | 267 | (supports_cmov() ? ", cmov" : ""), |
duke@435 | 268 | (supports_cmpxchg8() ? ", cx8" : ""), |
duke@435 | 269 | (supports_fxsr() ? ", fxsr" : ""), |
duke@435 | 270 | (supports_mmx() ? ", mmx" : ""), |
duke@435 | 271 | (supports_sse() ? ", sse" : ""), |
duke@435 | 272 | (supports_sse2() ? ", sse2" : ""), |
duke@435 | 273 | (supports_sse3() ? ", sse3" : ""), |
duke@435 | 274 | (supports_ssse3()? ", ssse3": ""), |
duke@435 | 275 | (supports_sse4() ? ", sse4" : ""), |
duke@435 | 276 | (supports_mmx_ext() ? ", mmxext" : ""), |
duke@435 | 277 | (supports_3dnow() ? ", 3dnow" : ""), |
duke@435 | 278 | (supports_3dnow2() ? ", 3dnowext" : ""), |
duke@435 | 279 | (supports_sse4a() ? ", sse4a": ""), |
duke@435 | 280 | (supports_ht() ? ", ht": "")); |
duke@435 | 281 | _features_str = strdup(buf); |
duke@435 | 282 | |
duke@435 | 283 | // UseSSE is set to the smaller of what hardware supports and what |
duke@435 | 284 | // the command line requires. I.e., you cannot set UseSSE to 2 on |
duke@435 | 285 | // older Pentiums which do not support it. |
duke@435 | 286 | if( UseSSE > 4 ) UseSSE=4; |
duke@435 | 287 | if( UseSSE < 0 ) UseSSE=0; |
duke@435 | 288 | if( !supports_sse4() ) // Drop to 3 if no SSE4 support |
duke@435 | 289 | UseSSE = MIN2((intx)3,UseSSE); |
duke@435 | 290 | if( !supports_sse3() ) // Drop to 2 if no SSE3 support |
duke@435 | 291 | UseSSE = MIN2((intx)2,UseSSE); |
duke@435 | 292 | if( !supports_sse2() ) // Drop to 1 if no SSE2 support |
duke@435 | 293 | UseSSE = MIN2((intx)1,UseSSE); |
duke@435 | 294 | if( !supports_sse () ) // Drop to 0 if no SSE support |
duke@435 | 295 | UseSSE = 0; |
duke@435 | 296 | |
duke@435 | 297 | // On new cpus instructions which update whole XMM register should be used |
duke@435 | 298 | // to prevent partial register stall due to dependencies on high half. |
duke@435 | 299 | // |
duke@435 | 300 | // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
duke@435 | 301 | // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
duke@435 | 302 | // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
duke@435 | 303 | // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
duke@435 | 304 | |
duke@435 | 305 | if( is_amd() ) { // AMD cpus specific settings |
duke@435 | 306 | if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
duke@435 | 307 | // Use it on new AMD cpus starting from Opteron. |
duke@435 | 308 | UseAddressNop = true; |
duke@435 | 309 | } |
duke@435 | 310 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
duke@435 | 311 | if( supports_sse4a() ) { |
duke@435 | 312 | UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
duke@435 | 313 | } else { |
duke@435 | 314 | UseXmmLoadAndClearUpper = false; |
duke@435 | 315 | } |
duke@435 | 316 | } |
duke@435 | 317 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
duke@435 | 318 | if( supports_sse4a() ) { |
duke@435 | 319 | UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
duke@435 | 320 | } else { |
duke@435 | 321 | UseXmmRegToRegMoveAll = false; |
duke@435 | 322 | } |
duke@435 | 323 | } |
kvn@506 | 324 | if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
kvn@506 | 325 | if( supports_sse4a() ) { |
kvn@506 | 326 | UseXmmI2F = true; |
kvn@506 | 327 | } else { |
kvn@506 | 328 | UseXmmI2F = false; |
kvn@506 | 329 | } |
kvn@506 | 330 | } |
kvn@506 | 331 | if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
kvn@506 | 332 | if( supports_sse4a() ) { |
kvn@506 | 333 | UseXmmI2D = true; |
kvn@506 | 334 | } else { |
kvn@506 | 335 | UseXmmI2D = false; |
kvn@506 | 336 | } |
kvn@506 | 337 | } |
duke@435 | 338 | } |
duke@435 | 339 | |
duke@435 | 340 | if( is_intel() ) { // Intel cpus specific settings |
duke@435 | 341 | if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
duke@435 | 342 | UseStoreImmI16 = false; // don't use it on Intel cpus |
duke@435 | 343 | } |
duke@435 | 344 | if( cpu_family() == 6 || cpu_family() == 15 ) { |
duke@435 | 345 | if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
duke@435 | 346 | // Use it on all Intel cpus starting from PentiumPro |
duke@435 | 347 | UseAddressNop = true; |
duke@435 | 348 | } |
duke@435 | 349 | } |
duke@435 | 350 | if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
duke@435 | 351 | UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
duke@435 | 352 | } |
duke@435 | 353 | if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
duke@435 | 354 | if( supports_sse3() ) { |
duke@435 | 355 | UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
duke@435 | 356 | } else { |
duke@435 | 357 | UseXmmRegToRegMoveAll = false; |
duke@435 | 358 | } |
duke@435 | 359 | } |
duke@435 | 360 | if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
duke@435 | 361 | #ifdef COMPILER2 |
duke@435 | 362 | if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
duke@435 | 363 | // For new Intel cpus do the next optimization: |
duke@435 | 364 | // don't align the beginning of a loop if there are enough instructions |
duke@435 | 365 | // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
duke@435 | 366 | // in current fetch line (OptoLoopAlignment) or the padding |
duke@435 | 367 | // is big (> MaxLoopPad). |
duke@435 | 368 | // Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
duke@435 | 369 | // generated NOP instructions. 11 is the largest size of one |
duke@435 | 370 | // address NOP instruction '0F 1F' (see Assembler::nop(i)). |
duke@435 | 371 | MaxLoopPad = 11; |
duke@435 | 372 | } |
duke@435 | 373 | #endif // COMPILER2 |
duke@435 | 374 | } |
duke@435 | 375 | } |
duke@435 | 376 | |
duke@435 | 377 | assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
duke@435 | 378 | assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
duke@435 | 379 | |
duke@435 | 380 | // set valid Prefetch instruction |
duke@435 | 381 | if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; |
duke@435 | 382 | if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; |
duke@435 | 383 | if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0; |
duke@435 | 384 | if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3; |
duke@435 | 385 | |
duke@435 | 386 | if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
duke@435 | 387 | if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; |
duke@435 | 388 | if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0; |
duke@435 | 389 | if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3; |
duke@435 | 390 | |
duke@435 | 391 | // Allocation prefetch settings |
duke@435 | 392 | intx cache_line_size = L1_data_cache_line_size(); |
duke@435 | 393 | if( cache_line_size > AllocatePrefetchStepSize ) |
duke@435 | 394 | AllocatePrefetchStepSize = cache_line_size; |
duke@435 | 395 | if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) |
duke@435 | 396 | AllocatePrefetchLines = 3; // Optimistic value |
duke@435 | 397 | assert(AllocatePrefetchLines > 0, "invalid value"); |
duke@435 | 398 | if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
duke@435 | 399 | AllocatePrefetchLines = 1; // Conservative value |
duke@435 | 400 | |
duke@435 | 401 | AllocatePrefetchDistance = allocate_prefetch_distance(); |
duke@435 | 402 | AllocatePrefetchStyle = allocate_prefetch_style(); |
duke@435 | 403 | |
duke@435 | 404 | if( AllocatePrefetchStyle == 2 && is_intel() && |
duke@435 | 405 | cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core |
duke@435 | 406 | AllocatePrefetchDistance = 320; |
duke@435 | 407 | } |
duke@435 | 408 | assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
duke@435 | 409 | |
duke@435 | 410 | #ifndef PRODUCT |
duke@435 | 411 | if (PrintMiscellaneous && Verbose) { |
duke@435 | 412 | tty->print_cr("Logical CPUs per package: %u", |
duke@435 | 413 | logical_processors_per_package()); |
duke@435 | 414 | tty->print_cr("UseSSE=%d",UseSSE); |
duke@435 | 415 | tty->print("Allocation: "); |
duke@435 | 416 | if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) { |
duke@435 | 417 | tty->print_cr("no prefetching"); |
duke@435 | 418 | } else { |
duke@435 | 419 | if (UseSSE == 0 && supports_3dnow()) { |
duke@435 | 420 | tty->print("PREFETCHW"); |
duke@435 | 421 | } else if (UseSSE >= 1) { |
duke@435 | 422 | if (AllocatePrefetchInstr == 0) { |
duke@435 | 423 | tty->print("PREFETCHNTA"); |
duke@435 | 424 | } else if (AllocatePrefetchInstr == 1) { |
duke@435 | 425 | tty->print("PREFETCHT0"); |
duke@435 | 426 | } else if (AllocatePrefetchInstr == 2) { |
duke@435 | 427 | tty->print("PREFETCHT2"); |
duke@435 | 428 | } else if (AllocatePrefetchInstr == 3) { |
duke@435 | 429 | tty->print("PREFETCHW"); |
duke@435 | 430 | } |
duke@435 | 431 | } |
duke@435 | 432 | if (AllocatePrefetchLines > 1) { |
duke@435 | 433 | tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
duke@435 | 434 | } else { |
duke@435 | 435 | tty->print_cr(" %d, one line", AllocatePrefetchDistance); |
duke@435 | 436 | } |
duke@435 | 437 | } |
duke@435 | 438 | } |
duke@435 | 439 | #endif // !PRODUCT |
duke@435 | 440 | } |
duke@435 | 441 | |
duke@435 | 442 | void VM_Version::initialize() { |
duke@435 | 443 | ResourceMark rm; |
duke@435 | 444 | // Making this stub must be FIRST use of assembler |
duke@435 | 445 | |
duke@435 | 446 | stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); |
duke@435 | 447 | if (stub_blob == NULL) { |
duke@435 | 448 | vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); |
duke@435 | 449 | } |
duke@435 | 450 | CodeBuffer c(stub_blob->instructions_begin(), |
duke@435 | 451 | stub_blob->instructions_size()); |
duke@435 | 452 | VM_Version_StubGenerator g(&c); |
duke@435 | 453 | getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, |
duke@435 | 454 | g.generate_getPsrInfo()); |
duke@435 | 455 | |
duke@435 | 456 | get_processor_features(); |
duke@435 | 457 | } |