Tue, 02 Sep 2014 12:48:45 -0700
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
Summary: Add new C2 intrinsic for BigInteger::multiplyToLen() on x86 in 64-bit VM.
Reviewed-by: roland
twisti@4318 | 1 | /* |
drchase@5353 | 2 | * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
twisti@4318 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
twisti@4318 | 4 | * |
twisti@4318 | 5 | * This code is free software; you can redistribute it and/or modify it |
twisti@4318 | 6 | * under the terms of the GNU General Public License version 2 only, as |
twisti@4318 | 7 | * published by the Free Software Foundation. |
twisti@4318 | 8 | * |
twisti@4318 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
twisti@4318 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
twisti@4318 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
twisti@4318 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
twisti@4318 | 13 | * accompanied this code). |
twisti@4318 | 14 | * |
twisti@4318 | 15 | * You should have received a copy of the GNU General Public License version |
twisti@4318 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
twisti@4318 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
twisti@4318 | 18 | * |
twisti@4318 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
twisti@4318 | 20 | * or visit www.oracle.com if you need additional information or have any |
twisti@4318 | 21 | * questions. |
twisti@4318 | 22 | * |
twisti@4318 | 23 | */ |
twisti@4318 | 24 | |
twisti@4318 | 25 | #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP |
twisti@4318 | 26 | #define CPU_X86_VM_MACROASSEMBLER_X86_HPP |
twisti@4318 | 27 | |
twisti@4318 | 28 | #include "asm/assembler.hpp" |
jprovino@4542 | 29 | #include "utilities/macros.hpp" |
kvn@6429 | 30 | #include "runtime/rtmLocking.hpp" |
twisti@4318 | 31 | |
twisti@4318 | 32 | |
twisti@4318 | 33 | // MacroAssembler extends Assembler by frequently used macros. |
twisti@4318 | 34 | // |
twisti@4318 | 35 | // Instructions for which a 'better' code sequence exists depending |
twisti@4318 | 36 | // on arguments should also go in here. |
twisti@4318 | 37 | |
twisti@4318 | 38 | class MacroAssembler: public Assembler { |
twisti@4318 | 39 | friend class LIR_Assembler; |
twisti@4318 | 40 | friend class Runtime1; // as_Address() |
twisti@4318 | 41 | |
twisti@4318 | 42 | protected: |
twisti@4318 | 43 | |
twisti@4318 | 44 | Address as_Address(AddressLiteral adr); |
twisti@4318 | 45 | Address as_Address(ArrayAddress adr); |
twisti@4318 | 46 | |
twisti@4318 | 47 | // Support for VM calls |
twisti@4318 | 48 | // |
twisti@4318 | 49 | // This is the base routine called by the different versions of call_VM_leaf. The interpreter |
twisti@4318 | 50 | // may customize this version by overriding it for its purposes (e.g., to save/restore |
twisti@4318 | 51 | // additional registers when doing a VM call). |
twisti@4318 | 52 | #ifdef CC_INTERP |
twisti@4318 | 53 | // c++ interpreter never wants to use interp_masm version of call_VM |
twisti@4318 | 54 | #define VIRTUAL |
twisti@4318 | 55 | #else |
twisti@4318 | 56 | #define VIRTUAL virtual |
twisti@4318 | 57 | #endif |
twisti@4318 | 58 | |
twisti@4318 | 59 | VIRTUAL void call_VM_leaf_base( |
twisti@4318 | 60 | address entry_point, // the entry point |
twisti@4318 | 61 | int number_of_arguments // the number of arguments to pop after the call |
twisti@4318 | 62 | ); |
twisti@4318 | 63 | |
twisti@4318 | 64 | // This is the base routine called by the different versions of call_VM. The interpreter |
twisti@4318 | 65 | // may customize this version by overriding it for its purposes (e.g., to save/restore |
twisti@4318 | 66 | // additional registers when doing a VM call). |
twisti@4318 | 67 | // |
twisti@4318 | 68 | // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base |
twisti@4318 | 69 | // returns the register which contains the thread upon return. If a thread register has been |
twisti@4318 | 70 | // specified, the return value will correspond to that register. If no last_java_sp is specified |
twisti@4318 | 71 | // (noreg) than rsp will be used instead. |
twisti@4318 | 72 | VIRTUAL void call_VM_base( // returns the register containing the thread upon return |
twisti@4318 | 73 | Register oop_result, // where an oop-result ends up if any; use noreg otherwise |
twisti@4318 | 74 | Register java_thread, // the thread if computed before ; use noreg otherwise |
twisti@4318 | 75 | Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise |
twisti@4318 | 76 | address entry_point, // the entry point |
twisti@4318 | 77 | int number_of_arguments, // the number of arguments (w/o thread) to pop after the call |
twisti@4318 | 78 | bool check_exceptions // whether to check for pending exceptions after return |
twisti@4318 | 79 | ); |
twisti@4318 | 80 | |
twisti@4318 | 81 | // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. |
twisti@4318 | 82 | // The implementation is only non-empty for the InterpreterMacroAssembler, |
twisti@4318 | 83 | // as only the interpreter handles PopFrame and ForceEarlyReturn requests. |
twisti@4318 | 84 | virtual void check_and_handle_popframe(Register java_thread); |
twisti@4318 | 85 | virtual void check_and_handle_earlyret(Register java_thread); |
twisti@4318 | 86 | |
twisti@4318 | 87 | void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); |
twisti@4318 | 88 | |
twisti@4318 | 89 | // helpers for FPU flag access |
twisti@4318 | 90 | // tmp is a temporary register, if none is available use noreg |
twisti@4318 | 91 | void save_rax (Register tmp); |
twisti@4318 | 92 | void restore_rax(Register tmp); |
twisti@4318 | 93 | |
twisti@4318 | 94 | public: |
twisti@4318 | 95 | MacroAssembler(CodeBuffer* code) : Assembler(code) {} |
twisti@4318 | 96 | |
twisti@4318 | 97 | // Support for NULL-checks |
twisti@4318 | 98 | // |
twisti@4318 | 99 | // Generates code that causes a NULL OS exception if the content of reg is NULL. |
twisti@4318 | 100 | // If the accessed location is M[reg + offset] and the offset is known, provide the |
twisti@4318 | 101 | // offset. No explicit code generation is needed if the offset is within a certain |
twisti@4318 | 102 | // range (0 <= offset <= page_size). |
twisti@4318 | 103 | |
twisti@4318 | 104 | void null_check(Register reg, int offset = -1); |
twisti@4318 | 105 | static bool needs_explicit_null_check(intptr_t offset); |
twisti@4318 | 106 | |
twisti@4318 | 107 | // Required platform-specific helpers for Label::patch_instructions. |
twisti@4318 | 108 | // They _shadow_ the declarations in AbstractAssembler, which are undefined. |
twisti@4318 | 109 | void pd_patch_instruction(address branch, address target) { |
twisti@4318 | 110 | unsigned char op = branch[0]; |
twisti@4318 | 111 | assert(op == 0xE8 /* call */ || |
twisti@4318 | 112 | op == 0xE9 /* jmp */ || |
twisti@4318 | 113 | op == 0xEB /* short jmp */ || |
twisti@4318 | 114 | (op & 0xF0) == 0x70 /* short jcc */ || |
kvn@6429 | 115 | op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ || |
kvn@6429 | 116 | op == 0xC7 && branch[1] == 0xF8 /* xbegin */, |
twisti@4318 | 117 | "Invalid opcode at patch point"); |
twisti@4318 | 118 | |
twisti@4318 | 119 | if (op == 0xEB || (op & 0xF0) == 0x70) { |
twisti@4318 | 120 | // short offset operators (jmp and jcc) |
twisti@4318 | 121 | char* disp = (char*) &branch[1]; |
twisti@4318 | 122 | int imm8 = target - (address) &disp[1]; |
twisti@4318 | 123 | guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset"); |
twisti@4318 | 124 | *disp = imm8; |
twisti@4318 | 125 | } else { |
kvn@6429 | 126 | int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1]; |
twisti@4318 | 127 | int imm32 = target - (address) &disp[1]; |
twisti@4318 | 128 | *disp = imm32; |
twisti@4318 | 129 | } |
twisti@4318 | 130 | } |
twisti@4318 | 131 | |
twisti@4318 | 132 | // The following 4 methods return the offset of the appropriate move instruction |
twisti@4318 | 133 | |
twisti@4318 | 134 | // Support for fast byte/short loading with zero extension (depending on particular CPU) |
twisti@4318 | 135 | int load_unsigned_byte(Register dst, Address src); |
twisti@4318 | 136 | int load_unsigned_short(Register dst, Address src); |
twisti@4318 | 137 | |
twisti@4318 | 138 | // Support for fast byte/short loading with sign extension (depending on particular CPU) |
twisti@4318 | 139 | int load_signed_byte(Register dst, Address src); |
twisti@4318 | 140 | int load_signed_short(Register dst, Address src); |
twisti@4318 | 141 | |
twisti@4318 | 142 | // Support for sign-extension (hi:lo = extend_sign(lo)) |
twisti@4318 | 143 | void extend_sign(Register hi, Register lo); |
twisti@4318 | 144 | |
twisti@4318 | 145 | // Load and store values by size and signed-ness |
twisti@4318 | 146 | void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); |
twisti@4318 | 147 | void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); |
twisti@4318 | 148 | |
twisti@4318 | 149 | // Support for inc/dec with optimal instruction selection depending on value |
twisti@4318 | 150 | |
twisti@4318 | 151 | void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } |
twisti@4318 | 152 | void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } |
twisti@4318 | 153 | |
twisti@4318 | 154 | void decrementl(Address dst, int value = 1); |
twisti@4318 | 155 | void decrementl(Register reg, int value = 1); |
twisti@4318 | 156 | |
twisti@4318 | 157 | void decrementq(Register reg, int value = 1); |
twisti@4318 | 158 | void decrementq(Address dst, int value = 1); |
twisti@4318 | 159 | |
twisti@4318 | 160 | void incrementl(Address dst, int value = 1); |
twisti@4318 | 161 | void incrementl(Register reg, int value = 1); |
twisti@4318 | 162 | |
twisti@4318 | 163 | void incrementq(Register reg, int value = 1); |
twisti@4318 | 164 | void incrementq(Address dst, int value = 1); |
twisti@4318 | 165 | |
twisti@4318 | 166 | // Support optimal SSE move instructions. |
twisti@4318 | 167 | void movflt(XMMRegister dst, XMMRegister src) { |
twisti@4318 | 168 | if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } |
twisti@4318 | 169 | else { movss (dst, src); return; } |
twisti@4318 | 170 | } |
twisti@4318 | 171 | void movflt(XMMRegister dst, Address src) { movss(dst, src); } |
twisti@4318 | 172 | void movflt(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 173 | void movflt(Address dst, XMMRegister src) { movss(dst, src); } |
twisti@4318 | 174 | |
twisti@4318 | 175 | void movdbl(XMMRegister dst, XMMRegister src) { |
twisti@4318 | 176 | if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } |
twisti@4318 | 177 | else { movsd (dst, src); return; } |
twisti@4318 | 178 | } |
twisti@4318 | 179 | |
twisti@4318 | 180 | void movdbl(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 181 | |
twisti@4318 | 182 | void movdbl(XMMRegister dst, Address src) { |
twisti@4318 | 183 | if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } |
twisti@4318 | 184 | else { movlpd(dst, src); return; } |
twisti@4318 | 185 | } |
twisti@4318 | 186 | void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } |
twisti@4318 | 187 | |
twisti@4318 | 188 | void incrementl(AddressLiteral dst); |
twisti@4318 | 189 | void incrementl(ArrayAddress dst); |
twisti@4318 | 190 | |
kvn@6429 | 191 | void incrementq(AddressLiteral dst); |
kvn@6429 | 192 | |
twisti@4318 | 193 | // Alignment |
twisti@4318 | 194 | void align(int modulus); |
twisti@4318 | 195 | |
twisti@4318 | 196 | // A 5 byte nop that is safe for patching (see patch_verified_entry) |
twisti@4318 | 197 | void fat_nop(); |
twisti@4318 | 198 | |
twisti@4318 | 199 | // Stack frame creation/removal |
twisti@4318 | 200 | void enter(); |
twisti@4318 | 201 | void leave(); |
twisti@4318 | 202 | |
twisti@4318 | 203 | // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) |
twisti@4318 | 204 | // The pointer will be loaded into the thread register. |
twisti@4318 | 205 | void get_thread(Register thread); |
twisti@4318 | 206 | |
twisti@4318 | 207 | |
twisti@4318 | 208 | // Support for VM calls |
twisti@4318 | 209 | // |
twisti@4318 | 210 | // It is imperative that all calls into the VM are handled via the call_VM macros. |
twisti@4318 | 211 | // They make sure that the stack linkage is setup correctly. call_VM's correspond |
twisti@4318 | 212 | // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. |
twisti@4318 | 213 | |
twisti@4318 | 214 | |
twisti@4318 | 215 | void call_VM(Register oop_result, |
twisti@4318 | 216 | address entry_point, |
twisti@4318 | 217 | bool check_exceptions = true); |
twisti@4318 | 218 | void call_VM(Register oop_result, |
twisti@4318 | 219 | address entry_point, |
twisti@4318 | 220 | Register arg_1, |
twisti@4318 | 221 | bool check_exceptions = true); |
twisti@4318 | 222 | void call_VM(Register oop_result, |
twisti@4318 | 223 | address entry_point, |
twisti@4318 | 224 | Register arg_1, Register arg_2, |
twisti@4318 | 225 | bool check_exceptions = true); |
twisti@4318 | 226 | void call_VM(Register oop_result, |
twisti@4318 | 227 | address entry_point, |
twisti@4318 | 228 | Register arg_1, Register arg_2, Register arg_3, |
twisti@4318 | 229 | bool check_exceptions = true); |
twisti@4318 | 230 | |
twisti@4318 | 231 | // Overloadings with last_Java_sp |
twisti@4318 | 232 | void call_VM(Register oop_result, |
twisti@4318 | 233 | Register last_java_sp, |
twisti@4318 | 234 | address entry_point, |
twisti@4318 | 235 | int number_of_arguments = 0, |
twisti@4318 | 236 | bool check_exceptions = true); |
twisti@4318 | 237 | void call_VM(Register oop_result, |
twisti@4318 | 238 | Register last_java_sp, |
twisti@4318 | 239 | address entry_point, |
twisti@4318 | 240 | Register arg_1, bool |
twisti@4318 | 241 | check_exceptions = true); |
twisti@4318 | 242 | void call_VM(Register oop_result, |
twisti@4318 | 243 | Register last_java_sp, |
twisti@4318 | 244 | address entry_point, |
twisti@4318 | 245 | Register arg_1, Register arg_2, |
twisti@4318 | 246 | bool check_exceptions = true); |
twisti@4318 | 247 | void call_VM(Register oop_result, |
twisti@4318 | 248 | Register last_java_sp, |
twisti@4318 | 249 | address entry_point, |
twisti@4318 | 250 | Register arg_1, Register arg_2, Register arg_3, |
twisti@4318 | 251 | bool check_exceptions = true); |
twisti@4318 | 252 | |
twisti@4318 | 253 | void get_vm_result (Register oop_result, Register thread); |
twisti@4318 | 254 | void get_vm_result_2(Register metadata_result, Register thread); |
twisti@4318 | 255 | |
twisti@4318 | 256 | // These always tightly bind to MacroAssembler::call_VM_base |
twisti@4318 | 257 | // bypassing the virtual implementation |
twisti@4318 | 258 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
twisti@4318 | 259 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); |
twisti@4318 | 260 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
twisti@4318 | 261 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
twisti@4318 | 262 | void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); |
twisti@4318 | 263 | |
twisti@4318 | 264 | void call_VM_leaf(address entry_point, |
twisti@4318 | 265 | int number_of_arguments = 0); |
twisti@4318 | 266 | void call_VM_leaf(address entry_point, |
twisti@4318 | 267 | Register arg_1); |
twisti@4318 | 268 | void call_VM_leaf(address entry_point, |
twisti@4318 | 269 | Register arg_1, Register arg_2); |
twisti@4318 | 270 | void call_VM_leaf(address entry_point, |
twisti@4318 | 271 | Register arg_1, Register arg_2, Register arg_3); |
twisti@4318 | 272 | |
twisti@4318 | 273 | // These always tightly bind to MacroAssembler::call_VM_leaf_base |
twisti@4318 | 274 | // bypassing the virtual implementation |
twisti@4318 | 275 | void super_call_VM_leaf(address entry_point); |
twisti@4318 | 276 | void super_call_VM_leaf(address entry_point, Register arg_1); |
twisti@4318 | 277 | void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); |
twisti@4318 | 278 | void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); |
twisti@4318 | 279 | void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); |
twisti@4318 | 280 | |
twisti@4318 | 281 | // last Java Frame (fills frame anchor) |
twisti@4318 | 282 | void set_last_Java_frame(Register thread, |
twisti@4318 | 283 | Register last_java_sp, |
twisti@4318 | 284 | Register last_java_fp, |
twisti@4318 | 285 | address last_java_pc); |
twisti@4318 | 286 | |
twisti@4318 | 287 | // thread in the default location (r15_thread on 64bit) |
twisti@4318 | 288 | void set_last_Java_frame(Register last_java_sp, |
twisti@4318 | 289 | Register last_java_fp, |
twisti@4318 | 290 | address last_java_pc); |
twisti@4318 | 291 | |
twisti@4318 | 292 | void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
twisti@4318 | 293 | |
twisti@4318 | 294 | // thread in the default location (r15_thread on 64bit) |
twisti@4318 | 295 | void reset_last_Java_frame(bool clear_fp, bool clear_pc); |
twisti@4318 | 296 | |
twisti@4318 | 297 | // Stores |
twisti@4318 | 298 | void store_check(Register obj); // store check for obj - register is destroyed afterwards |
twisti@4318 | 299 | void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) |
twisti@4318 | 300 | |
jprovino@4542 | 301 | #if INCLUDE_ALL_GCS |
twisti@4318 | 302 | |
twisti@4318 | 303 | void g1_write_barrier_pre(Register obj, |
twisti@4318 | 304 | Register pre_val, |
twisti@4318 | 305 | Register thread, |
twisti@4318 | 306 | Register tmp, |
twisti@4318 | 307 | bool tosca_live, |
twisti@4318 | 308 | bool expand_call); |
twisti@4318 | 309 | |
twisti@4318 | 310 | void g1_write_barrier_post(Register store_addr, |
twisti@4318 | 311 | Register new_val, |
twisti@4318 | 312 | Register thread, |
twisti@4318 | 313 | Register tmp, |
twisti@4318 | 314 | Register tmp2); |
twisti@4318 | 315 | |
jprovino@4542 | 316 | #endif // INCLUDE_ALL_GCS |
twisti@4318 | 317 | |
twisti@4318 | 318 | // split store_check(Register obj) to enhance instruction interleaving |
twisti@4318 | 319 | void store_check_part_1(Register obj); |
twisti@4318 | 320 | void store_check_part_2(Register obj); |
twisti@4318 | 321 | |
twisti@4318 | 322 | // C 'boolean' to Java boolean: x == 0 ? 0 : 1 |
twisti@4318 | 323 | void c2bool(Register x); |
twisti@4318 | 324 | |
twisti@4318 | 325 | // C++ bool manipulation |
twisti@4318 | 326 | |
twisti@4318 | 327 | void movbool(Register dst, Address src); |
twisti@4318 | 328 | void movbool(Address dst, bool boolconst); |
twisti@4318 | 329 | void movbool(Address dst, Register src); |
twisti@4318 | 330 | void testbool(Register dst); |
twisti@4318 | 331 | |
twisti@4318 | 332 | // oop manipulations |
twisti@4318 | 333 | void load_klass(Register dst, Register src); |
twisti@4318 | 334 | void store_klass(Register dst, Register src); |
twisti@4318 | 335 | |
twisti@4318 | 336 | void load_heap_oop(Register dst, Address src); |
twisti@4318 | 337 | void load_heap_oop_not_null(Register dst, Address src); |
twisti@4318 | 338 | void store_heap_oop(Address dst, Register src); |
twisti@4318 | 339 | void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg); |
twisti@4318 | 340 | |
twisti@4318 | 341 | // Used for storing NULL. All other oop constants should be |
twisti@4318 | 342 | // stored using routines that take a jobject. |
twisti@4318 | 343 | void store_heap_oop_null(Address dst); |
twisti@4318 | 344 | |
twisti@4318 | 345 | void load_prototype_header(Register dst, Register src); |
twisti@4318 | 346 | |
twisti@4318 | 347 | #ifdef _LP64 |
twisti@4318 | 348 | void store_klass_gap(Register dst, Register src); |
twisti@4318 | 349 | |
twisti@4318 | 350 | // This dummy is to prevent a call to store_heap_oop from |
twisti@4318 | 351 | // converting a zero (like NULL) into a Register by giving |
twisti@4318 | 352 | // the compiler two choices it can't resolve |
twisti@4318 | 353 | |
twisti@4318 | 354 | void store_heap_oop(Address dst, void* dummy); |
twisti@4318 | 355 | |
twisti@4318 | 356 | void encode_heap_oop(Register r); |
twisti@4318 | 357 | void decode_heap_oop(Register r); |
twisti@4318 | 358 | void encode_heap_oop_not_null(Register r); |
twisti@4318 | 359 | void decode_heap_oop_not_null(Register r); |
twisti@4318 | 360 | void encode_heap_oop_not_null(Register dst, Register src); |
twisti@4318 | 361 | void decode_heap_oop_not_null(Register dst, Register src); |
twisti@4318 | 362 | |
twisti@4318 | 363 | void set_narrow_oop(Register dst, jobject obj); |
twisti@4318 | 364 | void set_narrow_oop(Address dst, jobject obj); |
twisti@4318 | 365 | void cmp_narrow_oop(Register dst, jobject obj); |
twisti@4318 | 366 | void cmp_narrow_oop(Address dst, jobject obj); |
twisti@4318 | 367 | |
twisti@4318 | 368 | void encode_klass_not_null(Register r); |
twisti@4318 | 369 | void decode_klass_not_null(Register r); |
twisti@4318 | 370 | void encode_klass_not_null(Register dst, Register src); |
twisti@4318 | 371 | void decode_klass_not_null(Register dst, Register src); |
twisti@4318 | 372 | void set_narrow_klass(Register dst, Klass* k); |
twisti@4318 | 373 | void set_narrow_klass(Address dst, Klass* k); |
twisti@4318 | 374 | void cmp_narrow_klass(Register dst, Klass* k); |
twisti@4318 | 375 | void cmp_narrow_klass(Address dst, Klass* k); |
twisti@4318 | 376 | |
hseigel@5528 | 377 | // Returns the byte size of the instructions generated by decode_klass_not_null() |
hseigel@5528 | 378 | // when compressed klass pointers are being used. |
hseigel@5528 | 379 | static int instr_size_for_decode_klass_not_null(); |
hseigel@5528 | 380 | |
twisti@4318 | 381 | // if heap base register is used - reinit it with the correct value |
twisti@4318 | 382 | void reinit_heapbase(); |
twisti@4318 | 383 | |
twisti@4318 | 384 | DEBUG_ONLY(void verify_heapbase(const char* msg);) |
twisti@4318 | 385 | |
twisti@4318 | 386 | #endif // _LP64 |
twisti@4318 | 387 | |
twisti@4318 | 388 | // Int division/remainder for Java |
twisti@4318 | 389 | // (as idivl, but checks for special case as described in JVM spec.) |
twisti@4318 | 390 | // returns idivl instruction offset for implicit exception handling |
twisti@4318 | 391 | int corrected_idivl(Register reg); |
twisti@4318 | 392 | |
twisti@4318 | 393 | // Long division/remainder for Java |
twisti@4318 | 394 | // (as idivq, but checks for special case as described in JVM spec.) |
twisti@4318 | 395 | // returns idivq instruction offset for implicit exception handling |
twisti@4318 | 396 | int corrected_idivq(Register reg); |
twisti@4318 | 397 | |
twisti@4318 | 398 | void int3(); |
twisti@4318 | 399 | |
twisti@4318 | 400 | // Long operation macros for a 32bit cpu |
twisti@4318 | 401 | // Long negation for Java |
twisti@4318 | 402 | void lneg(Register hi, Register lo); |
twisti@4318 | 403 | |
twisti@4318 | 404 | // Long multiplication for Java |
twisti@4318 | 405 | // (destroys contents of eax, ebx, ecx and edx) |
twisti@4318 | 406 | void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
twisti@4318 | 407 | |
twisti@4318 | 408 | // Long shifts for Java |
twisti@4318 | 409 | // (semantics as described in JVM spec.) |
twisti@4318 | 410 | void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) |
twisti@4318 | 411 | void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) |
twisti@4318 | 412 | |
twisti@4318 | 413 | // Long compare for Java |
twisti@4318 | 414 | // (semantics as described in JVM spec.) |
twisti@4318 | 415 | void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) |
twisti@4318 | 416 | |
twisti@4318 | 417 | |
twisti@4318 | 418 | // misc |
twisti@4318 | 419 | |
twisti@4318 | 420 | // Sign extension |
twisti@4318 | 421 | void sign_extend_short(Register reg); |
twisti@4318 | 422 | void sign_extend_byte(Register reg); |
twisti@4318 | 423 | |
twisti@4318 | 424 | // Division by power of 2, rounding towards 0 |
twisti@4318 | 425 | void division_with_shift(Register reg, int shift_value); |
twisti@4318 | 426 | |
twisti@4318 | 427 | // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
twisti@4318 | 428 | // |
twisti@4318 | 429 | // CF (corresponds to C0) if x < y |
twisti@4318 | 430 | // PF (corresponds to C2) if unordered |
twisti@4318 | 431 | // ZF (corresponds to C3) if x = y |
twisti@4318 | 432 | // |
twisti@4318 | 433 | // The arguments are in reversed order on the stack (i.e., top of stack is first argument). |
twisti@4318 | 434 | // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) |
twisti@4318 | 435 | void fcmp(Register tmp); |
twisti@4318 | 436 | // Variant of the above which allows y to be further down the stack |
twisti@4318 | 437 | // and which only pops x and y if specified. If pop_right is |
twisti@4318 | 438 | // specified then pop_left must also be specified. |
twisti@4318 | 439 | void fcmp(Register tmp, int index, bool pop_left, bool pop_right); |
twisti@4318 | 440 | |
twisti@4318 | 441 | // Floating-point comparison for Java |
twisti@4318 | 442 | // Compares the top-most stack entries on the FPU stack and stores the result in dst. |
twisti@4318 | 443 | // The arguments are in reversed order on the stack (i.e., top of stack is first argument). |
twisti@4318 | 444 | // (semantics as described in JVM spec.) |
twisti@4318 | 445 | void fcmp2int(Register dst, bool unordered_is_less); |
twisti@4318 | 446 | // Variant of the above which allows y to be further down the stack |
twisti@4318 | 447 | // and which only pops x and y if specified. If pop_right is |
twisti@4318 | 448 | // specified then pop_left must also be specified. |
twisti@4318 | 449 | void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); |
twisti@4318 | 450 | |
twisti@4318 | 451 | // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) |
twisti@4318 | 452 | // tmp is a temporary register, if none is available use noreg |
twisti@4318 | 453 | void fremr(Register tmp); |
twisti@4318 | 454 | |
twisti@4318 | 455 | |
twisti@4318 | 456 | // same as fcmp2int, but using SSE2 |
twisti@4318 | 457 | void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); |
twisti@4318 | 458 | void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); |
twisti@4318 | 459 | |
twisti@4318 | 460 | // Inlined sin/cos generator for Java; must not use CPU instruction |
twisti@4318 | 461 | // directly on Intel as it does not have high enough precision |
twisti@4318 | 462 | // outside of the range [-pi/4, pi/4]. Extra argument indicate the |
twisti@4318 | 463 | // number of FPU stack slots in use; all but the topmost will |
twisti@4318 | 464 | // require saving if a slow case is necessary. Assumes argument is |
twisti@4318 | 465 | // on FP TOS; result is on FP TOS. No cpu registers are changed by |
twisti@4318 | 466 | // this code. |
twisti@4318 | 467 | void trigfunc(char trig, int num_fpu_regs_in_use = 1); |
twisti@4318 | 468 | |
twisti@4318 | 469 | // branch to L if FPU flag C2 is set/not set |
twisti@4318 | 470 | // tmp is a temporary register, if none is available use noreg |
twisti@4318 | 471 | void jC2 (Register tmp, Label& L); |
twisti@4318 | 472 | void jnC2(Register tmp, Label& L); |
twisti@4318 | 473 | |
twisti@4318 | 474 | // Pop ST (ffree & fincstp combined) |
twisti@4318 | 475 | void fpop(); |
twisti@4318 | 476 | |
twisti@4318 | 477 | // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack |
twisti@4318 | 478 | void push_fTOS(); |
twisti@4318 | 479 | |
twisti@4318 | 480 | // pops double TOS element from CPU stack and pushes on FPU stack |
twisti@4318 | 481 | void pop_fTOS(); |
twisti@4318 | 482 | |
twisti@4318 | 483 | void empty_FPU_stack(); |
twisti@4318 | 484 | |
twisti@4318 | 485 | void push_IU_state(); |
twisti@4318 | 486 | void pop_IU_state(); |
twisti@4318 | 487 | |
twisti@4318 | 488 | void push_FPU_state(); |
twisti@4318 | 489 | void pop_FPU_state(); |
twisti@4318 | 490 | |
twisti@4318 | 491 | void push_CPU_state(); |
twisti@4318 | 492 | void pop_CPU_state(); |
twisti@4318 | 493 | |
twisti@4318 | 494 | // Round up to a power of two |
twisti@4318 | 495 | void round_to(Register reg, int modulus); |
twisti@4318 | 496 | |
twisti@4318 | 497 | // Callee saved registers handling |
twisti@4318 | 498 | void push_callee_saved_registers(); |
twisti@4318 | 499 | void pop_callee_saved_registers(); |
twisti@4318 | 500 | |
twisti@4318 | 501 | // allocation |
twisti@4318 | 502 | void eden_allocate( |
twisti@4318 | 503 | Register obj, // result: pointer to object after successful allocation |
twisti@4318 | 504 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
twisti@4318 | 505 | int con_size_in_bytes, // object size in bytes if known at compile time |
twisti@4318 | 506 | Register t1, // temp register |
twisti@4318 | 507 | Label& slow_case // continuation point if fast allocation fails |
twisti@4318 | 508 | ); |
twisti@4318 | 509 | void tlab_allocate( |
twisti@4318 | 510 | Register obj, // result: pointer to object after successful allocation |
twisti@4318 | 511 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
twisti@4318 | 512 | int con_size_in_bytes, // object size in bytes if known at compile time |
twisti@4318 | 513 | Register t1, // temp register |
twisti@4318 | 514 | Register t2, // temp register |
twisti@4318 | 515 | Label& slow_case // continuation point if fast allocation fails |
twisti@4318 | 516 | ); |
twisti@4318 | 517 | Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address |
twisti@4318 | 518 | void incr_allocated_bytes(Register thread, |
twisti@4318 | 519 | Register var_size_in_bytes, int con_size_in_bytes, |
twisti@4318 | 520 | Register t1 = noreg); |
twisti@4318 | 521 | |
twisti@4318 | 522 | // interface method calling |
twisti@4318 | 523 | void lookup_interface_method(Register recv_klass, |
twisti@4318 | 524 | Register intf_klass, |
twisti@4318 | 525 | RegisterOrConstant itable_index, |
twisti@4318 | 526 | Register method_result, |
twisti@4318 | 527 | Register scan_temp, |
twisti@4318 | 528 | Label& no_such_interface); |
twisti@4318 | 529 | |
twisti@4318 | 530 | // virtual method calling |
twisti@4318 | 531 | void lookup_virtual_method(Register recv_klass, |
twisti@4318 | 532 | RegisterOrConstant vtable_index, |
twisti@4318 | 533 | Register method_result); |
twisti@4318 | 534 | |
twisti@4318 | 535 | // Test sub_klass against super_klass, with fast and slow paths. |
twisti@4318 | 536 | |
twisti@4318 | 537 | // The fast path produces a tri-state answer: yes / no / maybe-slow. |
twisti@4318 | 538 | // One of the three labels can be NULL, meaning take the fall-through. |
twisti@4318 | 539 | // If super_check_offset is -1, the value is loaded up from super_klass. |
twisti@4318 | 540 | // No registers are killed, except temp_reg. |
twisti@4318 | 541 | void check_klass_subtype_fast_path(Register sub_klass, |
twisti@4318 | 542 | Register super_klass, |
twisti@4318 | 543 | Register temp_reg, |
twisti@4318 | 544 | Label* L_success, |
twisti@4318 | 545 | Label* L_failure, |
twisti@4318 | 546 | Label* L_slow_path, |
twisti@4318 | 547 | RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
twisti@4318 | 548 | |
twisti@4318 | 549 | // The rest of the type check; must be wired to a corresponding fast path. |
twisti@4318 | 550 | // It does not repeat the fast path logic, so don't use it standalone. |
twisti@4318 | 551 | // The temp_reg and temp2_reg can be noreg, if no temps are available. |
twisti@4318 | 552 | // Updates the sub's secondary super cache as necessary. |
twisti@4318 | 553 | // If set_cond_codes, condition codes will be Z on success, NZ on failure. |
twisti@4318 | 554 | void check_klass_subtype_slow_path(Register sub_klass, |
twisti@4318 | 555 | Register super_klass, |
twisti@4318 | 556 | Register temp_reg, |
twisti@4318 | 557 | Register temp2_reg, |
twisti@4318 | 558 | Label* L_success, |
twisti@4318 | 559 | Label* L_failure, |
twisti@4318 | 560 | bool set_cond_codes = false); |
twisti@4318 | 561 | |
twisti@4318 | 562 | // Simplified, combined version, good for typical uses. |
twisti@4318 | 563 | // Falls through on failure. |
twisti@4318 | 564 | void check_klass_subtype(Register sub_klass, |
twisti@4318 | 565 | Register super_klass, |
twisti@4318 | 566 | Register temp_reg, |
twisti@4318 | 567 | Label& L_success); |
twisti@4318 | 568 | |
twisti@4318 | 569 | // method handles (JSR 292) |
twisti@4318 | 570 | Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); |
twisti@4318 | 571 | |
twisti@4318 | 572 | //---- |
twisti@4318 | 573 | void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 |
twisti@4318 | 574 | |
twisti@4318 | 575 | // Debugging |
twisti@4318 | 576 | |
twisti@4318 | 577 | // only if +VerifyOops |
twisti@4318 | 578 | // TODO: Make these macros with file and line like sparc version! |
twisti@4318 | 579 | void verify_oop(Register reg, const char* s = "broken oop"); |
twisti@4318 | 580 | void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
twisti@4318 | 581 | |
twisti@4318 | 582 | // TODO: verify method and klass metadata (compare against vptr?) |
twisti@4318 | 583 | void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} |
twisti@4318 | 584 | void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} |
twisti@4318 | 585 | |
twisti@4318 | 586 | #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) |
twisti@4318 | 587 | #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) |
twisti@4318 | 588 | |
twisti@4318 | 589 | // only if +VerifyFPU |
twisti@4318 | 590 | void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); |
twisti@4318 | 591 | |
kvn@4873 | 592 | // Verify or restore cpu control state after JNI call |
kvn@4873 | 593 | void restore_cpu_control_state_after_jni(); |
kvn@4873 | 594 | |
twisti@4318 | 595 | // prints msg, dumps registers and stops execution |
twisti@4318 | 596 | void stop(const char* msg); |
twisti@4318 | 597 | |
twisti@4318 | 598 | // prints msg and continues |
twisti@4318 | 599 | void warn(const char* msg); |
twisti@4318 | 600 | |
twisti@4318 | 601 | // dumps registers and other state |
twisti@4318 | 602 | void print_state(); |
twisti@4318 | 603 | |
twisti@4318 | 604 | static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); |
twisti@4318 | 605 | static void debug64(char* msg, int64_t pc, int64_t regs[]); |
twisti@4318 | 606 | static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip); |
twisti@4318 | 607 | static void print_state64(int64_t pc, int64_t regs[]); |
twisti@4318 | 608 | |
twisti@4318 | 609 | void os_breakpoint(); |
twisti@4318 | 610 | |
twisti@4318 | 611 | void untested() { stop("untested"); } |
twisti@4318 | 612 | |
twisti@4318 | 613 | void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
twisti@4318 | 614 | |
twisti@4318 | 615 | void should_not_reach_here() { stop("should not reach here"); } |
twisti@4318 | 616 | |
twisti@4318 | 617 | void print_CPU_state(); |
twisti@4318 | 618 | |
twisti@4318 | 619 | // Stack overflow checking |
twisti@4318 | 620 | void bang_stack_with_offset(int offset) { |
twisti@4318 | 621 | // stack grows down, caller passes positive offset |
twisti@4318 | 622 | assert(offset > 0, "must bang with negative offset"); |
twisti@4318 | 623 | movl(Address(rsp, (-offset)), rax); |
twisti@4318 | 624 | } |
twisti@4318 | 625 | |
twisti@4318 | 626 | // Writes to stack successive pages until offset reached to check for |
twisti@4318 | 627 | // stack overflow + shadow pages. Also, clobbers tmp |
twisti@4318 | 628 | void bang_stack_size(Register size, Register tmp); |
twisti@4318 | 629 | |
twisti@4318 | 630 | virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
twisti@4318 | 631 | Register tmp, |
twisti@4318 | 632 | int offset); |
twisti@4318 | 633 | |
twisti@4318 | 634 | // Support for serializing memory accesses between threads |
twisti@4318 | 635 | void serialize_memory(Register thread, Register tmp); |
twisti@4318 | 636 | |
twisti@4318 | 637 | void verify_tlab(); |
twisti@4318 | 638 | |
twisti@4318 | 639 | // Biased locking support |
twisti@4318 | 640 | // lock_reg and obj_reg must be loaded up with the appropriate values. |
twisti@4318 | 641 | // swap_reg must be rax, and is killed. |
twisti@4318 | 642 | // tmp_reg is optional. If it is supplied (i.e., != noreg) it will |
twisti@4318 | 643 | // be killed; if not supplied, push/pop will be used internally to |
twisti@4318 | 644 | // allocate a temporary (inefficient, avoid if possible). |
twisti@4318 | 645 | // Optional slow case is for implementations (interpreter and C1) which branch to |
twisti@4318 | 646 | // slow case directly. Leaves condition codes set for C2's Fast_Lock node. |
twisti@4318 | 647 | // Returns offset of first potentially-faulting instruction for null |
twisti@4318 | 648 | // check info (currently consumed only by C1). If |
twisti@4318 | 649 | // swap_reg_contains_mark is true then returns -1 as it is assumed |
twisti@4318 | 650 | // the calling code has already passed any potential faults. |
twisti@4318 | 651 | int biased_locking_enter(Register lock_reg, Register obj_reg, |
twisti@4318 | 652 | Register swap_reg, Register tmp_reg, |
twisti@4318 | 653 | bool swap_reg_contains_mark, |
twisti@4318 | 654 | Label& done, Label* slow_case = NULL, |
twisti@4318 | 655 | BiasedLockingCounters* counters = NULL); |
twisti@4318 | 656 | void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); |
kvn@6356 | 657 | #ifdef COMPILER2 |
kvn@6356 | 658 | // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file. |
kvn@6356 | 659 | // See full desription in macroAssembler_x86.cpp. |
kvn@6429 | 660 | void fast_lock(Register obj, Register box, Register tmp, |
kvn@6429 | 661 | Register scr, Register cx1, Register cx2, |
kvn@6429 | 662 | BiasedLockingCounters* counters, |
kvn@6429 | 663 | RTMLockingCounters* rtm_counters, |
kvn@6429 | 664 | RTMLockingCounters* stack_rtm_counters, |
kvn@6429 | 665 | Metadata* method_data, |
kvn@6429 | 666 | bool use_rtm, bool profile_rtm); |
kvn@6429 | 667 | void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm); |
kvn@6429 | 668 | #if INCLUDE_RTM_OPT |
kvn@6429 | 669 | void rtm_counters_update(Register abort_status, Register rtm_counters); |
kvn@6429 | 670 | void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel); |
kvn@6429 | 671 | void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg, |
kvn@6429 | 672 | RTMLockingCounters* rtm_counters, |
kvn@6429 | 673 | Metadata* method_data); |
kvn@6429 | 674 | void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg, |
kvn@6429 | 675 | RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm); |
kvn@6429 | 676 | void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel); |
kvn@6429 | 677 | void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel); |
kvn@6429 | 678 | void rtm_stack_locking(Register obj, Register tmp, Register scr, |
kvn@6429 | 679 | Register retry_on_abort_count, |
kvn@6429 | 680 | RTMLockingCounters* stack_rtm_counters, |
kvn@6429 | 681 | Metadata* method_data, bool profile_rtm, |
kvn@6429 | 682 | Label& DONE_LABEL, Label& IsInflated); |
kvn@6429 | 683 | void rtm_inflated_locking(Register obj, Register box, Register tmp, |
kvn@6429 | 684 | Register scr, Register retry_on_busy_count, |
kvn@6429 | 685 | Register retry_on_abort_count, |
kvn@6429 | 686 | RTMLockingCounters* rtm_counters, |
kvn@6429 | 687 | Metadata* method_data, bool profile_rtm, |
kvn@6429 | 688 | Label& DONE_LABEL); |
kvn@6429 | 689 | #endif |
kvn@6356 | 690 | #endif |
twisti@4318 | 691 | |
twisti@4318 | 692 | Condition negate_condition(Condition cond); |
twisti@4318 | 693 | |
twisti@4318 | 694 | // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit |
twisti@4318 | 695 | // operands. In general the names are modified to avoid hiding the instruction in Assembler |
twisti@4318 | 696 | // so that we don't need to implement all the varieties in the Assembler with trivial wrappers |
twisti@4318 | 697 | // here in MacroAssembler. The major exception to this rule is call |
twisti@4318 | 698 | |
twisti@4318 | 699 | // Arithmetics |
twisti@4318 | 700 | |
twisti@4318 | 701 | |
twisti@4318 | 702 | void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } |
twisti@4318 | 703 | void addptr(Address dst, Register src); |
twisti@4318 | 704 | |
twisti@4318 | 705 | void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } |
twisti@4318 | 706 | void addptr(Register dst, int32_t src); |
twisti@4318 | 707 | void addptr(Register dst, Register src); |
twisti@4318 | 708 | void addptr(Register dst, RegisterOrConstant src) { |
twisti@4318 | 709 | if (src.is_constant()) addptr(dst, (int) src.as_constant()); |
twisti@4318 | 710 | else addptr(dst, src.as_register()); |
twisti@4318 | 711 | } |
twisti@4318 | 712 | |
twisti@4318 | 713 | void andptr(Register dst, int32_t src); |
twisti@4318 | 714 | void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } |
twisti@4318 | 715 | |
twisti@4318 | 716 | void cmp8(AddressLiteral src1, int imm); |
twisti@4318 | 717 | |
twisti@4318 | 718 | // renamed to drag out the casting of address to int32_t/intptr_t |
twisti@4318 | 719 | void cmp32(Register src1, int32_t imm); |
twisti@4318 | 720 | |
twisti@4318 | 721 | void cmp32(AddressLiteral src1, int32_t imm); |
twisti@4318 | 722 | // compare reg - mem, or reg - &mem |
twisti@4318 | 723 | void cmp32(Register src1, AddressLiteral src2); |
twisti@4318 | 724 | |
twisti@4318 | 725 | void cmp32(Register src1, Address src2); |
twisti@4318 | 726 | |
twisti@4318 | 727 | #ifndef _LP64 |
twisti@4318 | 728 | void cmpklass(Address dst, Metadata* obj); |
twisti@4318 | 729 | void cmpklass(Register dst, Metadata* obj); |
twisti@4318 | 730 | void cmpoop(Address dst, jobject obj); |
twisti@4318 | 731 | void cmpoop(Register dst, jobject obj); |
twisti@4318 | 732 | #endif // _LP64 |
twisti@4318 | 733 | |
twisti@4318 | 734 | // NOTE src2 must be the lval. This is NOT an mem-mem compare |
twisti@4318 | 735 | void cmpptr(Address src1, AddressLiteral src2); |
twisti@4318 | 736 | |
twisti@4318 | 737 | void cmpptr(Register src1, AddressLiteral src2); |
twisti@4318 | 738 | |
twisti@4318 | 739 | void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
twisti@4318 | 740 | void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
twisti@4318 | 741 | // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
twisti@4318 | 742 | |
twisti@4318 | 743 | void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
twisti@4318 | 744 | void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
twisti@4318 | 745 | |
twisti@4318 | 746 | // cmp64 to avoild hiding cmpq |
twisti@4318 | 747 | void cmp64(Register src1, AddressLiteral src); |
twisti@4318 | 748 | |
twisti@4318 | 749 | void cmpxchgptr(Register reg, Address adr); |
twisti@4318 | 750 | |
twisti@4318 | 751 | void locked_cmpxchgptr(Register reg, AddressLiteral adr); |
twisti@4318 | 752 | |
twisti@4318 | 753 | |
twisti@4318 | 754 | void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } |
kvn@6429 | 755 | void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); } |
twisti@4318 | 756 | |
twisti@4318 | 757 | |
twisti@4318 | 758 | void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } |
twisti@4318 | 759 | |
twisti@4318 | 760 | void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } |
twisti@4318 | 761 | |
twisti@4318 | 762 | void shlptr(Register dst, int32_t shift); |
twisti@4318 | 763 | void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } |
twisti@4318 | 764 | |
twisti@4318 | 765 | void shrptr(Register dst, int32_t shift); |
twisti@4318 | 766 | void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } |
twisti@4318 | 767 | |
twisti@4318 | 768 | void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } |
twisti@4318 | 769 | void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } |
twisti@4318 | 770 | |
twisti@4318 | 771 | void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } |
twisti@4318 | 772 | |
twisti@4318 | 773 | void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } |
twisti@4318 | 774 | void subptr(Register dst, int32_t src); |
twisti@4318 | 775 | // Force generation of a 4 byte immediate value even if it fits into 8bit |
twisti@4318 | 776 | void subptr_imm32(Register dst, int32_t src); |
twisti@4318 | 777 | void subptr(Register dst, Register src); |
twisti@4318 | 778 | void subptr(Register dst, RegisterOrConstant src) { |
twisti@4318 | 779 | if (src.is_constant()) subptr(dst, (int) src.as_constant()); |
twisti@4318 | 780 | else subptr(dst, src.as_register()); |
twisti@4318 | 781 | } |
twisti@4318 | 782 | |
twisti@4318 | 783 | void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } |
twisti@4318 | 784 | void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } |
twisti@4318 | 785 | |
twisti@4318 | 786 | void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } |
twisti@4318 | 787 | void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } |
twisti@4318 | 788 | |
twisti@4318 | 789 | void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } |
twisti@4318 | 790 | |
twisti@4318 | 791 | |
twisti@4318 | 792 | |
twisti@4318 | 793 | // Helper functions for statistics gathering. |
twisti@4318 | 794 | // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. |
twisti@4318 | 795 | void cond_inc32(Condition cond, AddressLiteral counter_addr); |
twisti@4318 | 796 | // Unconditional atomic increment. |
kvn@6429 | 797 | void atomic_incl(Address counter_addr); |
kvn@6429 | 798 | void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1); |
kvn@6429 | 799 | #ifdef _LP64 |
kvn@6429 | 800 | void atomic_incq(Address counter_addr); |
kvn@6429 | 801 | void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1); |
kvn@6429 | 802 | #endif |
kvn@6429 | 803 | void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; } |
kvn@6429 | 804 | void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; } |
twisti@4318 | 805 | |
twisti@4318 | 806 | void lea(Register dst, AddressLiteral adr); |
twisti@4318 | 807 | void lea(Address dst, AddressLiteral adr); |
twisti@4318 | 808 | void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
twisti@4318 | 809 | |
twisti@4318 | 810 | void leal32(Register dst, Address src) { leal(dst, src); } |
twisti@4318 | 811 | |
twisti@4318 | 812 | // Import other testl() methods from the parent class or else |
twisti@4318 | 813 | // they will be hidden by the following overriding declaration. |
twisti@4318 | 814 | using Assembler::testl; |
twisti@4318 | 815 | void testl(Register dst, AddressLiteral src); |
twisti@4318 | 816 | |
twisti@4318 | 817 | void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
twisti@4318 | 818 | void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
twisti@4318 | 819 | void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
roland@5914 | 820 | void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); } |
twisti@4318 | 821 | |
twisti@4318 | 822 | void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } |
twisti@4318 | 823 | void testptr(Register src1, Register src2); |
twisti@4318 | 824 | |
twisti@4318 | 825 | void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } |
twisti@4318 | 826 | void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } |
twisti@4318 | 827 | |
twisti@4318 | 828 | // Calls |
twisti@4318 | 829 | |
twisti@4318 | 830 | void call(Label& L, relocInfo::relocType rtype); |
twisti@4318 | 831 | void call(Register entry); |
twisti@4318 | 832 | |
twisti@4318 | 833 | // NOTE: this call tranfers to the effective address of entry NOT |
twisti@4318 | 834 | // the address contained by entry. This is because this is more natural |
twisti@4318 | 835 | // for jumps/calls. |
twisti@4318 | 836 | void call(AddressLiteral entry); |
twisti@4318 | 837 | |
twisti@4318 | 838 | // Emit the CompiledIC call idiom |
twisti@4318 | 839 | void ic_call(address entry); |
twisti@4318 | 840 | |
twisti@4318 | 841 | // Jumps |
twisti@4318 | 842 | |
twisti@4318 | 843 | // NOTE: these jumps tranfer to the effective address of dst NOT |
twisti@4318 | 844 | // the address contained by dst. This is because this is more natural |
twisti@4318 | 845 | // for jumps/calls. |
twisti@4318 | 846 | void jump(AddressLiteral dst); |
twisti@4318 | 847 | void jump_cc(Condition cc, AddressLiteral dst); |
twisti@4318 | 848 | |
twisti@4318 | 849 | // 32bit can do a case table jump in one instruction but we no longer allow the base |
twisti@4318 | 850 | // to be installed in the Address class. This jump will tranfers to the address |
twisti@4318 | 851 | // contained in the location described by entry (not the address of entry) |
twisti@4318 | 852 | void jump(ArrayAddress entry); |
twisti@4318 | 853 | |
twisti@4318 | 854 | // Floating |
twisti@4318 | 855 | |
twisti@4318 | 856 | void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } |
twisti@4318 | 857 | void andpd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 858 | |
twisti@4318 | 859 | void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } |
twisti@4318 | 860 | void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } |
twisti@4318 | 861 | void andps(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 862 | |
twisti@4318 | 863 | void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } |
twisti@4318 | 864 | void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } |
twisti@4318 | 865 | void comiss(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 866 | |
twisti@4318 | 867 | void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } |
twisti@4318 | 868 | void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } |
twisti@4318 | 869 | void comisd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 870 | |
twisti@4318 | 871 | void fadd_s(Address src) { Assembler::fadd_s(src); } |
twisti@4318 | 872 | void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } |
twisti@4318 | 873 | |
twisti@4318 | 874 | void fldcw(Address src) { Assembler::fldcw(src); } |
twisti@4318 | 875 | void fldcw(AddressLiteral src); |
twisti@4318 | 876 | |
twisti@4318 | 877 | void fld_s(int index) { Assembler::fld_s(index); } |
twisti@4318 | 878 | void fld_s(Address src) { Assembler::fld_s(src); } |
twisti@4318 | 879 | void fld_s(AddressLiteral src); |
twisti@4318 | 880 | |
twisti@4318 | 881 | void fld_d(Address src) { Assembler::fld_d(src); } |
twisti@4318 | 882 | void fld_d(AddressLiteral src); |
twisti@4318 | 883 | |
twisti@4318 | 884 | void fld_x(Address src) { Assembler::fld_x(src); } |
twisti@4318 | 885 | void fld_x(AddressLiteral src); |
twisti@4318 | 886 | |
twisti@4318 | 887 | void fmul_s(Address src) { Assembler::fmul_s(src); } |
twisti@4318 | 888 | void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } |
twisti@4318 | 889 | |
twisti@4318 | 890 | void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
twisti@4318 | 891 | void ldmxcsr(AddressLiteral src); |
twisti@4318 | 892 | |
twisti@4318 | 893 | // compute pow(x,y) and exp(x) with x86 instructions. Don't cover |
twisti@4318 | 894 | // all corner cases and may result in NaN and require fallback to a |
twisti@4318 | 895 | // runtime call. |
twisti@4318 | 896 | void fast_pow(); |
twisti@4318 | 897 | void fast_exp(); |
twisti@4318 | 898 | void increase_precision(); |
twisti@4318 | 899 | void restore_precision(); |
twisti@4318 | 900 | |
twisti@4318 | 901 | // computes exp(x). Fallback to runtime call included. |
twisti@4318 | 902 | void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); } |
twisti@4318 | 903 | // computes pow(x,y). Fallback to runtime call included. |
twisti@4318 | 904 | void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); } |
twisti@4318 | 905 | |
twisti@4318 | 906 | private: |
twisti@4318 | 907 | |
twisti@4318 | 908 | // call runtime as a fallback for trig functions and pow/exp. |
twisti@4318 | 909 | void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use); |
twisti@4318 | 910 | |
twisti@4318 | 911 | // computes 2^(Ylog2X); Ylog2X in ST(0) |
twisti@4318 | 912 | void pow_exp_core_encoding(); |
twisti@4318 | 913 | |
twisti@4318 | 914 | // computes pow(x,y) or exp(x). Fallback to runtime call included. |
twisti@4318 | 915 | void pow_or_exp(bool is_exp, int num_fpu_regs_in_use); |
twisti@4318 | 916 | |
twisti@4318 | 917 | // these are private because users should be doing movflt/movdbl |
twisti@4318 | 918 | |
twisti@4318 | 919 | void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
twisti@4318 | 920 | void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } |
twisti@4318 | 921 | void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } |
twisti@4318 | 922 | void movss(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 923 | |
twisti@4318 | 924 | void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
twisti@4318 | 925 | void movlpd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 926 | |
twisti@4318 | 927 | public: |
twisti@4318 | 928 | |
twisti@4318 | 929 | void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } |
twisti@4318 | 930 | void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } |
twisti@4318 | 931 | void addsd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 932 | |
twisti@4318 | 933 | void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } |
twisti@4318 | 934 | void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } |
twisti@4318 | 935 | void addss(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 936 | |
twisti@4318 | 937 | void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } |
twisti@4318 | 938 | void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } |
twisti@4318 | 939 | void divsd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 940 | |
twisti@4318 | 941 | void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } |
twisti@4318 | 942 | void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } |
twisti@4318 | 943 | void divss(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 944 | |
twisti@4318 | 945 | // Move Unaligned Double Quadword |
twisti@4318 | 946 | void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); } |
twisti@4318 | 947 | void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); } |
twisti@4318 | 948 | void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); } |
twisti@4318 | 949 | void movdqu(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 950 | |
drchase@5353 | 951 | // Move Aligned Double Quadword |
drchase@5353 | 952 | void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); } |
drchase@5353 | 953 | void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); } |
drchase@5353 | 954 | void movdqa(XMMRegister dst, AddressLiteral src); |
drchase@5353 | 955 | |
twisti@4318 | 956 | void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
twisti@4318 | 957 | void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } |
twisti@4318 | 958 | void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } |
twisti@4318 | 959 | void movsd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 960 | |
twisti@4318 | 961 | void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } |
twisti@4318 | 962 | void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } |
twisti@4318 | 963 | void mulsd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 964 | |
twisti@4318 | 965 | void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } |
twisti@4318 | 966 | void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } |
twisti@4318 | 967 | void mulss(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 968 | |
kvn@7025 | 969 | // Carry-Less Multiplication Quadword |
kvn@7025 | 970 | void pclmulldq(XMMRegister dst, XMMRegister src) { |
kvn@7025 | 971 | // 0x00 - multiply lower 64 bits [0:63] |
kvn@7025 | 972 | Assembler::pclmulqdq(dst, src, 0x00); |
kvn@7025 | 973 | } |
kvn@7025 | 974 | void pclmulhdq(XMMRegister dst, XMMRegister src) { |
kvn@7025 | 975 | // 0x11 - multiply upper 64 bits [64:127] |
kvn@7025 | 976 | Assembler::pclmulqdq(dst, src, 0x11); |
kvn@7025 | 977 | } |
kvn@7025 | 978 | |
twisti@4318 | 979 | void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } |
twisti@4318 | 980 | void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } |
twisti@4318 | 981 | void sqrtsd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 982 | |
twisti@4318 | 983 | void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } |
twisti@4318 | 984 | void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } |
twisti@4318 | 985 | void sqrtss(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 986 | |
twisti@4318 | 987 | void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } |
twisti@4318 | 988 | void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } |
twisti@4318 | 989 | void subsd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 990 | |
twisti@4318 | 991 | void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } |
twisti@4318 | 992 | void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } |
twisti@4318 | 993 | void subss(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 994 | |
twisti@4318 | 995 | void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } |
twisti@4318 | 996 | void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } |
twisti@4318 | 997 | void ucomiss(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 998 | |
twisti@4318 | 999 | void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } |
twisti@4318 | 1000 | void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } |
twisti@4318 | 1001 | void ucomisd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 1002 | |
twisti@4318 | 1003 | // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values |
twisti@4318 | 1004 | void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } |
twisti@4318 | 1005 | void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } |
twisti@4318 | 1006 | void xorpd(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 1007 | |
twisti@4318 | 1008 | // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values |
twisti@4318 | 1009 | void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } |
twisti@4318 | 1010 | void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } |
twisti@4318 | 1011 | void xorps(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 1012 | |
twisti@4318 | 1013 | // Shuffle Bytes |
twisti@4318 | 1014 | void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); } |
twisti@4318 | 1015 | void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); } |
twisti@4318 | 1016 | void pshufb(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 1017 | // AVX 3-operands instructions |
twisti@4318 | 1018 | |
twisti@4318 | 1019 | void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } |
twisti@4318 | 1020 | void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } |
twisti@4318 | 1021 | void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
twisti@4318 | 1022 | |
twisti@4318 | 1023 | void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } |
twisti@4318 | 1024 | void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } |
twisti@4318 | 1025 | void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
twisti@4318 | 1026 | |
twisti@4318 | 1027 | void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); } |
twisti@4318 | 1028 | void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); } |
twisti@4318 | 1029 | void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); |
twisti@4318 | 1030 | |
twisti@4318 | 1031 | void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); } |
twisti@4318 | 1032 | void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); } |
twisti@4318 | 1033 | void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); |
twisti@4318 | 1034 | |
twisti@4318 | 1035 | void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } |
twisti@4318 | 1036 | void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } |
twisti@4318 | 1037 | void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
twisti@4318 | 1038 | |
twisti@4318 | 1039 | void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } |
twisti@4318 | 1040 | void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } |
twisti@4318 | 1041 | void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
twisti@4318 | 1042 | |
twisti@4318 | 1043 | void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } |
twisti@4318 | 1044 | void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } |
twisti@4318 | 1045 | void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
twisti@4318 | 1046 | |
twisti@4318 | 1047 | void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } |
twisti@4318 | 1048 | void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } |
twisti@4318 | 1049 | void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
twisti@4318 | 1050 | |
twisti@4318 | 1051 | void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } |
twisti@4318 | 1052 | void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } |
twisti@4318 | 1053 | void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
twisti@4318 | 1054 | |
twisti@4318 | 1055 | void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } |
twisti@4318 | 1056 | void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } |
twisti@4318 | 1057 | void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
twisti@4318 | 1058 | |
twisti@4318 | 1059 | // AVX Vector instructions |
twisti@4318 | 1060 | |
twisti@4318 | 1061 | void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } |
twisti@4318 | 1062 | void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } |
twisti@4318 | 1063 | void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); |
twisti@4318 | 1064 | |
twisti@4318 | 1065 | void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } |
twisti@4318 | 1066 | void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } |
twisti@4318 | 1067 | void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); |
twisti@4318 | 1068 | |
twisti@4318 | 1069 | void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
twisti@4318 | 1070 | if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 |
twisti@4318 | 1071 | Assembler::vpxor(dst, nds, src, vector256); |
twisti@4318 | 1072 | else |
twisti@4318 | 1073 | Assembler::vxorpd(dst, nds, src, vector256); |
twisti@4318 | 1074 | } |
twisti@4318 | 1075 | void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
twisti@4318 | 1076 | if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 |
twisti@4318 | 1077 | Assembler::vpxor(dst, nds, src, vector256); |
twisti@4318 | 1078 | else |
twisti@4318 | 1079 | Assembler::vxorpd(dst, nds, src, vector256); |
twisti@4318 | 1080 | } |
twisti@4318 | 1081 | |
kvn@4413 | 1082 | // Simple version for AVX2 256bit vectors |
kvn@4413 | 1083 | void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); } |
kvn@4413 | 1084 | void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); } |
kvn@4413 | 1085 | |
twisti@4318 | 1086 | // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector. |
twisti@4318 | 1087 | void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
twisti@4318 | 1088 | if (UseAVX > 1) // vinserti128h is available only in AVX2 |
twisti@4318 | 1089 | Assembler::vinserti128h(dst, nds, src); |
twisti@4318 | 1090 | else |
twisti@4318 | 1091 | Assembler::vinsertf128h(dst, nds, src); |
twisti@4318 | 1092 | } |
twisti@4318 | 1093 | |
drchase@5353 | 1094 | // Carry-Less Multiplication Quadword |
drchase@5353 | 1095 | void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
drchase@5353 | 1096 | // 0x00 - multiply lower 64 bits [0:63] |
drchase@5353 | 1097 | Assembler::vpclmulqdq(dst, nds, src, 0x00); |
drchase@5353 | 1098 | } |
drchase@5353 | 1099 | void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
drchase@5353 | 1100 | // 0x11 - multiply upper 64 bits [64:127] |
drchase@5353 | 1101 | Assembler::vpclmulqdq(dst, nds, src, 0x11); |
drchase@5353 | 1102 | } |
drchase@5353 | 1103 | |
twisti@4318 | 1104 | // Data |
twisti@4318 | 1105 | |
twisti@4318 | 1106 | void cmov32( Condition cc, Register dst, Address src); |
twisti@4318 | 1107 | void cmov32( Condition cc, Register dst, Register src); |
twisti@4318 | 1108 | |
twisti@4318 | 1109 | void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } |
twisti@4318 | 1110 | |
twisti@4318 | 1111 | void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
twisti@4318 | 1112 | void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
twisti@4318 | 1113 | |
twisti@4318 | 1114 | void movoop(Register dst, jobject obj); |
twisti@4318 | 1115 | void movoop(Address dst, jobject obj); |
twisti@4318 | 1116 | |
twisti@4318 | 1117 | void mov_metadata(Register dst, Metadata* obj); |
twisti@4318 | 1118 | void mov_metadata(Address dst, Metadata* obj); |
twisti@4318 | 1119 | |
twisti@4318 | 1120 | void movptr(ArrayAddress dst, Register src); |
twisti@4318 | 1121 | // can this do an lea? |
twisti@4318 | 1122 | void movptr(Register dst, ArrayAddress src); |
twisti@4318 | 1123 | |
twisti@4318 | 1124 | void movptr(Register dst, Address src); |
twisti@4318 | 1125 | |
kvn@6429 | 1126 | #ifdef _LP64 |
kvn@6429 | 1127 | void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1); |
kvn@6429 | 1128 | #else |
kvn@6429 | 1129 | void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit |
kvn@6429 | 1130 | #endif |
twisti@4318 | 1131 | |
twisti@4318 | 1132 | void movptr(Register dst, intptr_t src); |
twisti@4318 | 1133 | void movptr(Register dst, Register src); |
twisti@4318 | 1134 | void movptr(Address dst, intptr_t src); |
twisti@4318 | 1135 | |
twisti@4318 | 1136 | void movptr(Address dst, Register src); |
twisti@4318 | 1137 | |
twisti@4318 | 1138 | void movptr(Register dst, RegisterOrConstant src) { |
twisti@4318 | 1139 | if (src.is_constant()) movptr(dst, src.as_constant()); |
twisti@4318 | 1140 | else movptr(dst, src.as_register()); |
twisti@4318 | 1141 | } |
twisti@4318 | 1142 | |
twisti@4318 | 1143 | #ifdef _LP64 |
twisti@4318 | 1144 | // Generally the next two are only used for moving NULL |
twisti@4318 | 1145 | // Although there are situations in initializing the mark word where |
twisti@4318 | 1146 | // they could be used. They are dangerous. |
twisti@4318 | 1147 | |
twisti@4318 | 1148 | // They only exist on LP64 so that int32_t and intptr_t are not the same |
twisti@4318 | 1149 | // and we have ambiguous declarations. |
twisti@4318 | 1150 | |
twisti@4318 | 1151 | void movptr(Address dst, int32_t imm32); |
twisti@4318 | 1152 | void movptr(Register dst, int32_t imm32); |
twisti@4318 | 1153 | #endif // _LP64 |
twisti@4318 | 1154 | |
twisti@4318 | 1155 | // to avoid hiding movl |
twisti@4318 | 1156 | void mov32(AddressLiteral dst, Register src); |
twisti@4318 | 1157 | void mov32(Register dst, AddressLiteral src); |
twisti@4318 | 1158 | |
twisti@4318 | 1159 | // to avoid hiding movb |
twisti@4318 | 1160 | void movbyte(ArrayAddress dst, int src); |
twisti@4318 | 1161 | |
twisti@4318 | 1162 | // Import other mov() methods from the parent class or else |
twisti@4318 | 1163 | // they will be hidden by the following overriding declaration. |
twisti@4318 | 1164 | using Assembler::movdl; |
twisti@4318 | 1165 | using Assembler::movq; |
twisti@4318 | 1166 | void movdl(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 1167 | void movq(XMMRegister dst, AddressLiteral src); |
twisti@4318 | 1168 | |
twisti@4318 | 1169 | // Can push value or effective address |
twisti@4318 | 1170 | void pushptr(AddressLiteral src); |
twisti@4318 | 1171 | |
twisti@4318 | 1172 | void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
twisti@4318 | 1173 | void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } |
twisti@4318 | 1174 | |
twisti@4318 | 1175 | void pushoop(jobject obj); |
twisti@4318 | 1176 | void pushklass(Metadata* obj); |
twisti@4318 | 1177 | |
twisti@4318 | 1178 | // sign extend as need a l to ptr sized element |
twisti@4318 | 1179 | void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } |
twisti@4318 | 1180 | void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } |
twisti@4318 | 1181 | |
twisti@4318 | 1182 | // C2 compiled method's prolog code. |
roland@6723 | 1183 | void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b); |
twisti@4318 | 1184 | |
kvn@4410 | 1185 | // clear memory of size 'cnt' qwords, starting at 'base'. |
kvn@4410 | 1186 | void clear_mem(Register base, Register cnt, Register rtmp); |
kvn@4410 | 1187 | |
twisti@4318 | 1188 | // IndexOf strings. |
twisti@4318 | 1189 | // Small strings are loaded through stack if they cross page boundary. |
twisti@4318 | 1190 | void string_indexof(Register str1, Register str2, |
twisti@4318 | 1191 | Register cnt1, Register cnt2, |
twisti@4318 | 1192 | int int_cnt2, Register result, |
twisti@4318 | 1193 | XMMRegister vec, Register tmp); |
twisti@4318 | 1194 | |
twisti@4318 | 1195 | // IndexOf for constant substrings with size >= 8 elements |
twisti@4318 | 1196 | // which don't need to be loaded through stack. |
twisti@4318 | 1197 | void string_indexofC8(Register str1, Register str2, |
twisti@4318 | 1198 | Register cnt1, Register cnt2, |
twisti@4318 | 1199 | int int_cnt2, Register result, |
twisti@4318 | 1200 | XMMRegister vec, Register tmp); |
twisti@4318 | 1201 | |
twisti@4318 | 1202 | // Smallest code: we don't need to load through stack, |
twisti@4318 | 1203 | // check string tail. |
twisti@4318 | 1204 | |
twisti@4318 | 1205 | // Compare strings. |
twisti@4318 | 1206 | void string_compare(Register str1, Register str2, |
twisti@4318 | 1207 | Register cnt1, Register cnt2, Register result, |
twisti@4318 | 1208 | XMMRegister vec1); |
twisti@4318 | 1209 | |
twisti@4318 | 1210 | // Compare char[] arrays. |
twisti@4318 | 1211 | void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
twisti@4318 | 1212 | Register limit, Register result, Register chr, |
twisti@4318 | 1213 | XMMRegister vec1, XMMRegister vec2); |
twisti@4318 | 1214 | |
twisti@4318 | 1215 | // Fill primitive arrays |
twisti@4318 | 1216 | void generate_fill(BasicType t, bool aligned, |
twisti@4318 | 1217 | Register to, Register value, Register count, |
twisti@4318 | 1218 | Register rtmp, XMMRegister xtmp); |
twisti@4318 | 1219 | |
kvn@4479 | 1220 | void encode_iso_array(Register src, Register dst, Register len, |
kvn@4479 | 1221 | XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3, |
kvn@4479 | 1222 | XMMRegister tmp4, Register tmp5, Register result); |
kvn@4479 | 1223 | |
kvn@7152 | 1224 | #ifdef _LP64 |
kvn@7152 | 1225 | void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2); |
kvn@7152 | 1226 | void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, |
kvn@7152 | 1227 | Register y, Register y_idx, Register z, |
kvn@7152 | 1228 | Register carry, Register product, |
kvn@7152 | 1229 | Register idx, Register kdx); |
kvn@7152 | 1230 | void multiply_add_128_x_128(Register x_xstart, Register y, Register z, |
kvn@7152 | 1231 | Register yz_idx, Register idx, |
kvn@7152 | 1232 | Register carry, Register product, int offset); |
kvn@7152 | 1233 | void multiply_128_x_128_bmi2_loop(Register y, Register z, |
kvn@7152 | 1234 | Register carry, Register carry2, |
kvn@7152 | 1235 | Register idx, Register jdx, |
kvn@7152 | 1236 | Register yz_idx1, Register yz_idx2, |
kvn@7152 | 1237 | Register tmp, Register tmp3, Register tmp4); |
kvn@7152 | 1238 | void multiply_128_x_128_loop(Register x_xstart, Register y, Register z, |
kvn@7152 | 1239 | Register yz_idx, Register idx, Register jdx, |
kvn@7152 | 1240 | Register carry, Register product, |
kvn@7152 | 1241 | Register carry2); |
kvn@7152 | 1242 | void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, |
kvn@7152 | 1243 | Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5); |
kvn@7152 | 1244 | #endif |
kvn@7152 | 1245 | |
drchase@5353 | 1246 | // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. |
drchase@5353 | 1247 | void update_byte_crc32(Register crc, Register val, Register table); |
drchase@5353 | 1248 | void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp); |
drchase@5353 | 1249 | // Fold 128-bit data chunk |
drchase@5353 | 1250 | void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset); |
drchase@5353 | 1251 | void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf); |
drchase@5353 | 1252 | // Fold 8-bit data |
drchase@5353 | 1253 | void fold_8bit_crc32(Register crc, Register table, Register tmp); |
drchase@5353 | 1254 | void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp); |
drchase@5353 | 1255 | |
twisti@4318 | 1256 | #undef VIRTUAL |
twisti@4318 | 1257 | |
twisti@4318 | 1258 | }; |
twisti@4318 | 1259 | |
twisti@4318 | 1260 | /** |
twisti@4318 | 1261 | * class SkipIfEqual: |
twisti@4318 | 1262 | * |
twisti@4318 | 1263 | * Instantiating this class will result in assembly code being output that will |
twisti@4318 | 1264 | * jump around any code emitted between the creation of the instance and it's |
twisti@4318 | 1265 | * automatic destruction at the end of a scope block, depending on the value of |
twisti@4318 | 1266 | * the flag passed to the constructor, which will be checked at run-time. |
twisti@4318 | 1267 | */ |
twisti@4318 | 1268 | class SkipIfEqual { |
twisti@4318 | 1269 | private: |
twisti@4318 | 1270 | MacroAssembler* _masm; |
twisti@4318 | 1271 | Label _label; |
twisti@4318 | 1272 | |
twisti@4318 | 1273 | public: |
twisti@4318 | 1274 | SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); |
twisti@4318 | 1275 | ~SkipIfEqual(); |
twisti@4318 | 1276 | }; |
twisti@4318 | 1277 | |
twisti@4318 | 1278 | #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP |