Wed, 15 May 2013 11:05:09 +0200
6843347: Boundary values in some public GC options cause crashes
Summary: Setting some public integer options to specific values causes crashes or undefined GC behavior. This patchset adds the necessary argument checking for these options.
Reviewed-by: jmasa, brutisso
twisti@4323 | 1 | /* |
twisti@4323 | 2 | * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
twisti@4323 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
twisti@4323 | 4 | * |
twisti@4323 | 5 | * This code is free software; you can redistribute it and/or modify it |
twisti@4323 | 6 | * under the terms of the GNU General Public License version 2 only, as |
twisti@4323 | 7 | * published by the Free Software Foundation. |
twisti@4323 | 8 | * |
twisti@4323 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
twisti@4323 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
twisti@4323 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
twisti@4323 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
twisti@4323 | 13 | * accompanied this code). |
twisti@4323 | 14 | * |
twisti@4323 | 15 | * You should have received a copy of the GNU General Public License version |
twisti@4323 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
twisti@4323 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
twisti@4323 | 18 | * |
twisti@4323 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
twisti@4323 | 20 | * or visit www.oracle.com if you need additional information or have any |
twisti@4323 | 21 | * questions. |
twisti@4323 | 22 | * |
twisti@4323 | 23 | */ |
twisti@4323 | 24 | |
twisti@4323 | 25 | #include "precompiled.hpp" |
twisti@4323 | 26 | #include "asm/assembler.inline.hpp" |
twisti@4323 | 27 | #include "compiler/disassembler.hpp" |
twisti@4323 | 28 | #include "gc_interface/collectedHeap.inline.hpp" |
twisti@4323 | 29 | #include "interpreter/interpreter.hpp" |
twisti@4323 | 30 | #include "memory/cardTableModRefBS.hpp" |
twisti@4323 | 31 | #include "memory/resourceArea.hpp" |
twisti@4323 | 32 | #include "prims/methodHandles.hpp" |
twisti@4323 | 33 | #include "runtime/biasedLocking.hpp" |
twisti@4323 | 34 | #include "runtime/interfaceSupport.hpp" |
twisti@4323 | 35 | #include "runtime/objectMonitor.hpp" |
twisti@4323 | 36 | #include "runtime/os.hpp" |
twisti@4323 | 37 | #include "runtime/sharedRuntime.hpp" |
twisti@4323 | 38 | #include "runtime/stubRoutines.hpp" |
jprovino@4542 | 39 | #include "utilities/macros.hpp" |
jprovino@4542 | 40 | #if INCLUDE_ALL_GCS |
twisti@4323 | 41 | #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" |
twisti@4323 | 42 | #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" |
twisti@4323 | 43 | #include "gc_implementation/g1/heapRegion.hpp" |
jprovino@4542 | 44 | #endif // INCLUDE_ALL_GCS |
twisti@4323 | 45 | |
twisti@4323 | 46 | #ifdef PRODUCT |
twisti@4323 | 47 | #define BLOCK_COMMENT(str) /* nothing */ |
twisti@4323 | 48 | #define STOP(error) stop(error) |
twisti@4323 | 49 | #else |
twisti@4323 | 50 | #define BLOCK_COMMENT(str) block_comment(str) |
twisti@4323 | 51 | #define STOP(error) block_comment(error); stop(error) |
twisti@4323 | 52 | #endif |
twisti@4323 | 53 | |
twisti@4323 | 54 | // Convert the raw encoding form into the form expected by the |
twisti@4323 | 55 | // constructor for Address. |
twisti@4323 | 56 | Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { |
twisti@4323 | 57 | assert(scale == 0, "not supported"); |
twisti@4323 | 58 | RelocationHolder rspec; |
twisti@4323 | 59 | if (disp_reloc != relocInfo::none) { |
twisti@4323 | 60 | rspec = Relocation::spec_simple(disp_reloc); |
twisti@4323 | 61 | } |
twisti@4323 | 62 | |
twisti@4323 | 63 | Register rindex = as_Register(index); |
twisti@4323 | 64 | if (rindex != G0) { |
twisti@4323 | 65 | Address madr(as_Register(base), rindex); |
twisti@4323 | 66 | madr._rspec = rspec; |
twisti@4323 | 67 | return madr; |
twisti@4323 | 68 | } else { |
twisti@4323 | 69 | Address madr(as_Register(base), disp); |
twisti@4323 | 70 | madr._rspec = rspec; |
twisti@4323 | 71 | return madr; |
twisti@4323 | 72 | } |
twisti@4323 | 73 | } |
twisti@4323 | 74 | |
twisti@4323 | 75 | Address Argument::address_in_frame() const { |
twisti@4323 | 76 | // Warning: In LP64 mode disp will occupy more than 10 bits, but |
twisti@4323 | 77 | // op codes such as ld or ldx, only access disp() to get |
twisti@4323 | 78 | // their simm13 argument. |
twisti@4323 | 79 | int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; |
twisti@4323 | 80 | if (is_in()) |
twisti@4323 | 81 | return Address(FP, disp); // In argument. |
twisti@4323 | 82 | else |
twisti@4323 | 83 | return Address(SP, disp); // Out argument. |
twisti@4323 | 84 | } |
twisti@4323 | 85 | |
twisti@4323 | 86 | static const char* argumentNames[][2] = { |
twisti@4323 | 87 | {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, |
twisti@4323 | 88 | {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, |
twisti@4323 | 89 | {"A(n>9)","P(n>9)"} |
twisti@4323 | 90 | }; |
twisti@4323 | 91 | |
twisti@4323 | 92 | const char* Argument::name() const { |
twisti@4323 | 93 | int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; |
twisti@4323 | 94 | int num = number(); |
twisti@4323 | 95 | if (num >= nofArgs) num = nofArgs - 1; |
twisti@4323 | 96 | return argumentNames[num][is_in() ? 1 : 0]; |
twisti@4323 | 97 | } |
twisti@4323 | 98 | |
twisti@4323 | 99 | #ifdef ASSERT |
twisti@4323 | 100 | // On RISC, there's no benefit to verifying instruction boundaries. |
twisti@4323 | 101 | bool AbstractAssembler::pd_check_instruction_mark() { return false; } |
twisti@4323 | 102 | #endif |
twisti@4323 | 103 | |
twisti@4323 | 104 | // Patch instruction inst at offset inst_pos to refer to dest_pos |
twisti@4323 | 105 | // and return the resulting instruction. |
twisti@4323 | 106 | // We should have pcs, not offsets, but since all is relative, it will work out |
twisti@4323 | 107 | // OK. |
twisti@4323 | 108 | int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) { |
twisti@4323 | 109 | int m; // mask for displacement field |
twisti@4323 | 110 | int v; // new value for displacement field |
twisti@4323 | 111 | const int word_aligned_ones = -4; |
twisti@4323 | 112 | switch (inv_op(inst)) { |
twisti@4323 | 113 | default: ShouldNotReachHere(); |
twisti@4323 | 114 | case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; |
twisti@4323 | 115 | case branch_op: |
twisti@4323 | 116 | switch (inv_op2(inst)) { |
twisti@4323 | 117 | case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; |
twisti@4323 | 118 | case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; |
twisti@4323 | 119 | case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; |
twisti@4323 | 120 | case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; |
twisti@4323 | 121 | case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; |
twisti@4323 | 122 | case bpr_op2: { |
twisti@4323 | 123 | if (is_cbcond(inst)) { |
twisti@4323 | 124 | m = wdisp10(word_aligned_ones, 0); |
twisti@4323 | 125 | v = wdisp10(dest_pos, inst_pos); |
twisti@4323 | 126 | } else { |
twisti@4323 | 127 | m = wdisp16(word_aligned_ones, 0); |
twisti@4323 | 128 | v = wdisp16(dest_pos, inst_pos); |
twisti@4323 | 129 | } |
twisti@4323 | 130 | break; |
twisti@4323 | 131 | } |
twisti@4323 | 132 | default: ShouldNotReachHere(); |
twisti@4323 | 133 | } |
twisti@4323 | 134 | } |
twisti@4323 | 135 | return inst & ~m | v; |
twisti@4323 | 136 | } |
twisti@4323 | 137 | |
twisti@4323 | 138 | // Return the offset of the branch destionation of instruction inst |
twisti@4323 | 139 | // at offset pos. |
twisti@4323 | 140 | // Should have pcs, but since all is relative, it works out. |
twisti@4323 | 141 | int MacroAssembler::branch_destination(int inst, int pos) { |
twisti@4323 | 142 | int r; |
twisti@4323 | 143 | switch (inv_op(inst)) { |
twisti@4323 | 144 | default: ShouldNotReachHere(); |
twisti@4323 | 145 | case call_op: r = inv_wdisp(inst, pos, 30); break; |
twisti@4323 | 146 | case branch_op: |
twisti@4323 | 147 | switch (inv_op2(inst)) { |
twisti@4323 | 148 | case fbp_op2: r = inv_wdisp( inst, pos, 19); break; |
twisti@4323 | 149 | case bp_op2: r = inv_wdisp( inst, pos, 19); break; |
twisti@4323 | 150 | case fb_op2: r = inv_wdisp( inst, pos, 22); break; |
twisti@4323 | 151 | case br_op2: r = inv_wdisp( inst, pos, 22); break; |
twisti@4323 | 152 | case cb_op2: r = inv_wdisp( inst, pos, 22); break; |
twisti@4323 | 153 | case bpr_op2: { |
twisti@4323 | 154 | if (is_cbcond(inst)) { |
twisti@4323 | 155 | r = inv_wdisp10(inst, pos); |
twisti@4323 | 156 | } else { |
twisti@4323 | 157 | r = inv_wdisp16(inst, pos); |
twisti@4323 | 158 | } |
twisti@4323 | 159 | break; |
twisti@4323 | 160 | } |
twisti@4323 | 161 | default: ShouldNotReachHere(); |
twisti@4323 | 162 | } |
twisti@4323 | 163 | } |
twisti@4323 | 164 | return r; |
twisti@4323 | 165 | } |
twisti@4323 | 166 | |
twisti@4323 | 167 | void MacroAssembler::null_check(Register reg, int offset) { |
twisti@4323 | 168 | if (needs_explicit_null_check((intptr_t)offset)) { |
twisti@4323 | 169 | // provoke OS NULL exception if reg = NULL by |
twisti@4323 | 170 | // accessing M[reg] w/o changing any registers |
twisti@4323 | 171 | ld_ptr(reg, 0, G0); |
twisti@4323 | 172 | } |
twisti@4323 | 173 | else { |
twisti@4323 | 174 | // nothing to do, (later) access of M[reg + offset] |
twisti@4323 | 175 | // will provoke OS NULL exception if reg = NULL |
twisti@4323 | 176 | } |
twisti@4323 | 177 | } |
twisti@4323 | 178 | |
twisti@4323 | 179 | // Ring buffer jumps |
twisti@4323 | 180 | |
twisti@4323 | 181 | #ifndef PRODUCT |
twisti@4323 | 182 | void MacroAssembler::ret( bool trace ) { if (trace) { |
twisti@4323 | 183 | mov(I7, O7); // traceable register |
twisti@4323 | 184 | JMP(O7, 2 * BytesPerInstWord); |
twisti@4323 | 185 | } else { |
twisti@4323 | 186 | jmpl( I7, 2 * BytesPerInstWord, G0 ); |
twisti@4323 | 187 | } |
twisti@4323 | 188 | } |
twisti@4323 | 189 | |
twisti@4323 | 190 | void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord); |
twisti@4323 | 191 | else jmpl( O7, 2 * BytesPerInstWord, G0 ); } |
twisti@4323 | 192 | #endif /* PRODUCT */ |
twisti@4323 | 193 | |
twisti@4323 | 194 | |
twisti@4323 | 195 | void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { |
twisti@4323 | 196 | assert_not_delayed(); |
twisti@4323 | 197 | // This can only be traceable if r1 & r2 are visible after a window save |
twisti@4323 | 198 | if (TraceJumps) { |
twisti@4323 | 199 | #ifndef PRODUCT |
twisti@4323 | 200 | save_frame(0); |
twisti@4323 | 201 | verify_thread(); |
twisti@4323 | 202 | ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); |
twisti@4323 | 203 | add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); |
twisti@4323 | 204 | sll(O0, exact_log2(4*sizeof(intptr_t)), O2); |
twisti@4323 | 205 | add(O2, O1, O1); |
twisti@4323 | 206 | |
twisti@4323 | 207 | add(r1->after_save(), r2->after_save(), O2); |
twisti@4323 | 208 | set((intptr_t)file, O3); |
twisti@4323 | 209 | set(line, O4); |
twisti@4323 | 210 | Label L; |
twisti@4323 | 211 | // get nearby pc, store jmp target |
twisti@4323 | 212 | call(L, relocInfo::none); // No relocation for call to pc+0x8 |
twisti@4323 | 213 | delayed()->st(O2, O1, 0); |
twisti@4323 | 214 | bind(L); |
twisti@4323 | 215 | |
twisti@4323 | 216 | // store nearby pc |
twisti@4323 | 217 | st(O7, O1, sizeof(intptr_t)); |
twisti@4323 | 218 | // store file |
twisti@4323 | 219 | st(O3, O1, 2*sizeof(intptr_t)); |
twisti@4323 | 220 | // store line |
twisti@4323 | 221 | st(O4, O1, 3*sizeof(intptr_t)); |
twisti@4323 | 222 | add(O0, 1, O0); |
twisti@4323 | 223 | and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); |
twisti@4323 | 224 | st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); |
twisti@4323 | 225 | restore(); |
twisti@4323 | 226 | #endif /* PRODUCT */ |
twisti@4323 | 227 | } |
twisti@4323 | 228 | jmpl(r1, r2, G0); |
twisti@4323 | 229 | } |
twisti@4323 | 230 | void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { |
twisti@4323 | 231 | assert_not_delayed(); |
twisti@4323 | 232 | // This can only be traceable if r1 is visible after a window save |
twisti@4323 | 233 | if (TraceJumps) { |
twisti@4323 | 234 | #ifndef PRODUCT |
twisti@4323 | 235 | save_frame(0); |
twisti@4323 | 236 | verify_thread(); |
twisti@4323 | 237 | ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); |
twisti@4323 | 238 | add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); |
twisti@4323 | 239 | sll(O0, exact_log2(4*sizeof(intptr_t)), O2); |
twisti@4323 | 240 | add(O2, O1, O1); |
twisti@4323 | 241 | |
twisti@4323 | 242 | add(r1->after_save(), offset, O2); |
twisti@4323 | 243 | set((intptr_t)file, O3); |
twisti@4323 | 244 | set(line, O4); |
twisti@4323 | 245 | Label L; |
twisti@4323 | 246 | // get nearby pc, store jmp target |
twisti@4323 | 247 | call(L, relocInfo::none); // No relocation for call to pc+0x8 |
twisti@4323 | 248 | delayed()->st(O2, O1, 0); |
twisti@4323 | 249 | bind(L); |
twisti@4323 | 250 | |
twisti@4323 | 251 | // store nearby pc |
twisti@4323 | 252 | st(O7, O1, sizeof(intptr_t)); |
twisti@4323 | 253 | // store file |
twisti@4323 | 254 | st(O3, O1, 2*sizeof(intptr_t)); |
twisti@4323 | 255 | // store line |
twisti@4323 | 256 | st(O4, O1, 3*sizeof(intptr_t)); |
twisti@4323 | 257 | add(O0, 1, O0); |
twisti@4323 | 258 | and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); |
twisti@4323 | 259 | st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); |
twisti@4323 | 260 | restore(); |
twisti@4323 | 261 | #endif /* PRODUCT */ |
twisti@4323 | 262 | } |
twisti@4323 | 263 | jmp(r1, offset); |
twisti@4323 | 264 | } |
twisti@4323 | 265 | |
twisti@4323 | 266 | // This code sequence is relocatable to any address, even on LP64. |
twisti@4323 | 267 | void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) { |
twisti@4323 | 268 | assert_not_delayed(); |
twisti@4323 | 269 | // Force fixed length sethi because NativeJump and NativeFarCall don't handle |
twisti@4323 | 270 | // variable length instruction streams. |
twisti@4323 | 271 | patchable_sethi(addrlit, temp); |
twisti@4323 | 272 | Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement. |
twisti@4323 | 273 | if (TraceJumps) { |
twisti@4323 | 274 | #ifndef PRODUCT |
twisti@4323 | 275 | // Must do the add here so relocation can find the remainder of the |
twisti@4323 | 276 | // value to be relocated. |
twisti@4323 | 277 | add(a.base(), a.disp(), a.base(), addrlit.rspec(offset)); |
twisti@4323 | 278 | save_frame(0); |
twisti@4323 | 279 | verify_thread(); |
twisti@4323 | 280 | ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); |
twisti@4323 | 281 | add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); |
twisti@4323 | 282 | sll(O0, exact_log2(4*sizeof(intptr_t)), O2); |
twisti@4323 | 283 | add(O2, O1, O1); |
twisti@4323 | 284 | |
twisti@4323 | 285 | set((intptr_t)file, O3); |
twisti@4323 | 286 | set(line, O4); |
twisti@4323 | 287 | Label L; |
twisti@4323 | 288 | |
twisti@4323 | 289 | // get nearby pc, store jmp target |
twisti@4323 | 290 | call(L, relocInfo::none); // No relocation for call to pc+0x8 |
twisti@4323 | 291 | delayed()->st(a.base()->after_save(), O1, 0); |
twisti@4323 | 292 | bind(L); |
twisti@4323 | 293 | |
twisti@4323 | 294 | // store nearby pc |
twisti@4323 | 295 | st(O7, O1, sizeof(intptr_t)); |
twisti@4323 | 296 | // store file |
twisti@4323 | 297 | st(O3, O1, 2*sizeof(intptr_t)); |
twisti@4323 | 298 | // store line |
twisti@4323 | 299 | st(O4, O1, 3*sizeof(intptr_t)); |
twisti@4323 | 300 | add(O0, 1, O0); |
twisti@4323 | 301 | and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); |
twisti@4323 | 302 | st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); |
twisti@4323 | 303 | restore(); |
twisti@4323 | 304 | jmpl(a.base(), G0, d); |
twisti@4323 | 305 | #else |
twisti@4323 | 306 | jmpl(a.base(), a.disp(), d); |
twisti@4323 | 307 | #endif /* PRODUCT */ |
twisti@4323 | 308 | } else { |
twisti@4323 | 309 | jmpl(a.base(), a.disp(), d); |
twisti@4323 | 310 | } |
twisti@4323 | 311 | } |
twisti@4323 | 312 | |
twisti@4323 | 313 | void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) { |
twisti@4323 | 314 | jumpl(addrlit, temp, G0, offset, file, line); |
twisti@4323 | 315 | } |
twisti@4323 | 316 | |
twisti@4323 | 317 | |
twisti@4323 | 318 | // Conditional breakpoint (for assertion checks in assembly code) |
twisti@4323 | 319 | void MacroAssembler::breakpoint_trap(Condition c, CC cc) { |
twisti@4323 | 320 | trap(c, cc, G0, ST_RESERVED_FOR_USER_0); |
twisti@4323 | 321 | } |
twisti@4323 | 322 | |
twisti@4323 | 323 | // We want to use ST_BREAKPOINT here, but the debugger is confused by it. |
twisti@4323 | 324 | void MacroAssembler::breakpoint_trap() { |
twisti@4323 | 325 | trap(ST_RESERVED_FOR_USER_0); |
twisti@4323 | 326 | } |
twisti@4323 | 327 | |
twisti@4323 | 328 | // flush windows (except current) using flushw instruction if avail. |
twisti@4323 | 329 | void MacroAssembler::flush_windows() { |
twisti@4323 | 330 | if (VM_Version::v9_instructions_work()) flushw(); |
twisti@4323 | 331 | else flush_windows_trap(); |
twisti@4323 | 332 | } |
twisti@4323 | 333 | |
twisti@4323 | 334 | // Write serialization page so VM thread can do a pseudo remote membar |
twisti@4323 | 335 | // We use the current thread pointer to calculate a thread specific |
twisti@4323 | 336 | // offset to write to within the page. This minimizes bus traffic |
twisti@4323 | 337 | // due to cache line collision. |
twisti@4323 | 338 | void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { |
twisti@4323 | 339 | srl(thread, os::get_serialize_page_shift_count(), tmp2); |
twisti@4323 | 340 | if (Assembler::is_simm13(os::vm_page_size())) { |
twisti@4323 | 341 | and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); |
twisti@4323 | 342 | } |
twisti@4323 | 343 | else { |
twisti@4323 | 344 | set((os::vm_page_size() - sizeof(int)), tmp1); |
twisti@4323 | 345 | and3(tmp2, tmp1, tmp2); |
twisti@4323 | 346 | } |
twisti@4323 | 347 | set(os::get_memory_serialize_page(), tmp1); |
twisti@4323 | 348 | st(G0, tmp1, tmp2); |
twisti@4323 | 349 | } |
twisti@4323 | 350 | |
twisti@4323 | 351 | |
twisti@4323 | 352 | |
twisti@4323 | 353 | void MacroAssembler::enter() { |
twisti@4323 | 354 | Unimplemented(); |
twisti@4323 | 355 | } |
twisti@4323 | 356 | |
twisti@4323 | 357 | void MacroAssembler::leave() { |
twisti@4323 | 358 | Unimplemented(); |
twisti@4323 | 359 | } |
twisti@4323 | 360 | |
twisti@4323 | 361 | void MacroAssembler::mult(Register s1, Register s2, Register d) { |
twisti@4323 | 362 | if(VM_Version::v9_instructions_work()) { |
twisti@4323 | 363 | mulx (s1, s2, d); |
twisti@4323 | 364 | } else { |
twisti@4323 | 365 | smul (s1, s2, d); |
twisti@4323 | 366 | } |
twisti@4323 | 367 | } |
twisti@4323 | 368 | |
twisti@4323 | 369 | void MacroAssembler::mult(Register s1, int simm13a, Register d) { |
twisti@4323 | 370 | if(VM_Version::v9_instructions_work()) { |
twisti@4323 | 371 | mulx (s1, simm13a, d); |
twisti@4323 | 372 | } else { |
twisti@4323 | 373 | smul (s1, simm13a, d); |
twisti@4323 | 374 | } |
twisti@4323 | 375 | } |
twisti@4323 | 376 | |
twisti@4323 | 377 | |
twisti@4323 | 378 | #ifdef ASSERT |
twisti@4323 | 379 | void MacroAssembler::read_ccr_v8_assert(Register ccr_save) { |
twisti@4323 | 380 | const Register s1 = G3_scratch; |
twisti@4323 | 381 | const Register s2 = G4_scratch; |
twisti@4323 | 382 | Label get_psr_test; |
twisti@4323 | 383 | // Get the condition codes the V8 way. |
twisti@4323 | 384 | read_ccr_trap(s1); |
twisti@4323 | 385 | mov(ccr_save, s2); |
twisti@4323 | 386 | // This is a test of V8 which has icc but not xcc |
twisti@4323 | 387 | // so mask off the xcc bits |
twisti@4323 | 388 | and3(s2, 0xf, s2); |
twisti@4323 | 389 | // Compare condition codes from the V8 and V9 ways. |
twisti@4323 | 390 | subcc(s2, s1, G0); |
twisti@4323 | 391 | br(Assembler::notEqual, true, Assembler::pt, get_psr_test); |
twisti@4323 | 392 | delayed()->breakpoint_trap(); |
twisti@4323 | 393 | bind(get_psr_test); |
twisti@4323 | 394 | } |
twisti@4323 | 395 | |
twisti@4323 | 396 | void MacroAssembler::write_ccr_v8_assert(Register ccr_save) { |
twisti@4323 | 397 | const Register s1 = G3_scratch; |
twisti@4323 | 398 | const Register s2 = G4_scratch; |
twisti@4323 | 399 | Label set_psr_test; |
twisti@4323 | 400 | // Write out the saved condition codes the V8 way |
twisti@4323 | 401 | write_ccr_trap(ccr_save, s1, s2); |
twisti@4323 | 402 | // Read back the condition codes using the V9 instruction |
twisti@4323 | 403 | rdccr(s1); |
twisti@4323 | 404 | mov(ccr_save, s2); |
twisti@4323 | 405 | // This is a test of V8 which has icc but not xcc |
twisti@4323 | 406 | // so mask off the xcc bits |
twisti@4323 | 407 | and3(s2, 0xf, s2); |
twisti@4323 | 408 | and3(s1, 0xf, s1); |
twisti@4323 | 409 | // Compare the V8 way with the V9 way. |
twisti@4323 | 410 | subcc(s2, s1, G0); |
twisti@4323 | 411 | br(Assembler::notEqual, true, Assembler::pt, set_psr_test); |
twisti@4323 | 412 | delayed()->breakpoint_trap(); |
twisti@4323 | 413 | bind(set_psr_test); |
twisti@4323 | 414 | } |
twisti@4323 | 415 | #else |
twisti@4323 | 416 | #define read_ccr_v8_assert(x) |
twisti@4323 | 417 | #define write_ccr_v8_assert(x) |
twisti@4323 | 418 | #endif // ASSERT |
twisti@4323 | 419 | |
twisti@4323 | 420 | void MacroAssembler::read_ccr(Register ccr_save) { |
twisti@4323 | 421 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 422 | rdccr(ccr_save); |
twisti@4323 | 423 | // Test code sequence used on V8. Do not move above rdccr. |
twisti@4323 | 424 | read_ccr_v8_assert(ccr_save); |
twisti@4323 | 425 | } else { |
twisti@4323 | 426 | read_ccr_trap(ccr_save); |
twisti@4323 | 427 | } |
twisti@4323 | 428 | } |
twisti@4323 | 429 | |
twisti@4323 | 430 | void MacroAssembler::write_ccr(Register ccr_save) { |
twisti@4323 | 431 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 432 | // Test code sequence used on V8. Do not move below wrccr. |
twisti@4323 | 433 | write_ccr_v8_assert(ccr_save); |
twisti@4323 | 434 | wrccr(ccr_save); |
twisti@4323 | 435 | } else { |
twisti@4323 | 436 | const Register temp_reg1 = G3_scratch; |
twisti@4323 | 437 | const Register temp_reg2 = G4_scratch; |
twisti@4323 | 438 | write_ccr_trap(ccr_save, temp_reg1, temp_reg2); |
twisti@4323 | 439 | } |
twisti@4323 | 440 | } |
twisti@4323 | 441 | |
twisti@4323 | 442 | |
twisti@4323 | 443 | // Calls to C land |
twisti@4323 | 444 | |
twisti@4323 | 445 | #ifdef ASSERT |
twisti@4323 | 446 | // a hook for debugging |
twisti@4323 | 447 | static Thread* reinitialize_thread() { |
twisti@4323 | 448 | return ThreadLocalStorage::thread(); |
twisti@4323 | 449 | } |
twisti@4323 | 450 | #else |
twisti@4323 | 451 | #define reinitialize_thread ThreadLocalStorage::thread |
twisti@4323 | 452 | #endif |
twisti@4323 | 453 | |
twisti@4323 | 454 | #ifdef ASSERT |
twisti@4323 | 455 | address last_get_thread = NULL; |
twisti@4323 | 456 | #endif |
twisti@4323 | 457 | |
twisti@4323 | 458 | // call this when G2_thread is not known to be valid |
twisti@4323 | 459 | void MacroAssembler::get_thread() { |
twisti@4323 | 460 | save_frame(0); // to avoid clobbering O0 |
twisti@4323 | 461 | mov(G1, L0); // avoid clobbering G1 |
twisti@4323 | 462 | mov(G5_method, L1); // avoid clobbering G5 |
twisti@4323 | 463 | mov(G3, L2); // avoid clobbering G3 also |
twisti@4323 | 464 | mov(G4, L5); // avoid clobbering G4 |
twisti@4323 | 465 | #ifdef ASSERT |
twisti@4323 | 466 | AddressLiteral last_get_thread_addrlit(&last_get_thread); |
twisti@4323 | 467 | set(last_get_thread_addrlit, L3); |
twisti@4323 | 468 | inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call |
twisti@4323 | 469 | st_ptr(L4, L3, 0); |
twisti@4323 | 470 | #endif |
twisti@4323 | 471 | call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); |
twisti@4323 | 472 | delayed()->nop(); |
twisti@4323 | 473 | mov(L0, G1); |
twisti@4323 | 474 | mov(L1, G5_method); |
twisti@4323 | 475 | mov(L2, G3); |
twisti@4323 | 476 | mov(L5, G4); |
twisti@4323 | 477 | restore(O0, 0, G2_thread); |
twisti@4323 | 478 | } |
twisti@4323 | 479 | |
twisti@4323 | 480 | static Thread* verify_thread_subroutine(Thread* gthread_value) { |
twisti@4323 | 481 | Thread* correct_value = ThreadLocalStorage::thread(); |
twisti@4323 | 482 | guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); |
twisti@4323 | 483 | return correct_value; |
twisti@4323 | 484 | } |
twisti@4323 | 485 | |
twisti@4323 | 486 | void MacroAssembler::verify_thread() { |
twisti@4323 | 487 | if (VerifyThread) { |
twisti@4323 | 488 | // NOTE: this chops off the heads of the 64-bit O registers. |
twisti@4323 | 489 | #ifdef CC_INTERP |
twisti@4323 | 490 | save_frame(0); |
twisti@4323 | 491 | #else |
twisti@4323 | 492 | // make sure G2_thread contains the right value |
twisti@4323 | 493 | save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) |
twisti@4323 | 494 | mov(G1, L1); // avoid clobbering G1 |
twisti@4323 | 495 | // G2 saved below |
twisti@4323 | 496 | mov(G3, L3); // avoid clobbering G3 |
twisti@4323 | 497 | mov(G4, L4); // avoid clobbering G4 |
twisti@4323 | 498 | mov(G5_method, L5); // avoid clobbering G5_method |
twisti@4323 | 499 | #endif /* CC_INTERP */ |
twisti@4323 | 500 | #if defined(COMPILER2) && !defined(_LP64) |
twisti@4323 | 501 | // Save & restore possible 64-bit Long arguments in G-regs |
twisti@4323 | 502 | srlx(G1,32,L0); |
twisti@4323 | 503 | srlx(G4,32,L6); |
twisti@4323 | 504 | #endif |
twisti@4323 | 505 | call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); |
twisti@4323 | 506 | delayed()->mov(G2_thread, O0); |
twisti@4323 | 507 | |
twisti@4323 | 508 | mov(L1, G1); // Restore G1 |
twisti@4323 | 509 | // G2 restored below |
twisti@4323 | 510 | mov(L3, G3); // restore G3 |
twisti@4323 | 511 | mov(L4, G4); // restore G4 |
twisti@4323 | 512 | mov(L5, G5_method); // restore G5_method |
twisti@4323 | 513 | #if defined(COMPILER2) && !defined(_LP64) |
twisti@4323 | 514 | // Save & restore possible 64-bit Long arguments in G-regs |
twisti@4323 | 515 | sllx(L0,32,G2); // Move old high G1 bits high in G2 |
twisti@4323 | 516 | srl(G1, 0,G1); // Clear current high G1 bits |
twisti@4323 | 517 | or3 (G1,G2,G1); // Recover 64-bit G1 |
twisti@4323 | 518 | sllx(L6,32,G2); // Move old high G4 bits high in G2 |
twisti@4323 | 519 | srl(G4, 0,G4); // Clear current high G4 bits |
twisti@4323 | 520 | or3 (G4,G2,G4); // Recover 64-bit G4 |
twisti@4323 | 521 | #endif |
twisti@4323 | 522 | restore(O0, 0, G2_thread); |
twisti@4323 | 523 | } |
twisti@4323 | 524 | } |
twisti@4323 | 525 | |
twisti@4323 | 526 | |
twisti@4323 | 527 | void MacroAssembler::save_thread(const Register thread_cache) { |
twisti@4323 | 528 | verify_thread(); |
twisti@4323 | 529 | if (thread_cache->is_valid()) { |
twisti@4323 | 530 | assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); |
twisti@4323 | 531 | mov(G2_thread, thread_cache); |
twisti@4323 | 532 | } |
twisti@4323 | 533 | if (VerifyThread) { |
twisti@4323 | 534 | // smash G2_thread, as if the VM were about to anyway |
twisti@4323 | 535 | set(0x67676767, G2_thread); |
twisti@4323 | 536 | } |
twisti@4323 | 537 | } |
twisti@4323 | 538 | |
twisti@4323 | 539 | |
twisti@4323 | 540 | void MacroAssembler::restore_thread(const Register thread_cache) { |
twisti@4323 | 541 | if (thread_cache->is_valid()) { |
twisti@4323 | 542 | assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); |
twisti@4323 | 543 | mov(thread_cache, G2_thread); |
twisti@4323 | 544 | verify_thread(); |
twisti@4323 | 545 | } else { |
twisti@4323 | 546 | // do it the slow way |
twisti@4323 | 547 | get_thread(); |
twisti@4323 | 548 | } |
twisti@4323 | 549 | } |
twisti@4323 | 550 | |
twisti@4323 | 551 | |
twisti@4323 | 552 | // %%% maybe get rid of [re]set_last_Java_frame |
twisti@4323 | 553 | void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { |
twisti@4323 | 554 | assert_not_delayed(); |
twisti@4323 | 555 | Address flags(G2_thread, JavaThread::frame_anchor_offset() + |
twisti@4323 | 556 | JavaFrameAnchor::flags_offset()); |
twisti@4323 | 557 | Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset()); |
twisti@4323 | 558 | |
twisti@4323 | 559 | // Always set last_Java_pc and flags first because once last_Java_sp is visible |
twisti@4323 | 560 | // has_last_Java_frame is true and users will look at the rest of the fields. |
twisti@4323 | 561 | // (Note: flags should always be zero before we get here so doesn't need to be set.) |
twisti@4323 | 562 | |
twisti@4323 | 563 | #ifdef ASSERT |
twisti@4323 | 564 | // Verify that flags was zeroed on return to Java |
twisti@4323 | 565 | Label PcOk; |
twisti@4323 | 566 | save_frame(0); // to avoid clobbering O0 |
twisti@4323 | 567 | ld_ptr(pc_addr, L0); |
twisti@4323 | 568 | br_null_short(L0, Assembler::pt, PcOk); |
twisti@4323 | 569 | STOP("last_Java_pc not zeroed before leaving Java"); |
twisti@4323 | 570 | bind(PcOk); |
twisti@4323 | 571 | |
twisti@4323 | 572 | // Verify that flags was zeroed on return to Java |
twisti@4323 | 573 | Label FlagsOk; |
twisti@4323 | 574 | ld(flags, L0); |
twisti@4323 | 575 | tst(L0); |
twisti@4323 | 576 | br(Assembler::zero, false, Assembler::pt, FlagsOk); |
twisti@4323 | 577 | delayed() -> restore(); |
twisti@4323 | 578 | STOP("flags not zeroed before leaving Java"); |
twisti@4323 | 579 | bind(FlagsOk); |
twisti@4323 | 580 | #endif /* ASSERT */ |
twisti@4323 | 581 | // |
twisti@4323 | 582 | // When returning from calling out from Java mode the frame anchor's last_Java_pc |
twisti@4323 | 583 | // will always be set to NULL. It is set here so that if we are doing a call to |
twisti@4323 | 584 | // native (not VM) that we capture the known pc and don't have to rely on the |
twisti@4323 | 585 | // native call having a standard frame linkage where we can find the pc. |
twisti@4323 | 586 | |
twisti@4323 | 587 | if (last_Java_pc->is_valid()) { |
twisti@4323 | 588 | st_ptr(last_Java_pc, pc_addr); |
twisti@4323 | 589 | } |
twisti@4323 | 590 | |
twisti@4323 | 591 | #ifdef _LP64 |
twisti@4323 | 592 | #ifdef ASSERT |
twisti@4323 | 593 | // Make sure that we have an odd stack |
twisti@4323 | 594 | Label StackOk; |
twisti@4323 | 595 | andcc(last_java_sp, 0x01, G0); |
twisti@4323 | 596 | br(Assembler::notZero, false, Assembler::pt, StackOk); |
twisti@4323 | 597 | delayed()->nop(); |
twisti@4323 | 598 | STOP("Stack Not Biased in set_last_Java_frame"); |
twisti@4323 | 599 | bind(StackOk); |
twisti@4323 | 600 | #endif // ASSERT |
twisti@4323 | 601 | assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); |
twisti@4323 | 602 | add( last_java_sp, STACK_BIAS, G4_scratch ); |
twisti@4323 | 603 | st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset()); |
twisti@4323 | 604 | #else |
twisti@4323 | 605 | st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset()); |
twisti@4323 | 606 | #endif // _LP64 |
twisti@4323 | 607 | } |
twisti@4323 | 608 | |
twisti@4323 | 609 | void MacroAssembler::reset_last_Java_frame(void) { |
twisti@4323 | 610 | assert_not_delayed(); |
twisti@4323 | 611 | |
twisti@4323 | 612 | Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset()); |
twisti@4323 | 613 | Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); |
twisti@4323 | 614 | Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); |
twisti@4323 | 615 | |
twisti@4323 | 616 | #ifdef ASSERT |
twisti@4323 | 617 | // check that it WAS previously set |
twisti@4323 | 618 | #ifdef CC_INTERP |
twisti@4323 | 619 | save_frame(0); |
twisti@4323 | 620 | #else |
twisti@4323 | 621 | save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof |
twisti@4323 | 622 | #endif /* CC_INTERP */ |
twisti@4323 | 623 | ld_ptr(sp_addr, L0); |
twisti@4323 | 624 | tst(L0); |
twisti@4323 | 625 | breakpoint_trap(Assembler::zero, Assembler::ptr_cc); |
twisti@4323 | 626 | restore(); |
twisti@4323 | 627 | #endif // ASSERT |
twisti@4323 | 628 | |
twisti@4323 | 629 | st_ptr(G0, sp_addr); |
twisti@4323 | 630 | // Always return last_Java_pc to zero |
twisti@4323 | 631 | st_ptr(G0, pc_addr); |
twisti@4323 | 632 | // Always null flags after return to Java |
twisti@4323 | 633 | st(G0, flags); |
twisti@4323 | 634 | } |
twisti@4323 | 635 | |
twisti@4323 | 636 | |
twisti@4323 | 637 | void MacroAssembler::call_VM_base( |
twisti@4323 | 638 | Register oop_result, |
twisti@4323 | 639 | Register thread_cache, |
twisti@4323 | 640 | Register last_java_sp, |
twisti@4323 | 641 | address entry_point, |
twisti@4323 | 642 | int number_of_arguments, |
twisti@4323 | 643 | bool check_exceptions) |
twisti@4323 | 644 | { |
twisti@4323 | 645 | assert_not_delayed(); |
twisti@4323 | 646 | |
twisti@4323 | 647 | // determine last_java_sp register |
twisti@4323 | 648 | if (!last_java_sp->is_valid()) { |
twisti@4323 | 649 | last_java_sp = SP; |
twisti@4323 | 650 | } |
twisti@4323 | 651 | // debugging support |
twisti@4323 | 652 | assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); |
twisti@4323 | 653 | |
twisti@4323 | 654 | // 64-bit last_java_sp is biased! |
twisti@4323 | 655 | set_last_Java_frame(last_java_sp, noreg); |
twisti@4323 | 656 | if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early |
twisti@4323 | 657 | save_thread(thread_cache); |
twisti@4323 | 658 | // do the call |
twisti@4323 | 659 | call(entry_point, relocInfo::runtime_call_type); |
twisti@4323 | 660 | if (!VerifyThread) |
twisti@4323 | 661 | delayed()->mov(G2_thread, O0); // pass thread as first argument |
twisti@4323 | 662 | else |
twisti@4323 | 663 | delayed()->nop(); // (thread already passed) |
twisti@4323 | 664 | restore_thread(thread_cache); |
twisti@4323 | 665 | reset_last_Java_frame(); |
twisti@4323 | 666 | |
twisti@4323 | 667 | // check for pending exceptions. use Gtemp as scratch register. |
twisti@4323 | 668 | if (check_exceptions) { |
twisti@4323 | 669 | check_and_forward_exception(Gtemp); |
twisti@4323 | 670 | } |
twisti@4323 | 671 | |
twisti@4323 | 672 | #ifdef ASSERT |
twisti@4323 | 673 | set(badHeapWordVal, G3); |
twisti@4323 | 674 | set(badHeapWordVal, G4); |
twisti@4323 | 675 | set(badHeapWordVal, G5); |
twisti@4323 | 676 | #endif |
twisti@4323 | 677 | |
twisti@4323 | 678 | // get oop result if there is one and reset the value in the thread |
twisti@4323 | 679 | if (oop_result->is_valid()) { |
twisti@4323 | 680 | get_vm_result(oop_result); |
twisti@4323 | 681 | } |
twisti@4323 | 682 | } |
twisti@4323 | 683 | |
twisti@4323 | 684 | void MacroAssembler::check_and_forward_exception(Register scratch_reg) |
twisti@4323 | 685 | { |
twisti@4323 | 686 | Label L; |
twisti@4323 | 687 | |
twisti@4323 | 688 | check_and_handle_popframe(scratch_reg); |
twisti@4323 | 689 | check_and_handle_earlyret(scratch_reg); |
twisti@4323 | 690 | |
twisti@4323 | 691 | Address exception_addr(G2_thread, Thread::pending_exception_offset()); |
twisti@4323 | 692 | ld_ptr(exception_addr, scratch_reg); |
twisti@4323 | 693 | br_null_short(scratch_reg, pt, L); |
twisti@4323 | 694 | // we use O7 linkage so that forward_exception_entry has the issuing PC |
twisti@4323 | 695 | call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); |
twisti@4323 | 696 | delayed()->nop(); |
twisti@4323 | 697 | bind(L); |
twisti@4323 | 698 | } |
twisti@4323 | 699 | |
twisti@4323 | 700 | |
twisti@4323 | 701 | void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { |
twisti@4323 | 702 | } |
twisti@4323 | 703 | |
twisti@4323 | 704 | |
twisti@4323 | 705 | void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { |
twisti@4323 | 706 | } |
twisti@4323 | 707 | |
twisti@4323 | 708 | |
twisti@4323 | 709 | void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { |
twisti@4323 | 710 | call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); |
twisti@4323 | 711 | } |
twisti@4323 | 712 | |
twisti@4323 | 713 | |
twisti@4323 | 714 | void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { |
twisti@4323 | 715 | // O0 is reserved for the thread |
twisti@4323 | 716 | mov(arg_1, O1); |
twisti@4323 | 717 | call_VM(oop_result, entry_point, 1, check_exceptions); |
twisti@4323 | 718 | } |
twisti@4323 | 719 | |
twisti@4323 | 720 | |
twisti@4323 | 721 | void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { |
twisti@4323 | 722 | // O0 is reserved for the thread |
twisti@4323 | 723 | mov(arg_1, O1); |
twisti@4323 | 724 | mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); |
twisti@4323 | 725 | call_VM(oop_result, entry_point, 2, check_exceptions); |
twisti@4323 | 726 | } |
twisti@4323 | 727 | |
twisti@4323 | 728 | |
twisti@4323 | 729 | void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { |
twisti@4323 | 730 | // O0 is reserved for the thread |
twisti@4323 | 731 | mov(arg_1, O1); |
twisti@4323 | 732 | mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); |
twisti@4323 | 733 | mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); |
twisti@4323 | 734 | call_VM(oop_result, entry_point, 3, check_exceptions); |
twisti@4323 | 735 | } |
twisti@4323 | 736 | |
twisti@4323 | 737 | |
twisti@4323 | 738 | |
twisti@4323 | 739 | // Note: The following call_VM overloadings are useful when a "save" |
twisti@4323 | 740 | // has already been performed by a stub, and the last Java frame is |
twisti@4323 | 741 | // the previous one. In that case, last_java_sp must be passed as FP |
twisti@4323 | 742 | // instead of SP. |
twisti@4323 | 743 | |
twisti@4323 | 744 | |
twisti@4323 | 745 | void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { |
twisti@4323 | 746 | call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); |
twisti@4323 | 747 | } |
twisti@4323 | 748 | |
twisti@4323 | 749 | |
twisti@4323 | 750 | void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { |
twisti@4323 | 751 | // O0 is reserved for the thread |
twisti@4323 | 752 | mov(arg_1, O1); |
twisti@4323 | 753 | call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); |
twisti@4323 | 754 | } |
twisti@4323 | 755 | |
twisti@4323 | 756 | |
twisti@4323 | 757 | void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { |
twisti@4323 | 758 | // O0 is reserved for the thread |
twisti@4323 | 759 | mov(arg_1, O1); |
twisti@4323 | 760 | mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); |
twisti@4323 | 761 | call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); |
twisti@4323 | 762 | } |
twisti@4323 | 763 | |
twisti@4323 | 764 | |
twisti@4323 | 765 | void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { |
twisti@4323 | 766 | // O0 is reserved for the thread |
twisti@4323 | 767 | mov(arg_1, O1); |
twisti@4323 | 768 | mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); |
twisti@4323 | 769 | mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); |
twisti@4323 | 770 | call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); |
twisti@4323 | 771 | } |
twisti@4323 | 772 | |
twisti@4323 | 773 | |
twisti@4323 | 774 | |
twisti@4323 | 775 | void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { |
twisti@4323 | 776 | assert_not_delayed(); |
twisti@4323 | 777 | save_thread(thread_cache); |
twisti@4323 | 778 | // do the call |
twisti@4323 | 779 | call(entry_point, relocInfo::runtime_call_type); |
twisti@4323 | 780 | delayed()->nop(); |
twisti@4323 | 781 | restore_thread(thread_cache); |
twisti@4323 | 782 | #ifdef ASSERT |
twisti@4323 | 783 | set(badHeapWordVal, G3); |
twisti@4323 | 784 | set(badHeapWordVal, G4); |
twisti@4323 | 785 | set(badHeapWordVal, G5); |
twisti@4323 | 786 | #endif |
twisti@4323 | 787 | } |
twisti@4323 | 788 | |
twisti@4323 | 789 | |
twisti@4323 | 790 | void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { |
twisti@4323 | 791 | call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); |
twisti@4323 | 792 | } |
twisti@4323 | 793 | |
twisti@4323 | 794 | |
twisti@4323 | 795 | void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { |
twisti@4323 | 796 | mov(arg_1, O0); |
twisti@4323 | 797 | call_VM_leaf(thread_cache, entry_point, 1); |
twisti@4323 | 798 | } |
twisti@4323 | 799 | |
twisti@4323 | 800 | |
twisti@4323 | 801 | void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { |
twisti@4323 | 802 | mov(arg_1, O0); |
twisti@4323 | 803 | mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); |
twisti@4323 | 804 | call_VM_leaf(thread_cache, entry_point, 2); |
twisti@4323 | 805 | } |
twisti@4323 | 806 | |
twisti@4323 | 807 | |
twisti@4323 | 808 | void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { |
twisti@4323 | 809 | mov(arg_1, O0); |
twisti@4323 | 810 | mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); |
twisti@4323 | 811 | mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); |
twisti@4323 | 812 | call_VM_leaf(thread_cache, entry_point, 3); |
twisti@4323 | 813 | } |
twisti@4323 | 814 | |
twisti@4323 | 815 | |
twisti@4323 | 816 | void MacroAssembler::get_vm_result(Register oop_result) { |
twisti@4323 | 817 | verify_thread(); |
twisti@4323 | 818 | Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); |
twisti@4323 | 819 | ld_ptr( vm_result_addr, oop_result); |
twisti@4323 | 820 | st_ptr(G0, vm_result_addr); |
twisti@4323 | 821 | verify_oop(oop_result); |
twisti@4323 | 822 | } |
twisti@4323 | 823 | |
twisti@4323 | 824 | |
twisti@4323 | 825 | void MacroAssembler::get_vm_result_2(Register metadata_result) { |
twisti@4323 | 826 | verify_thread(); |
twisti@4323 | 827 | Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset()); |
twisti@4323 | 828 | ld_ptr(vm_result_addr_2, metadata_result); |
twisti@4323 | 829 | st_ptr(G0, vm_result_addr_2); |
twisti@4323 | 830 | } |
twisti@4323 | 831 | |
twisti@4323 | 832 | |
twisti@4323 | 833 | // We require that C code which does not return a value in vm_result will |
twisti@4323 | 834 | // leave it undisturbed. |
twisti@4323 | 835 | void MacroAssembler::set_vm_result(Register oop_result) { |
twisti@4323 | 836 | verify_thread(); |
twisti@4323 | 837 | Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); |
twisti@4323 | 838 | verify_oop(oop_result); |
twisti@4323 | 839 | |
twisti@4323 | 840 | # ifdef ASSERT |
twisti@4323 | 841 | // Check that we are not overwriting any other oop. |
twisti@4323 | 842 | #ifdef CC_INTERP |
twisti@4323 | 843 | save_frame(0); |
twisti@4323 | 844 | #else |
twisti@4323 | 845 | save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof |
twisti@4323 | 846 | #endif /* CC_INTERP */ |
twisti@4323 | 847 | ld_ptr(vm_result_addr, L0); |
twisti@4323 | 848 | tst(L0); |
twisti@4323 | 849 | restore(); |
twisti@4323 | 850 | breakpoint_trap(notZero, Assembler::ptr_cc); |
twisti@4323 | 851 | // } |
twisti@4323 | 852 | # endif |
twisti@4323 | 853 | |
twisti@4323 | 854 | st_ptr(oop_result, vm_result_addr); |
twisti@4323 | 855 | } |
twisti@4323 | 856 | |
twisti@4323 | 857 | |
twisti@4323 | 858 | void MacroAssembler::ic_call(address entry, bool emit_delay) { |
twisti@4323 | 859 | RelocationHolder rspec = virtual_call_Relocation::spec(pc()); |
twisti@4323 | 860 | patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg); |
twisti@4323 | 861 | relocate(rspec); |
twisti@4323 | 862 | call(entry, relocInfo::none); |
twisti@4323 | 863 | if (emit_delay) { |
twisti@4323 | 864 | delayed()->nop(); |
twisti@4323 | 865 | } |
twisti@4323 | 866 | } |
twisti@4323 | 867 | |
twisti@4323 | 868 | |
twisti@4323 | 869 | void MacroAssembler::card_table_write(jbyte* byte_map_base, |
twisti@4323 | 870 | Register tmp, Register obj) { |
twisti@4323 | 871 | #ifdef _LP64 |
twisti@4323 | 872 | srlx(obj, CardTableModRefBS::card_shift, obj); |
twisti@4323 | 873 | #else |
twisti@4323 | 874 | srl(obj, CardTableModRefBS::card_shift, obj); |
twisti@4323 | 875 | #endif |
twisti@4323 | 876 | assert(tmp != obj, "need separate temp reg"); |
twisti@4323 | 877 | set((address) byte_map_base, tmp); |
twisti@4323 | 878 | stb(G0, tmp, obj); |
twisti@4323 | 879 | } |
twisti@4323 | 880 | |
twisti@4323 | 881 | |
twisti@4323 | 882 | void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { |
twisti@4323 | 883 | address save_pc; |
twisti@4323 | 884 | int shiftcnt; |
twisti@4323 | 885 | #ifdef _LP64 |
twisti@4323 | 886 | # ifdef CHECK_DELAY |
twisti@4323 | 887 | assert_not_delayed((char*) "cannot put two instructions in delay slot"); |
twisti@4323 | 888 | # endif |
twisti@4323 | 889 | v9_dep(); |
twisti@4323 | 890 | save_pc = pc(); |
twisti@4323 | 891 | |
twisti@4323 | 892 | int msb32 = (int) (addrlit.value() >> 32); |
twisti@4323 | 893 | int lsb32 = (int) (addrlit.value()); |
twisti@4323 | 894 | |
twisti@4323 | 895 | if (msb32 == 0 && lsb32 >= 0) { |
twisti@4323 | 896 | Assembler::sethi(lsb32, d, addrlit.rspec()); |
twisti@4323 | 897 | } |
twisti@4323 | 898 | else if (msb32 == -1) { |
twisti@4323 | 899 | Assembler::sethi(~lsb32, d, addrlit.rspec()); |
twisti@4323 | 900 | xor3(d, ~low10(~0), d); |
twisti@4323 | 901 | } |
twisti@4323 | 902 | else { |
twisti@4323 | 903 | Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits |
twisti@4323 | 904 | if (msb32 & 0x3ff) // Any bits? |
twisti@4323 | 905 | or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32 |
twisti@4323 | 906 | if (lsb32 & 0xFFFFFC00) { // done? |
twisti@4323 | 907 | if ((lsb32 >> 20) & 0xfff) { // Any bits set? |
twisti@4323 | 908 | sllx(d, 12, d); // Make room for next 12 bits |
twisti@4323 | 909 | or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12 |
twisti@4323 | 910 | shiftcnt = 0; // We already shifted |
twisti@4323 | 911 | } |
twisti@4323 | 912 | else |
twisti@4323 | 913 | shiftcnt = 12; |
twisti@4323 | 914 | if ((lsb32 >> 10) & 0x3ff) { |
twisti@4323 | 915 | sllx(d, shiftcnt + 10, d); // Make room for last 10 bits |
twisti@4323 | 916 | or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10 |
twisti@4323 | 917 | shiftcnt = 0; |
twisti@4323 | 918 | } |
twisti@4323 | 919 | else |
twisti@4323 | 920 | shiftcnt = 10; |
twisti@4323 | 921 | sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd |
twisti@4323 | 922 | } |
twisti@4323 | 923 | else |
twisti@4323 | 924 | sllx(d, 32, d); |
twisti@4323 | 925 | } |
twisti@4323 | 926 | // Pad out the instruction sequence so it can be patched later. |
twisti@4323 | 927 | if (ForceRelocatable || (addrlit.rtype() != relocInfo::none && |
twisti@4323 | 928 | addrlit.rtype() != relocInfo::runtime_call_type)) { |
twisti@4323 | 929 | while (pc() < (save_pc + (7 * BytesPerInstWord))) |
twisti@4323 | 930 | nop(); |
twisti@4323 | 931 | } |
twisti@4323 | 932 | #else |
twisti@4323 | 933 | Assembler::sethi(addrlit.value(), d, addrlit.rspec()); |
twisti@4323 | 934 | #endif |
twisti@4323 | 935 | } |
twisti@4323 | 936 | |
twisti@4323 | 937 | |
twisti@4323 | 938 | void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) { |
twisti@4323 | 939 | internal_sethi(addrlit, d, false); |
twisti@4323 | 940 | } |
twisti@4323 | 941 | |
twisti@4323 | 942 | |
twisti@4323 | 943 | void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) { |
twisti@4323 | 944 | internal_sethi(addrlit, d, true); |
twisti@4323 | 945 | } |
twisti@4323 | 946 | |
twisti@4323 | 947 | |
twisti@4323 | 948 | int MacroAssembler::insts_for_sethi(address a, bool worst_case) { |
twisti@4323 | 949 | #ifdef _LP64 |
twisti@4323 | 950 | if (worst_case) return 7; |
twisti@4323 | 951 | intptr_t iaddr = (intptr_t) a; |
twisti@4323 | 952 | int msb32 = (int) (iaddr >> 32); |
twisti@4323 | 953 | int lsb32 = (int) (iaddr); |
twisti@4323 | 954 | int count; |
twisti@4323 | 955 | if (msb32 == 0 && lsb32 >= 0) |
twisti@4323 | 956 | count = 1; |
twisti@4323 | 957 | else if (msb32 == -1) |
twisti@4323 | 958 | count = 2; |
twisti@4323 | 959 | else { |
twisti@4323 | 960 | count = 2; |
twisti@4323 | 961 | if (msb32 & 0x3ff) |
twisti@4323 | 962 | count++; |
twisti@4323 | 963 | if (lsb32 & 0xFFFFFC00 ) { |
twisti@4323 | 964 | if ((lsb32 >> 20) & 0xfff) count += 2; |
twisti@4323 | 965 | if ((lsb32 >> 10) & 0x3ff) count += 2; |
twisti@4323 | 966 | } |
twisti@4323 | 967 | } |
twisti@4323 | 968 | return count; |
twisti@4323 | 969 | #else |
twisti@4323 | 970 | return 1; |
twisti@4323 | 971 | #endif |
twisti@4323 | 972 | } |
twisti@4323 | 973 | |
twisti@4323 | 974 | int MacroAssembler::worst_case_insts_for_set() { |
twisti@4323 | 975 | return insts_for_sethi(NULL, true) + 1; |
twisti@4323 | 976 | } |
twisti@4323 | 977 | |
twisti@4323 | 978 | |
twisti@4323 | 979 | // Keep in sync with MacroAssembler::insts_for_internal_set |
twisti@4323 | 980 | void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { |
twisti@4323 | 981 | intptr_t value = addrlit.value(); |
twisti@4323 | 982 | |
twisti@4323 | 983 | if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) { |
twisti@4323 | 984 | // can optimize |
twisti@4323 | 985 | if (-4096 <= value && value <= 4095) { |
twisti@4323 | 986 | or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) |
twisti@4323 | 987 | return; |
twisti@4323 | 988 | } |
twisti@4323 | 989 | if (inv_hi22(hi22(value)) == value) { |
twisti@4323 | 990 | sethi(addrlit, d); |
twisti@4323 | 991 | return; |
twisti@4323 | 992 | } |
twisti@4323 | 993 | } |
twisti@4323 | 994 | assert_not_delayed((char*) "cannot put two instructions in delay slot"); |
twisti@4323 | 995 | internal_sethi(addrlit, d, ForceRelocatable); |
twisti@4323 | 996 | if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) { |
twisti@4323 | 997 | add(d, addrlit.low10(), d, addrlit.rspec()); |
twisti@4323 | 998 | } |
twisti@4323 | 999 | } |
twisti@4323 | 1000 | |
twisti@4323 | 1001 | // Keep in sync with MacroAssembler::internal_set |
twisti@4323 | 1002 | int MacroAssembler::insts_for_internal_set(intptr_t value) { |
twisti@4323 | 1003 | // can optimize |
twisti@4323 | 1004 | if (-4096 <= value && value <= 4095) { |
twisti@4323 | 1005 | return 1; |
twisti@4323 | 1006 | } |
twisti@4323 | 1007 | if (inv_hi22(hi22(value)) == value) { |
twisti@4323 | 1008 | return insts_for_sethi((address) value); |
twisti@4323 | 1009 | } |
twisti@4323 | 1010 | int count = insts_for_sethi((address) value); |
twisti@4323 | 1011 | AddressLiteral al(value); |
twisti@4323 | 1012 | if (al.low10() != 0) { |
twisti@4323 | 1013 | count++; |
twisti@4323 | 1014 | } |
twisti@4323 | 1015 | return count; |
twisti@4323 | 1016 | } |
twisti@4323 | 1017 | |
twisti@4323 | 1018 | void MacroAssembler::set(const AddressLiteral& al, Register d) { |
twisti@4323 | 1019 | internal_set(al, d, false); |
twisti@4323 | 1020 | } |
twisti@4323 | 1021 | |
twisti@4323 | 1022 | void MacroAssembler::set(intptr_t value, Register d) { |
twisti@4323 | 1023 | AddressLiteral al(value); |
twisti@4323 | 1024 | internal_set(al, d, false); |
twisti@4323 | 1025 | } |
twisti@4323 | 1026 | |
twisti@4323 | 1027 | void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) { |
twisti@4323 | 1028 | AddressLiteral al(addr, rspec); |
twisti@4323 | 1029 | internal_set(al, d, false); |
twisti@4323 | 1030 | } |
twisti@4323 | 1031 | |
twisti@4323 | 1032 | void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) { |
twisti@4323 | 1033 | internal_set(al, d, true); |
twisti@4323 | 1034 | } |
twisti@4323 | 1035 | |
twisti@4323 | 1036 | void MacroAssembler::patchable_set(intptr_t value, Register d) { |
twisti@4323 | 1037 | AddressLiteral al(value); |
twisti@4323 | 1038 | internal_set(al, d, true); |
twisti@4323 | 1039 | } |
twisti@4323 | 1040 | |
twisti@4323 | 1041 | |
twisti@4323 | 1042 | void MacroAssembler::set64(jlong value, Register d, Register tmp) { |
twisti@4323 | 1043 | assert_not_delayed(); |
twisti@4323 | 1044 | v9_dep(); |
twisti@4323 | 1045 | |
twisti@4323 | 1046 | int hi = (int)(value >> 32); |
twisti@4323 | 1047 | int lo = (int)(value & ~0); |
twisti@4323 | 1048 | // (Matcher::isSimpleConstant64 knows about the following optimizations.) |
twisti@4323 | 1049 | if (Assembler::is_simm13(lo) && value == lo) { |
twisti@4323 | 1050 | or3(G0, lo, d); |
twisti@4323 | 1051 | } else if (hi == 0) { |
twisti@4323 | 1052 | Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 |
twisti@4323 | 1053 | if (low10(lo) != 0) |
twisti@4323 | 1054 | or3(d, low10(lo), d); |
twisti@4323 | 1055 | } |
twisti@4323 | 1056 | else if (hi == -1) { |
twisti@4323 | 1057 | Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 |
twisti@4323 | 1058 | xor3(d, low10(lo) ^ ~low10(~0), d); |
twisti@4323 | 1059 | } |
twisti@4323 | 1060 | else if (lo == 0) { |
twisti@4323 | 1061 | if (Assembler::is_simm13(hi)) { |
twisti@4323 | 1062 | or3(G0, hi, d); |
twisti@4323 | 1063 | } else { |
twisti@4323 | 1064 | Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 |
twisti@4323 | 1065 | if (low10(hi) != 0) |
twisti@4323 | 1066 | or3(d, low10(hi), d); |
twisti@4323 | 1067 | } |
twisti@4323 | 1068 | sllx(d, 32, d); |
twisti@4323 | 1069 | } |
twisti@4323 | 1070 | else { |
twisti@4323 | 1071 | Assembler::sethi(hi, tmp); |
twisti@4323 | 1072 | Assembler::sethi(lo, d); // macro assembler version sign-extends |
twisti@4323 | 1073 | if (low10(hi) != 0) |
twisti@4323 | 1074 | or3 (tmp, low10(hi), tmp); |
twisti@4323 | 1075 | if (low10(lo) != 0) |
twisti@4323 | 1076 | or3 ( d, low10(lo), d); |
twisti@4323 | 1077 | sllx(tmp, 32, tmp); |
twisti@4323 | 1078 | or3 (d, tmp, d); |
twisti@4323 | 1079 | } |
twisti@4323 | 1080 | } |
twisti@4323 | 1081 | |
twisti@4323 | 1082 | int MacroAssembler::insts_for_set64(jlong value) { |
twisti@4323 | 1083 | v9_dep(); |
twisti@4323 | 1084 | |
twisti@4323 | 1085 | int hi = (int) (value >> 32); |
twisti@4323 | 1086 | int lo = (int) (value & ~0); |
twisti@4323 | 1087 | int count = 0; |
twisti@4323 | 1088 | |
twisti@4323 | 1089 | // (Matcher::isSimpleConstant64 knows about the following optimizations.) |
twisti@4323 | 1090 | if (Assembler::is_simm13(lo) && value == lo) { |
twisti@4323 | 1091 | count++; |
twisti@4323 | 1092 | } else if (hi == 0) { |
twisti@4323 | 1093 | count++; |
twisti@4323 | 1094 | if (low10(lo) != 0) |
twisti@4323 | 1095 | count++; |
twisti@4323 | 1096 | } |
twisti@4323 | 1097 | else if (hi == -1) { |
twisti@4323 | 1098 | count += 2; |
twisti@4323 | 1099 | } |
twisti@4323 | 1100 | else if (lo == 0) { |
twisti@4323 | 1101 | if (Assembler::is_simm13(hi)) { |
twisti@4323 | 1102 | count++; |
twisti@4323 | 1103 | } else { |
twisti@4323 | 1104 | count++; |
twisti@4323 | 1105 | if (low10(hi) != 0) |
twisti@4323 | 1106 | count++; |
twisti@4323 | 1107 | } |
twisti@4323 | 1108 | count++; |
twisti@4323 | 1109 | } |
twisti@4323 | 1110 | else { |
twisti@4323 | 1111 | count += 2; |
twisti@4323 | 1112 | if (low10(hi) != 0) |
twisti@4323 | 1113 | count++; |
twisti@4323 | 1114 | if (low10(lo) != 0) |
twisti@4323 | 1115 | count++; |
twisti@4323 | 1116 | count += 2; |
twisti@4323 | 1117 | } |
twisti@4323 | 1118 | return count; |
twisti@4323 | 1119 | } |
twisti@4323 | 1120 | |
twisti@4323 | 1121 | // compute size in bytes of sparc frame, given |
twisti@4323 | 1122 | // number of extraWords |
twisti@4323 | 1123 | int MacroAssembler::total_frame_size_in_bytes(int extraWords) { |
twisti@4323 | 1124 | |
twisti@4323 | 1125 | int nWords = frame::memory_parameter_word_sp_offset; |
twisti@4323 | 1126 | |
twisti@4323 | 1127 | nWords += extraWords; |
twisti@4323 | 1128 | |
twisti@4323 | 1129 | if (nWords & 1) ++nWords; // round up to double-word |
twisti@4323 | 1130 | |
twisti@4323 | 1131 | return nWords * BytesPerWord; |
twisti@4323 | 1132 | } |
twisti@4323 | 1133 | |
twisti@4323 | 1134 | |
twisti@4323 | 1135 | // save_frame: given number of "extra" words in frame, |
twisti@4323 | 1136 | // issue approp. save instruction (p 200, v8 manual) |
twisti@4323 | 1137 | |
twisti@4323 | 1138 | void MacroAssembler::save_frame(int extraWords) { |
twisti@4323 | 1139 | int delta = -total_frame_size_in_bytes(extraWords); |
twisti@4323 | 1140 | if (is_simm13(delta)) { |
twisti@4323 | 1141 | save(SP, delta, SP); |
twisti@4323 | 1142 | } else { |
twisti@4323 | 1143 | set(delta, G3_scratch); |
twisti@4323 | 1144 | save(SP, G3_scratch, SP); |
twisti@4323 | 1145 | } |
twisti@4323 | 1146 | } |
twisti@4323 | 1147 | |
twisti@4323 | 1148 | |
twisti@4323 | 1149 | void MacroAssembler::save_frame_c1(int size_in_bytes) { |
twisti@4323 | 1150 | if (is_simm13(-size_in_bytes)) { |
twisti@4323 | 1151 | save(SP, -size_in_bytes, SP); |
twisti@4323 | 1152 | } else { |
twisti@4323 | 1153 | set(-size_in_bytes, G3_scratch); |
twisti@4323 | 1154 | save(SP, G3_scratch, SP); |
twisti@4323 | 1155 | } |
twisti@4323 | 1156 | } |
twisti@4323 | 1157 | |
twisti@4323 | 1158 | |
twisti@4323 | 1159 | void MacroAssembler::save_frame_and_mov(int extraWords, |
twisti@4323 | 1160 | Register s1, Register d1, |
twisti@4323 | 1161 | Register s2, Register d2) { |
twisti@4323 | 1162 | assert_not_delayed(); |
twisti@4323 | 1163 | |
twisti@4323 | 1164 | // The trick here is to use precisely the same memory word |
twisti@4323 | 1165 | // that trap handlers also use to save the register. |
twisti@4323 | 1166 | // This word cannot be used for any other purpose, but |
twisti@4323 | 1167 | // it works fine to save the register's value, whether or not |
twisti@4323 | 1168 | // an interrupt flushes register windows at any given moment! |
twisti@4323 | 1169 | Address s1_addr; |
twisti@4323 | 1170 | if (s1->is_valid() && (s1->is_in() || s1->is_local())) { |
twisti@4323 | 1171 | s1_addr = s1->address_in_saved_window(); |
twisti@4323 | 1172 | st_ptr(s1, s1_addr); |
twisti@4323 | 1173 | } |
twisti@4323 | 1174 | |
twisti@4323 | 1175 | Address s2_addr; |
twisti@4323 | 1176 | if (s2->is_valid() && (s2->is_in() || s2->is_local())) { |
twisti@4323 | 1177 | s2_addr = s2->address_in_saved_window(); |
twisti@4323 | 1178 | st_ptr(s2, s2_addr); |
twisti@4323 | 1179 | } |
twisti@4323 | 1180 | |
twisti@4323 | 1181 | save_frame(extraWords); |
twisti@4323 | 1182 | |
twisti@4323 | 1183 | if (s1_addr.base() == SP) { |
twisti@4323 | 1184 | ld_ptr(s1_addr.after_save(), d1); |
twisti@4323 | 1185 | } else if (s1->is_valid()) { |
twisti@4323 | 1186 | mov(s1->after_save(), d1); |
twisti@4323 | 1187 | } |
twisti@4323 | 1188 | |
twisti@4323 | 1189 | if (s2_addr.base() == SP) { |
twisti@4323 | 1190 | ld_ptr(s2_addr.after_save(), d2); |
twisti@4323 | 1191 | } else if (s2->is_valid()) { |
twisti@4323 | 1192 | mov(s2->after_save(), d2); |
twisti@4323 | 1193 | } |
twisti@4323 | 1194 | } |
twisti@4323 | 1195 | |
twisti@4323 | 1196 | |
twisti@4323 | 1197 | AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) { |
twisti@4323 | 1198 | assert(oop_recorder() != NULL, "this assembler needs a Recorder"); |
twisti@4323 | 1199 | int index = oop_recorder()->allocate_metadata_index(obj); |
twisti@4323 | 1200 | RelocationHolder rspec = metadata_Relocation::spec(index); |
twisti@4323 | 1201 | return AddressLiteral((address)obj, rspec); |
twisti@4323 | 1202 | } |
twisti@4323 | 1203 | |
twisti@4323 | 1204 | AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) { |
twisti@4323 | 1205 | assert(oop_recorder() != NULL, "this assembler needs a Recorder"); |
twisti@4323 | 1206 | int index = oop_recorder()->find_index(obj); |
twisti@4323 | 1207 | RelocationHolder rspec = metadata_Relocation::spec(index); |
twisti@4323 | 1208 | return AddressLiteral((address)obj, rspec); |
twisti@4323 | 1209 | } |
twisti@4323 | 1210 | |
twisti@4323 | 1211 | |
twisti@4323 | 1212 | AddressLiteral MacroAssembler::constant_oop_address(jobject obj) { |
twisti@4323 | 1213 | assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
twisti@4323 | 1214 | assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); |
twisti@4323 | 1215 | int oop_index = oop_recorder()->find_index(obj); |
twisti@4323 | 1216 | return AddressLiteral(obj, oop_Relocation::spec(oop_index)); |
twisti@4323 | 1217 | } |
twisti@4323 | 1218 | |
twisti@4323 | 1219 | void MacroAssembler::set_narrow_oop(jobject obj, Register d) { |
twisti@4323 | 1220 | assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
twisti@4323 | 1221 | int oop_index = oop_recorder()->find_index(obj); |
twisti@4323 | 1222 | RelocationHolder rspec = oop_Relocation::spec(oop_index); |
twisti@4323 | 1223 | |
twisti@4323 | 1224 | assert_not_delayed(); |
twisti@4323 | 1225 | // Relocation with special format (see relocInfo_sparc.hpp). |
twisti@4323 | 1226 | relocate(rspec, 1); |
twisti@4323 | 1227 | // Assembler::sethi(0x3fffff, d); |
twisti@4412 | 1228 | emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) ); |
twisti@4323 | 1229 | // Don't add relocation for 'add'. Do patching during 'sethi' processing. |
twisti@4323 | 1230 | add(d, 0x3ff, d); |
twisti@4323 | 1231 | |
twisti@4323 | 1232 | } |
twisti@4323 | 1233 | |
twisti@4323 | 1234 | void MacroAssembler::set_narrow_klass(Klass* k, Register d) { |
twisti@4323 | 1235 | assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
twisti@4323 | 1236 | int klass_index = oop_recorder()->find_index(k); |
twisti@4323 | 1237 | RelocationHolder rspec = metadata_Relocation::spec(klass_index); |
twisti@4323 | 1238 | narrowOop encoded_k = oopDesc::encode_klass(k); |
twisti@4323 | 1239 | |
twisti@4323 | 1240 | assert_not_delayed(); |
twisti@4323 | 1241 | // Relocation with special format (see relocInfo_sparc.hpp). |
twisti@4323 | 1242 | relocate(rspec, 1); |
twisti@4323 | 1243 | // Assembler::sethi(encoded_k, d); |
twisti@4412 | 1244 | emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(encoded_k) ); |
twisti@4323 | 1245 | // Don't add relocation for 'add'. Do patching during 'sethi' processing. |
twisti@4323 | 1246 | add(d, low10(encoded_k), d); |
twisti@4323 | 1247 | |
twisti@4323 | 1248 | } |
twisti@4323 | 1249 | |
twisti@4323 | 1250 | void MacroAssembler::align(int modulus) { |
twisti@4323 | 1251 | while (offset() % modulus != 0) nop(); |
twisti@4323 | 1252 | } |
twisti@4323 | 1253 | |
twisti@4323 | 1254 | |
twisti@4323 | 1255 | void MacroAssembler::safepoint() { |
twisti@4323 | 1256 | relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint)); |
twisti@4323 | 1257 | } |
twisti@4323 | 1258 | |
twisti@4323 | 1259 | |
twisti@4323 | 1260 | void RegistersForDebugging::print(outputStream* s) { |
twisti@4323 | 1261 | FlagSetting fs(Debugging, true); |
twisti@4323 | 1262 | int j; |
twisti@4323 | 1263 | for (j = 0; j < 8; ++j) { |
twisti@4323 | 1264 | if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); } |
twisti@4323 | 1265 | else { s->print( "fp = " ); os::print_location(s, i[j]); } |
twisti@4323 | 1266 | } |
twisti@4323 | 1267 | s->cr(); |
twisti@4323 | 1268 | |
twisti@4323 | 1269 | for (j = 0; j < 8; ++j) { |
twisti@4323 | 1270 | s->print("l%d = ", j); os::print_location(s, l[j]); |
twisti@4323 | 1271 | } |
twisti@4323 | 1272 | s->cr(); |
twisti@4323 | 1273 | |
twisti@4323 | 1274 | for (j = 0; j < 8; ++j) { |
twisti@4323 | 1275 | if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); } |
twisti@4323 | 1276 | else { s->print( "sp = " ); os::print_location(s, o[j]); } |
twisti@4323 | 1277 | } |
twisti@4323 | 1278 | s->cr(); |
twisti@4323 | 1279 | |
twisti@4323 | 1280 | for (j = 0; j < 8; ++j) { |
twisti@4323 | 1281 | s->print("g%d = ", j); os::print_location(s, g[j]); |
twisti@4323 | 1282 | } |
twisti@4323 | 1283 | s->cr(); |
twisti@4323 | 1284 | |
twisti@4323 | 1285 | // print out floats with compression |
twisti@4323 | 1286 | for (j = 0; j < 32; ) { |
twisti@4323 | 1287 | jfloat val = f[j]; |
twisti@4323 | 1288 | int last = j; |
twisti@4323 | 1289 | for ( ; last+1 < 32; ++last ) { |
twisti@4323 | 1290 | char b1[1024], b2[1024]; |
twisti@4323 | 1291 | sprintf(b1, "%f", val); |
twisti@4323 | 1292 | sprintf(b2, "%f", f[last+1]); |
twisti@4323 | 1293 | if (strcmp(b1, b2)) |
twisti@4323 | 1294 | break; |
twisti@4323 | 1295 | } |
twisti@4323 | 1296 | s->print("f%d", j); |
twisti@4323 | 1297 | if ( j != last ) s->print(" - f%d", last); |
twisti@4323 | 1298 | s->print(" = %f", val); |
twisti@4323 | 1299 | s->fill_to(25); |
twisti@4323 | 1300 | s->print_cr(" (0x%x)", val); |
twisti@4323 | 1301 | j = last + 1; |
twisti@4323 | 1302 | } |
twisti@4323 | 1303 | s->cr(); |
twisti@4323 | 1304 | |
twisti@4323 | 1305 | // and doubles (evens only) |
twisti@4323 | 1306 | for (j = 0; j < 32; ) { |
twisti@4323 | 1307 | jdouble val = d[j]; |
twisti@4323 | 1308 | int last = j; |
twisti@4323 | 1309 | for ( ; last+1 < 32; ++last ) { |
twisti@4323 | 1310 | char b1[1024], b2[1024]; |
twisti@4323 | 1311 | sprintf(b1, "%f", val); |
twisti@4323 | 1312 | sprintf(b2, "%f", d[last+1]); |
twisti@4323 | 1313 | if (strcmp(b1, b2)) |
twisti@4323 | 1314 | break; |
twisti@4323 | 1315 | } |
twisti@4323 | 1316 | s->print("d%d", 2 * j); |
twisti@4323 | 1317 | if ( j != last ) s->print(" - d%d", last); |
twisti@4323 | 1318 | s->print(" = %f", val); |
twisti@4323 | 1319 | s->fill_to(30); |
twisti@4323 | 1320 | s->print("(0x%x)", *(int*)&val); |
twisti@4323 | 1321 | s->fill_to(42); |
twisti@4323 | 1322 | s->print_cr("(0x%x)", *(1 + (int*)&val)); |
twisti@4323 | 1323 | j = last + 1; |
twisti@4323 | 1324 | } |
twisti@4323 | 1325 | s->cr(); |
twisti@4323 | 1326 | } |
twisti@4323 | 1327 | |
twisti@4323 | 1328 | void RegistersForDebugging::save_registers(MacroAssembler* a) { |
twisti@4323 | 1329 | a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); |
twisti@4323 | 1330 | a->flush_windows(); |
twisti@4323 | 1331 | int i; |
twisti@4323 | 1332 | for (i = 0; i < 8; ++i) { |
twisti@4323 | 1333 | a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); |
twisti@4323 | 1334 | a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); |
twisti@4323 | 1335 | a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); |
twisti@4323 | 1336 | a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); |
twisti@4323 | 1337 | } |
twisti@4323 | 1338 | for (i = 0; i < 32; ++i) { |
twisti@4323 | 1339 | a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); |
twisti@4323 | 1340 | } |
twisti@4323 | 1341 | for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) { |
twisti@4323 | 1342 | a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); |
twisti@4323 | 1343 | } |
twisti@4323 | 1344 | } |
twisti@4323 | 1345 | |
twisti@4323 | 1346 | void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { |
twisti@4323 | 1347 | for (int i = 1; i < 8; ++i) { |
twisti@4323 | 1348 | a->ld_ptr(r, g_offset(i), as_gRegister(i)); |
twisti@4323 | 1349 | } |
twisti@4323 | 1350 | for (int j = 0; j < 32; ++j) { |
twisti@4323 | 1351 | a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); |
twisti@4323 | 1352 | } |
twisti@4323 | 1353 | for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) { |
twisti@4323 | 1354 | a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); |
twisti@4323 | 1355 | } |
twisti@4323 | 1356 | } |
twisti@4323 | 1357 | |
twisti@4323 | 1358 | |
twisti@4323 | 1359 | // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack |
twisti@4323 | 1360 | void MacroAssembler::push_fTOS() { |
twisti@4323 | 1361 | // %%%%%% need to implement this |
twisti@4323 | 1362 | } |
twisti@4323 | 1363 | |
twisti@4323 | 1364 | // pops double TOS element from CPU stack and pushes on FPU stack |
twisti@4323 | 1365 | void MacroAssembler::pop_fTOS() { |
twisti@4323 | 1366 | // %%%%%% need to implement this |
twisti@4323 | 1367 | } |
twisti@4323 | 1368 | |
twisti@4323 | 1369 | void MacroAssembler::empty_FPU_stack() { |
twisti@4323 | 1370 | // %%%%%% need to implement this |
twisti@4323 | 1371 | } |
twisti@4323 | 1372 | |
twisti@4323 | 1373 | void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { |
twisti@4323 | 1374 | // plausibility check for oops |
twisti@4323 | 1375 | if (!VerifyOops) return; |
twisti@4323 | 1376 | |
twisti@4323 | 1377 | if (reg == G0) return; // always NULL, which is always an oop |
twisti@4323 | 1378 | |
twisti@4323 | 1379 | BLOCK_COMMENT("verify_oop {"); |
twisti@4323 | 1380 | char buffer[64]; |
twisti@4323 | 1381 | #ifdef COMPILER1 |
twisti@4323 | 1382 | if (CommentedAssembly) { |
twisti@4323 | 1383 | snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset()); |
twisti@4323 | 1384 | block_comment(buffer); |
twisti@4323 | 1385 | } |
twisti@4323 | 1386 | #endif |
twisti@4323 | 1387 | |
roland@4767 | 1388 | const char* real_msg = NULL; |
roland@4767 | 1389 | { |
roland@4767 | 1390 | ResourceMark rm; |
roland@4767 | 1391 | stringStream ss; |
roland@4767 | 1392 | ss.print("%s at offset %d (%s:%d)", msg, offset(), file, line); |
roland@4767 | 1393 | real_msg = code_string(ss.as_string()); |
roland@4767 | 1394 | } |
twisti@4323 | 1395 | |
twisti@4323 | 1396 | // Call indirectly to solve generation ordering problem |
twisti@4323 | 1397 | AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); |
twisti@4323 | 1398 | |
twisti@4323 | 1399 | // Make some space on stack above the current register window. |
twisti@4323 | 1400 | // Enough to hold 8 64-bit registers. |
twisti@4323 | 1401 | add(SP,-8*8,SP); |
twisti@4323 | 1402 | |
twisti@4323 | 1403 | // Save some 64-bit registers; a normal 'save' chops the heads off |
twisti@4323 | 1404 | // of 64-bit longs in the 32-bit build. |
twisti@4323 | 1405 | stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); |
twisti@4323 | 1406 | stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); |
twisti@4323 | 1407 | mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed |
twisti@4323 | 1408 | stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); |
twisti@4323 | 1409 | |
twisti@4323 | 1410 | // Size of set() should stay the same |
twisti@4323 | 1411 | patchable_set((intptr_t)real_msg, O1); |
twisti@4323 | 1412 | // Load address to call to into O7 |
twisti@4323 | 1413 | load_ptr_contents(a, O7); |
twisti@4323 | 1414 | // Register call to verify_oop_subroutine |
twisti@4323 | 1415 | callr(O7, G0); |
twisti@4323 | 1416 | delayed()->nop(); |
twisti@4323 | 1417 | // recover frame size |
twisti@4323 | 1418 | add(SP, 8*8,SP); |
twisti@4323 | 1419 | BLOCK_COMMENT("} verify_oop"); |
twisti@4323 | 1420 | } |
twisti@4323 | 1421 | |
twisti@4323 | 1422 | void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { |
twisti@4323 | 1423 | // plausibility check for oops |
twisti@4323 | 1424 | if (!VerifyOops) return; |
twisti@4323 | 1425 | |
roland@4767 | 1426 | const char* real_msg = NULL; |
roland@4767 | 1427 | { |
roland@4767 | 1428 | ResourceMark rm; |
roland@4767 | 1429 | stringStream ss; |
roland@4767 | 1430 | ss.print("%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); |
roland@4767 | 1431 | real_msg = code_string(ss.as_string()); |
roland@4767 | 1432 | } |
twisti@4323 | 1433 | |
twisti@4323 | 1434 | // Call indirectly to solve generation ordering problem |
twisti@4323 | 1435 | AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); |
twisti@4323 | 1436 | |
twisti@4323 | 1437 | // Make some space on stack above the current register window. |
twisti@4323 | 1438 | // Enough to hold 8 64-bit registers. |
twisti@4323 | 1439 | add(SP,-8*8,SP); |
twisti@4323 | 1440 | |
twisti@4323 | 1441 | // Save some 64-bit registers; a normal 'save' chops the heads off |
twisti@4323 | 1442 | // of 64-bit longs in the 32-bit build. |
twisti@4323 | 1443 | stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); |
twisti@4323 | 1444 | stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); |
twisti@4323 | 1445 | ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed |
twisti@4323 | 1446 | stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); |
twisti@4323 | 1447 | |
twisti@4323 | 1448 | // Size of set() should stay the same |
twisti@4323 | 1449 | patchable_set((intptr_t)real_msg, O1); |
twisti@4323 | 1450 | // Load address to call to into O7 |
twisti@4323 | 1451 | load_ptr_contents(a, O7); |
twisti@4323 | 1452 | // Register call to verify_oop_subroutine |
twisti@4323 | 1453 | callr(O7, G0); |
twisti@4323 | 1454 | delayed()->nop(); |
twisti@4323 | 1455 | // recover frame size |
twisti@4323 | 1456 | add(SP, 8*8,SP); |
twisti@4323 | 1457 | } |
twisti@4323 | 1458 | |
twisti@4323 | 1459 | // side-door communication with signalHandler in os_solaris.cpp |
twisti@4323 | 1460 | address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; |
twisti@4323 | 1461 | |
twisti@4323 | 1462 | // This macro is expanded just once; it creates shared code. Contract: |
twisti@4323 | 1463 | // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY |
twisti@4323 | 1464 | // registers, including flags. May not use a register 'save', as this blows |
twisti@4323 | 1465 | // the high bits of the O-regs if they contain Long values. Acts as a 'leaf' |
twisti@4323 | 1466 | // call. |
twisti@4323 | 1467 | void MacroAssembler::verify_oop_subroutine() { |
twisti@4323 | 1468 | assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" ); |
twisti@4323 | 1469 | |
twisti@4323 | 1470 | // Leaf call; no frame. |
twisti@4323 | 1471 | Label succeed, fail, null_or_fail; |
twisti@4323 | 1472 | |
twisti@4323 | 1473 | // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). |
twisti@4323 | 1474 | // O0 is now the oop to be checked. O7 is the return address. |
twisti@4323 | 1475 | Register O0_obj = O0; |
twisti@4323 | 1476 | |
twisti@4323 | 1477 | // Save some more registers for temps. |
twisti@4323 | 1478 | stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); |
twisti@4323 | 1479 | stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); |
twisti@4323 | 1480 | stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); |
twisti@4323 | 1481 | stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); |
twisti@4323 | 1482 | |
twisti@4323 | 1483 | // Save flags |
twisti@4323 | 1484 | Register O5_save_flags = O5; |
twisti@4323 | 1485 | rdccr( O5_save_flags ); |
twisti@4323 | 1486 | |
twisti@4323 | 1487 | { // count number of verifies |
twisti@4323 | 1488 | Register O2_adr = O2; |
twisti@4323 | 1489 | Register O3_accum = O3; |
twisti@4323 | 1490 | inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum); |
twisti@4323 | 1491 | } |
twisti@4323 | 1492 | |
twisti@4323 | 1493 | Register O2_mask = O2; |
twisti@4323 | 1494 | Register O3_bits = O3; |
twisti@4323 | 1495 | Register O4_temp = O4; |
twisti@4323 | 1496 | |
twisti@4323 | 1497 | // mark lower end of faulting range |
twisti@4323 | 1498 | assert(_verify_oop_implicit_branch[0] == NULL, "set once"); |
twisti@4323 | 1499 | _verify_oop_implicit_branch[0] = pc(); |
twisti@4323 | 1500 | |
twisti@4323 | 1501 | // We can't check the mark oop because it could be in the process of |
twisti@4323 | 1502 | // locking or unlocking while this is running. |
twisti@4323 | 1503 | set(Universe::verify_oop_mask (), O2_mask); |
twisti@4323 | 1504 | set(Universe::verify_oop_bits (), O3_bits); |
twisti@4323 | 1505 | |
twisti@4323 | 1506 | // assert((obj & oop_mask) == oop_bits); |
twisti@4323 | 1507 | and3(O0_obj, O2_mask, O4_temp); |
twisti@4323 | 1508 | cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail); |
twisti@4323 | 1509 | |
twisti@4323 | 1510 | if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { |
twisti@4323 | 1511 | // the null_or_fail case is useless; must test for null separately |
twisti@4323 | 1512 | br_null_short(O0_obj, pn, succeed); |
twisti@4323 | 1513 | } |
twisti@4323 | 1514 | |
twisti@4323 | 1515 | // Check the Klass* of this object for being in the right area of memory. |
twisti@4323 | 1516 | // Cannot do the load in the delay above slot in case O0 is null |
twisti@4323 | 1517 | load_klass(O0_obj, O0_obj); |
twisti@4323 | 1518 | // assert((klass != NULL) |
twisti@4323 | 1519 | br_null_short(O0_obj, pn, fail); |
twisti@4323 | 1520 | // TODO: Future assert that klass is lower 4g memory for UseCompressedKlassPointers |
twisti@4323 | 1521 | |
twisti@4323 | 1522 | wrccr( O5_save_flags ); // Restore CCR's |
twisti@4323 | 1523 | |
twisti@4323 | 1524 | // mark upper end of faulting range |
twisti@4323 | 1525 | _verify_oop_implicit_branch[1] = pc(); |
twisti@4323 | 1526 | |
twisti@4323 | 1527 | //----------------------- |
twisti@4323 | 1528 | // all tests pass |
twisti@4323 | 1529 | bind(succeed); |
twisti@4323 | 1530 | |
twisti@4323 | 1531 | // Restore prior 64-bit registers |
twisti@4323 | 1532 | ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); |
twisti@4323 | 1533 | ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); |
twisti@4323 | 1534 | ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); |
twisti@4323 | 1535 | ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); |
twisti@4323 | 1536 | ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); |
twisti@4323 | 1537 | ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); |
twisti@4323 | 1538 | |
twisti@4323 | 1539 | retl(); // Leaf return; restore prior O7 in delay slot |
twisti@4323 | 1540 | delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); |
twisti@4323 | 1541 | |
twisti@4323 | 1542 | //----------------------- |
twisti@4323 | 1543 | bind(null_or_fail); // nulls are less common but OK |
twisti@4323 | 1544 | br_null(O0_obj, false, pt, succeed); |
twisti@4323 | 1545 | delayed()->wrccr( O5_save_flags ); // Restore CCR's |
twisti@4323 | 1546 | |
twisti@4323 | 1547 | //----------------------- |
twisti@4323 | 1548 | // report failure: |
twisti@4323 | 1549 | bind(fail); |
twisti@4323 | 1550 | _verify_oop_implicit_branch[2] = pc(); |
twisti@4323 | 1551 | |
twisti@4323 | 1552 | wrccr( O5_save_flags ); // Restore CCR's |
twisti@4323 | 1553 | |
twisti@4323 | 1554 | save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); |
twisti@4323 | 1555 | |
twisti@4323 | 1556 | // stop_subroutine expects message pointer in I1. |
twisti@4323 | 1557 | mov(I1, O1); |
twisti@4323 | 1558 | |
twisti@4323 | 1559 | // Restore prior 64-bit registers |
twisti@4323 | 1560 | ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); |
twisti@4323 | 1561 | ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); |
twisti@4323 | 1562 | ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); |
twisti@4323 | 1563 | ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); |
twisti@4323 | 1564 | ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); |
twisti@4323 | 1565 | ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); |
twisti@4323 | 1566 | |
twisti@4323 | 1567 | // factor long stop-sequence into subroutine to save space |
twisti@4323 | 1568 | assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); |
twisti@4323 | 1569 | |
twisti@4323 | 1570 | // call indirectly to solve generation ordering problem |
twisti@4323 | 1571 | AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address()); |
twisti@4323 | 1572 | load_ptr_contents(al, O5); |
twisti@4323 | 1573 | jmpl(O5, 0, O7); |
twisti@4323 | 1574 | delayed()->nop(); |
twisti@4323 | 1575 | } |
twisti@4323 | 1576 | |
twisti@4323 | 1577 | |
twisti@4323 | 1578 | void MacroAssembler::stop(const char* msg) { |
twisti@4323 | 1579 | // save frame first to get O7 for return address |
twisti@4323 | 1580 | // add one word to size in case struct is odd number of words long |
twisti@4323 | 1581 | // It must be doubleword-aligned for storing doubles into it. |
twisti@4323 | 1582 | |
twisti@4323 | 1583 | save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); |
twisti@4323 | 1584 | |
twisti@4323 | 1585 | // stop_subroutine expects message pointer in I1. |
twisti@4323 | 1586 | // Size of set() should stay the same |
twisti@4323 | 1587 | patchable_set((intptr_t)msg, O1); |
twisti@4323 | 1588 | |
twisti@4323 | 1589 | // factor long stop-sequence into subroutine to save space |
twisti@4323 | 1590 | assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); |
twisti@4323 | 1591 | |
twisti@4323 | 1592 | // call indirectly to solve generation ordering problem |
twisti@4323 | 1593 | AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address()); |
twisti@4323 | 1594 | load_ptr_contents(a, O5); |
twisti@4323 | 1595 | jmpl(O5, 0, O7); |
twisti@4323 | 1596 | delayed()->nop(); |
twisti@4323 | 1597 | |
twisti@4323 | 1598 | breakpoint_trap(); // make stop actually stop rather than writing |
twisti@4323 | 1599 | // unnoticeable results in the output files. |
twisti@4323 | 1600 | |
twisti@4323 | 1601 | // restore(); done in callee to save space! |
twisti@4323 | 1602 | } |
twisti@4323 | 1603 | |
twisti@4323 | 1604 | |
twisti@4323 | 1605 | void MacroAssembler::warn(const char* msg) { |
twisti@4323 | 1606 | save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); |
twisti@4323 | 1607 | RegistersForDebugging::save_registers(this); |
twisti@4323 | 1608 | mov(O0, L0); |
twisti@4323 | 1609 | // Size of set() should stay the same |
twisti@4323 | 1610 | patchable_set((intptr_t)msg, O0); |
twisti@4323 | 1611 | call( CAST_FROM_FN_PTR(address, warning) ); |
twisti@4323 | 1612 | delayed()->nop(); |
twisti@4323 | 1613 | // ret(); |
twisti@4323 | 1614 | // delayed()->restore(); |
twisti@4323 | 1615 | RegistersForDebugging::restore_registers(this, L0); |
twisti@4323 | 1616 | restore(); |
twisti@4323 | 1617 | } |
twisti@4323 | 1618 | |
twisti@4323 | 1619 | |
twisti@4323 | 1620 | void MacroAssembler::untested(const char* what) { |
twisti@4323 | 1621 | // We must be able to turn interactive prompting off |
twisti@4323 | 1622 | // in order to run automated test scripts on the VM |
twisti@4323 | 1623 | // Use the flag ShowMessageBoxOnError |
twisti@4323 | 1624 | |
roland@4767 | 1625 | const char* b = NULL; |
roland@4767 | 1626 | { |
roland@4767 | 1627 | ResourceMark rm; |
roland@4767 | 1628 | stringStream ss; |
roland@4767 | 1629 | ss.print("untested: %s", what); |
roland@4767 | 1630 | b = code_string(ss.as_string()); |
roland@4767 | 1631 | } |
twisti@4323 | 1632 | if (ShowMessageBoxOnError) { STOP(b); } |
twisti@4323 | 1633 | else { warn(b); } |
twisti@4323 | 1634 | } |
twisti@4323 | 1635 | |
twisti@4323 | 1636 | |
twisti@4323 | 1637 | void MacroAssembler::stop_subroutine() { |
twisti@4323 | 1638 | RegistersForDebugging::save_registers(this); |
twisti@4323 | 1639 | |
twisti@4323 | 1640 | // for the sake of the debugger, stick a PC on the current frame |
twisti@4323 | 1641 | // (this assumes that the caller has performed an extra "save") |
twisti@4323 | 1642 | mov(I7, L7); |
twisti@4323 | 1643 | add(O7, -7 * BytesPerInt, I7); |
twisti@4323 | 1644 | |
twisti@4323 | 1645 | save_frame(); // one more save to free up another O7 register |
twisti@4323 | 1646 | mov(I0, O1); // addr of reg save area |
twisti@4323 | 1647 | |
twisti@4323 | 1648 | // We expect pointer to message in I1. Caller must set it up in O1 |
twisti@4323 | 1649 | mov(I1, O0); // get msg |
twisti@4323 | 1650 | call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); |
twisti@4323 | 1651 | delayed()->nop(); |
twisti@4323 | 1652 | |
twisti@4323 | 1653 | restore(); |
twisti@4323 | 1654 | |
twisti@4323 | 1655 | RegistersForDebugging::restore_registers(this, O0); |
twisti@4323 | 1656 | |
twisti@4323 | 1657 | save_frame(0); |
twisti@4323 | 1658 | call(CAST_FROM_FN_PTR(address,breakpoint)); |
twisti@4323 | 1659 | delayed()->nop(); |
twisti@4323 | 1660 | restore(); |
twisti@4323 | 1661 | |
twisti@4323 | 1662 | mov(L7, I7); |
twisti@4323 | 1663 | retl(); |
twisti@4323 | 1664 | delayed()->restore(); // see stop above |
twisti@4323 | 1665 | } |
twisti@4323 | 1666 | |
twisti@4323 | 1667 | |
twisti@4323 | 1668 | void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { |
twisti@4323 | 1669 | if ( ShowMessageBoxOnError ) { |
twisti@4323 | 1670 | JavaThread* thread = JavaThread::current(); |
twisti@4323 | 1671 | JavaThreadState saved_state = thread->thread_state(); |
twisti@4323 | 1672 | thread->set_thread_state(_thread_in_vm); |
twisti@4323 | 1673 | { |
twisti@4323 | 1674 | // In order to get locks work, we need to fake a in_VM state |
twisti@4323 | 1675 | ttyLocker ttyl; |
twisti@4323 | 1676 | ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); |
twisti@4323 | 1677 | if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { |
twisti@4323 | 1678 | BytecodeCounter::print(); |
twisti@4323 | 1679 | } |
twisti@4323 | 1680 | if (os::message_box(msg, "Execution stopped, print registers?")) |
twisti@4323 | 1681 | regs->print(::tty); |
twisti@4323 | 1682 | } |
twisti@4323 | 1683 | BREAKPOINT; |
twisti@4323 | 1684 | ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); |
twisti@4323 | 1685 | } |
twisti@4323 | 1686 | else { |
twisti@4323 | 1687 | ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); |
twisti@4323 | 1688 | } |
twisti@4323 | 1689 | assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
twisti@4323 | 1690 | } |
twisti@4323 | 1691 | |
twisti@4323 | 1692 | |
twisti@4323 | 1693 | void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { |
twisti@4323 | 1694 | subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? |
twisti@4323 | 1695 | Label no_extras; |
twisti@4323 | 1696 | br( negative, true, pt, no_extras ); // if neg, clear reg |
twisti@4323 | 1697 | delayed()->set(0, Rresult); // annuled, so only if taken |
twisti@4323 | 1698 | bind( no_extras ); |
twisti@4323 | 1699 | } |
twisti@4323 | 1700 | |
twisti@4323 | 1701 | |
twisti@4323 | 1702 | void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { |
twisti@4323 | 1703 | #ifdef _LP64 |
twisti@4323 | 1704 | add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); |
twisti@4323 | 1705 | #else |
twisti@4323 | 1706 | add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); |
twisti@4323 | 1707 | #endif |
twisti@4323 | 1708 | bclr(1, Rresult); |
twisti@4323 | 1709 | sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes |
twisti@4323 | 1710 | } |
twisti@4323 | 1711 | |
twisti@4323 | 1712 | |
twisti@4323 | 1713 | void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { |
twisti@4323 | 1714 | calc_frame_size(Rextra_words, Rresult); |
twisti@4323 | 1715 | neg(Rresult); |
twisti@4323 | 1716 | save(SP, Rresult, SP); |
twisti@4323 | 1717 | } |
twisti@4323 | 1718 | |
twisti@4323 | 1719 | |
twisti@4323 | 1720 | // --------------------------------------------------------- |
twisti@4323 | 1721 | Assembler::RCondition cond2rcond(Assembler::Condition c) { |
twisti@4323 | 1722 | switch (c) { |
twisti@4323 | 1723 | /*case zero: */ |
twisti@4323 | 1724 | case Assembler::equal: return Assembler::rc_z; |
twisti@4323 | 1725 | case Assembler::lessEqual: return Assembler::rc_lez; |
twisti@4323 | 1726 | case Assembler::less: return Assembler::rc_lz; |
twisti@4323 | 1727 | /*case notZero:*/ |
twisti@4323 | 1728 | case Assembler::notEqual: return Assembler::rc_nz; |
twisti@4323 | 1729 | case Assembler::greater: return Assembler::rc_gz; |
twisti@4323 | 1730 | case Assembler::greaterEqual: return Assembler::rc_gez; |
twisti@4323 | 1731 | } |
twisti@4323 | 1732 | ShouldNotReachHere(); |
twisti@4323 | 1733 | return Assembler::rc_z; |
twisti@4323 | 1734 | } |
twisti@4323 | 1735 | |
twisti@4323 | 1736 | // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS |
twisti@4323 | 1737 | void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) { |
twisti@4323 | 1738 | tst(s1); |
twisti@4323 | 1739 | br (c, a, p, L); |
twisti@4323 | 1740 | } |
twisti@4323 | 1741 | |
twisti@4323 | 1742 | // Compares a pointer register with zero and branches on null. |
twisti@4323 | 1743 | // Does a test & branch on 32-bit systems and a register-branch on 64-bit. |
twisti@4323 | 1744 | void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { |
twisti@4323 | 1745 | assert_not_delayed(); |
twisti@4323 | 1746 | #ifdef _LP64 |
twisti@4323 | 1747 | bpr( rc_z, a, p, s1, L ); |
twisti@4323 | 1748 | #else |
twisti@4323 | 1749 | tst(s1); |
twisti@4323 | 1750 | br ( zero, a, p, L ); |
twisti@4323 | 1751 | #endif |
twisti@4323 | 1752 | } |
twisti@4323 | 1753 | |
twisti@4323 | 1754 | void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { |
twisti@4323 | 1755 | assert_not_delayed(); |
twisti@4323 | 1756 | #ifdef _LP64 |
twisti@4323 | 1757 | bpr( rc_nz, a, p, s1, L ); |
twisti@4323 | 1758 | #else |
twisti@4323 | 1759 | tst(s1); |
twisti@4323 | 1760 | br ( notZero, a, p, L ); |
twisti@4323 | 1761 | #endif |
twisti@4323 | 1762 | } |
twisti@4323 | 1763 | |
twisti@4323 | 1764 | // Compare registers and branch with nop in delay slot or cbcond without delay slot. |
twisti@4323 | 1765 | |
twisti@4323 | 1766 | // Compare integer (32 bit) values (icc only). |
twisti@4323 | 1767 | void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c, |
twisti@4323 | 1768 | Predict p, Label& L) { |
twisti@4323 | 1769 | assert_not_delayed(); |
twisti@4323 | 1770 | if (use_cbcond(L)) { |
twisti@4323 | 1771 | Assembler::cbcond(c, icc, s1, s2, L); |
twisti@4323 | 1772 | } else { |
twisti@4323 | 1773 | cmp(s1, s2); |
twisti@4323 | 1774 | br(c, false, p, L); |
twisti@4323 | 1775 | delayed()->nop(); |
twisti@4323 | 1776 | } |
twisti@4323 | 1777 | } |
twisti@4323 | 1778 | |
twisti@4323 | 1779 | // Compare integer (32 bit) values (icc only). |
twisti@4323 | 1780 | void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c, |
twisti@4323 | 1781 | Predict p, Label& L) { |
twisti@4323 | 1782 | assert_not_delayed(); |
twisti@4323 | 1783 | if (is_simm(simm13a,5) && use_cbcond(L)) { |
twisti@4323 | 1784 | Assembler::cbcond(c, icc, s1, simm13a, L); |
twisti@4323 | 1785 | } else { |
twisti@4323 | 1786 | cmp(s1, simm13a); |
twisti@4323 | 1787 | br(c, false, p, L); |
twisti@4323 | 1788 | delayed()->nop(); |
twisti@4323 | 1789 | } |
twisti@4323 | 1790 | } |
twisti@4323 | 1791 | |
twisti@4323 | 1792 | // Branch that tests xcc in LP64 and icc in !LP64 |
twisti@4323 | 1793 | void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c, |
twisti@4323 | 1794 | Predict p, Label& L) { |
twisti@4323 | 1795 | assert_not_delayed(); |
twisti@4323 | 1796 | if (use_cbcond(L)) { |
twisti@4323 | 1797 | Assembler::cbcond(c, ptr_cc, s1, s2, L); |
twisti@4323 | 1798 | } else { |
twisti@4323 | 1799 | cmp(s1, s2); |
twisti@4323 | 1800 | brx(c, false, p, L); |
twisti@4323 | 1801 | delayed()->nop(); |
twisti@4323 | 1802 | } |
twisti@4323 | 1803 | } |
twisti@4323 | 1804 | |
twisti@4323 | 1805 | // Branch that tests xcc in LP64 and icc in !LP64 |
twisti@4323 | 1806 | void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c, |
twisti@4323 | 1807 | Predict p, Label& L) { |
twisti@4323 | 1808 | assert_not_delayed(); |
twisti@4323 | 1809 | if (is_simm(simm13a,5) && use_cbcond(L)) { |
twisti@4323 | 1810 | Assembler::cbcond(c, ptr_cc, s1, simm13a, L); |
twisti@4323 | 1811 | } else { |
twisti@4323 | 1812 | cmp(s1, simm13a); |
twisti@4323 | 1813 | brx(c, false, p, L); |
twisti@4323 | 1814 | delayed()->nop(); |
twisti@4323 | 1815 | } |
twisti@4323 | 1816 | } |
twisti@4323 | 1817 | |
twisti@4323 | 1818 | // Short branch version for compares a pointer with zero. |
twisti@4323 | 1819 | |
twisti@4323 | 1820 | void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) { |
twisti@4323 | 1821 | assert_not_delayed(); |
twisti@4323 | 1822 | if (use_cbcond(L)) { |
twisti@4323 | 1823 | Assembler::cbcond(zero, ptr_cc, s1, 0, L); |
twisti@4323 | 1824 | return; |
twisti@4323 | 1825 | } |
twisti@4323 | 1826 | br_null(s1, false, p, L); |
twisti@4323 | 1827 | delayed()->nop(); |
twisti@4323 | 1828 | } |
twisti@4323 | 1829 | |
twisti@4323 | 1830 | void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) { |
twisti@4323 | 1831 | assert_not_delayed(); |
twisti@4323 | 1832 | if (use_cbcond(L)) { |
twisti@4323 | 1833 | Assembler::cbcond(notZero, ptr_cc, s1, 0, L); |
twisti@4323 | 1834 | return; |
twisti@4323 | 1835 | } |
twisti@4323 | 1836 | br_notnull(s1, false, p, L); |
twisti@4323 | 1837 | delayed()->nop(); |
twisti@4323 | 1838 | } |
twisti@4323 | 1839 | |
twisti@4323 | 1840 | // Unconditional short branch |
twisti@4323 | 1841 | void MacroAssembler::ba_short(Label& L) { |
twisti@4323 | 1842 | if (use_cbcond(L)) { |
twisti@4323 | 1843 | Assembler::cbcond(equal, icc, G0, G0, L); |
twisti@4323 | 1844 | return; |
twisti@4323 | 1845 | } |
twisti@4323 | 1846 | br(always, false, pt, L); |
twisti@4323 | 1847 | delayed()->nop(); |
twisti@4323 | 1848 | } |
twisti@4323 | 1849 | |
twisti@4323 | 1850 | // instruction sequences factored across compiler & interpreter |
twisti@4323 | 1851 | |
twisti@4323 | 1852 | |
twisti@4323 | 1853 | void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, |
twisti@4323 | 1854 | Register Rb_hi, Register Rb_low, |
twisti@4323 | 1855 | Register Rresult) { |
twisti@4323 | 1856 | |
twisti@4323 | 1857 | Label check_low_parts, done; |
twisti@4323 | 1858 | |
twisti@4323 | 1859 | cmp(Ra_hi, Rb_hi ); // compare hi parts |
twisti@4323 | 1860 | br(equal, true, pt, check_low_parts); |
twisti@4323 | 1861 | delayed()->cmp(Ra_low, Rb_low); // test low parts |
twisti@4323 | 1862 | |
twisti@4323 | 1863 | // And, with an unsigned comparison, it does not matter if the numbers |
twisti@4323 | 1864 | // are negative or not. |
twisti@4323 | 1865 | // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. |
twisti@4323 | 1866 | // The second one is bigger (unsignedly). |
twisti@4323 | 1867 | |
twisti@4323 | 1868 | // Other notes: The first move in each triplet can be unconditional |
twisti@4323 | 1869 | // (and therefore probably prefetchable). |
twisti@4323 | 1870 | // And the equals case for the high part does not need testing, |
twisti@4323 | 1871 | // since that triplet is reached only after finding the high halves differ. |
twisti@4323 | 1872 | |
twisti@4323 | 1873 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 1874 | mov(-1, Rresult); |
twisti@4323 | 1875 | ba(done); delayed()-> movcc(greater, false, icc, 1, Rresult); |
twisti@4323 | 1876 | } else { |
twisti@4323 | 1877 | br(less, true, pt, done); delayed()-> set(-1, Rresult); |
twisti@4323 | 1878 | br(greater, true, pt, done); delayed()-> set( 1, Rresult); |
twisti@4323 | 1879 | } |
twisti@4323 | 1880 | |
twisti@4323 | 1881 | bind( check_low_parts ); |
twisti@4323 | 1882 | |
twisti@4323 | 1883 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 1884 | mov( -1, Rresult); |
twisti@4323 | 1885 | movcc(equal, false, icc, 0, Rresult); |
twisti@4323 | 1886 | movcc(greaterUnsigned, false, icc, 1, Rresult); |
twisti@4323 | 1887 | } else { |
twisti@4323 | 1888 | set(-1, Rresult); |
twisti@4323 | 1889 | br(equal, true, pt, done); delayed()->set( 0, Rresult); |
twisti@4323 | 1890 | br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult); |
twisti@4323 | 1891 | } |
twisti@4323 | 1892 | bind( done ); |
twisti@4323 | 1893 | } |
twisti@4323 | 1894 | |
twisti@4323 | 1895 | void MacroAssembler::lneg( Register Rhi, Register Rlow ) { |
twisti@4323 | 1896 | subcc( G0, Rlow, Rlow ); |
twisti@4323 | 1897 | subc( G0, Rhi, Rhi ); |
twisti@4323 | 1898 | } |
twisti@4323 | 1899 | |
twisti@4323 | 1900 | void MacroAssembler::lshl( Register Rin_high, Register Rin_low, |
twisti@4323 | 1901 | Register Rcount, |
twisti@4323 | 1902 | Register Rout_high, Register Rout_low, |
twisti@4323 | 1903 | Register Rtemp ) { |
twisti@4323 | 1904 | |
twisti@4323 | 1905 | |
twisti@4323 | 1906 | Register Ralt_count = Rtemp; |
twisti@4323 | 1907 | Register Rxfer_bits = Rtemp; |
twisti@4323 | 1908 | |
twisti@4323 | 1909 | assert( Ralt_count != Rin_high |
twisti@4323 | 1910 | && Ralt_count != Rin_low |
twisti@4323 | 1911 | && Ralt_count != Rcount |
twisti@4323 | 1912 | && Rxfer_bits != Rin_low |
twisti@4323 | 1913 | && Rxfer_bits != Rin_high |
twisti@4323 | 1914 | && Rxfer_bits != Rcount |
twisti@4323 | 1915 | && Rxfer_bits != Rout_low |
twisti@4323 | 1916 | && Rout_low != Rin_high, |
twisti@4323 | 1917 | "register alias checks"); |
twisti@4323 | 1918 | |
twisti@4323 | 1919 | Label big_shift, done; |
twisti@4323 | 1920 | |
twisti@4323 | 1921 | // This code can be optimized to use the 64 bit shifts in V9. |
twisti@4323 | 1922 | // Here we use the 32 bit shifts. |
twisti@4323 | 1923 | |
twisti@4323 | 1924 | and3( Rcount, 0x3f, Rcount); // take least significant 6 bits |
twisti@4323 | 1925 | subcc(Rcount, 31, Ralt_count); |
twisti@4323 | 1926 | br(greater, true, pn, big_shift); |
twisti@4323 | 1927 | delayed()->dec(Ralt_count); |
twisti@4323 | 1928 | |
twisti@4323 | 1929 | // shift < 32 bits, Ralt_count = Rcount-31 |
twisti@4323 | 1930 | |
twisti@4323 | 1931 | // We get the transfer bits by shifting right by 32-count the low |
twisti@4323 | 1932 | // register. This is done by shifting right by 31-count and then by one |
twisti@4323 | 1933 | // more to take care of the special (rare) case where count is zero |
twisti@4323 | 1934 | // (shifting by 32 would not work). |
twisti@4323 | 1935 | |
twisti@4323 | 1936 | neg(Ralt_count); |
twisti@4323 | 1937 | |
twisti@4323 | 1938 | // The order of the next two instructions is critical in the case where |
twisti@4323 | 1939 | // Rin and Rout are the same and should not be reversed. |
twisti@4323 | 1940 | |
twisti@4323 | 1941 | srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count |
twisti@4323 | 1942 | if (Rcount != Rout_low) { |
twisti@4323 | 1943 | sll(Rin_low, Rcount, Rout_low); // low half |
twisti@4323 | 1944 | } |
twisti@4323 | 1945 | sll(Rin_high, Rcount, Rout_high); |
twisti@4323 | 1946 | if (Rcount == Rout_low) { |
twisti@4323 | 1947 | sll(Rin_low, Rcount, Rout_low); // low half |
twisti@4323 | 1948 | } |
twisti@4323 | 1949 | srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more |
twisti@4323 | 1950 | ba(done); |
twisti@4323 | 1951 | delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low |
twisti@4323 | 1952 | |
twisti@4323 | 1953 | // shift >= 32 bits, Ralt_count = Rcount-32 |
twisti@4323 | 1954 | bind(big_shift); |
twisti@4323 | 1955 | sll(Rin_low, Ralt_count, Rout_high ); |
twisti@4323 | 1956 | clr(Rout_low); |
twisti@4323 | 1957 | |
twisti@4323 | 1958 | bind(done); |
twisti@4323 | 1959 | } |
twisti@4323 | 1960 | |
twisti@4323 | 1961 | |
twisti@4323 | 1962 | void MacroAssembler::lshr( Register Rin_high, Register Rin_low, |
twisti@4323 | 1963 | Register Rcount, |
twisti@4323 | 1964 | Register Rout_high, Register Rout_low, |
twisti@4323 | 1965 | Register Rtemp ) { |
twisti@4323 | 1966 | |
twisti@4323 | 1967 | Register Ralt_count = Rtemp; |
twisti@4323 | 1968 | Register Rxfer_bits = Rtemp; |
twisti@4323 | 1969 | |
twisti@4323 | 1970 | assert( Ralt_count != Rin_high |
twisti@4323 | 1971 | && Ralt_count != Rin_low |
twisti@4323 | 1972 | && Ralt_count != Rcount |
twisti@4323 | 1973 | && Rxfer_bits != Rin_low |
twisti@4323 | 1974 | && Rxfer_bits != Rin_high |
twisti@4323 | 1975 | && Rxfer_bits != Rcount |
twisti@4323 | 1976 | && Rxfer_bits != Rout_high |
twisti@4323 | 1977 | && Rout_high != Rin_low, |
twisti@4323 | 1978 | "register alias checks"); |
twisti@4323 | 1979 | |
twisti@4323 | 1980 | Label big_shift, done; |
twisti@4323 | 1981 | |
twisti@4323 | 1982 | // This code can be optimized to use the 64 bit shifts in V9. |
twisti@4323 | 1983 | // Here we use the 32 bit shifts. |
twisti@4323 | 1984 | |
twisti@4323 | 1985 | and3( Rcount, 0x3f, Rcount); // take least significant 6 bits |
twisti@4323 | 1986 | subcc(Rcount, 31, Ralt_count); |
twisti@4323 | 1987 | br(greater, true, pn, big_shift); |
twisti@4323 | 1988 | delayed()->dec(Ralt_count); |
twisti@4323 | 1989 | |
twisti@4323 | 1990 | // shift < 32 bits, Ralt_count = Rcount-31 |
twisti@4323 | 1991 | |
twisti@4323 | 1992 | // We get the transfer bits by shifting left by 32-count the high |
twisti@4323 | 1993 | // register. This is done by shifting left by 31-count and then by one |
twisti@4323 | 1994 | // more to take care of the special (rare) case where count is zero |
twisti@4323 | 1995 | // (shifting by 32 would not work). |
twisti@4323 | 1996 | |
twisti@4323 | 1997 | neg(Ralt_count); |
twisti@4323 | 1998 | if (Rcount != Rout_low) { |
twisti@4323 | 1999 | srl(Rin_low, Rcount, Rout_low); |
twisti@4323 | 2000 | } |
twisti@4323 | 2001 | |
twisti@4323 | 2002 | // The order of the next two instructions is critical in the case where |
twisti@4323 | 2003 | // Rin and Rout are the same and should not be reversed. |
twisti@4323 | 2004 | |
twisti@4323 | 2005 | sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count |
twisti@4323 | 2006 | sra(Rin_high, Rcount, Rout_high ); // high half |
twisti@4323 | 2007 | sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more |
twisti@4323 | 2008 | if (Rcount == Rout_low) { |
twisti@4323 | 2009 | srl(Rin_low, Rcount, Rout_low); |
twisti@4323 | 2010 | } |
twisti@4323 | 2011 | ba(done); |
twisti@4323 | 2012 | delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high |
twisti@4323 | 2013 | |
twisti@4323 | 2014 | // shift >= 32 bits, Ralt_count = Rcount-32 |
twisti@4323 | 2015 | bind(big_shift); |
twisti@4323 | 2016 | |
twisti@4323 | 2017 | sra(Rin_high, Ralt_count, Rout_low); |
twisti@4323 | 2018 | sra(Rin_high, 31, Rout_high); // sign into hi |
twisti@4323 | 2019 | |
twisti@4323 | 2020 | bind( done ); |
twisti@4323 | 2021 | } |
twisti@4323 | 2022 | |
twisti@4323 | 2023 | |
twisti@4323 | 2024 | |
twisti@4323 | 2025 | void MacroAssembler::lushr( Register Rin_high, Register Rin_low, |
twisti@4323 | 2026 | Register Rcount, |
twisti@4323 | 2027 | Register Rout_high, Register Rout_low, |
twisti@4323 | 2028 | Register Rtemp ) { |
twisti@4323 | 2029 | |
twisti@4323 | 2030 | Register Ralt_count = Rtemp; |
twisti@4323 | 2031 | Register Rxfer_bits = Rtemp; |
twisti@4323 | 2032 | |
twisti@4323 | 2033 | assert( Ralt_count != Rin_high |
twisti@4323 | 2034 | && Ralt_count != Rin_low |
twisti@4323 | 2035 | && Ralt_count != Rcount |
twisti@4323 | 2036 | && Rxfer_bits != Rin_low |
twisti@4323 | 2037 | && Rxfer_bits != Rin_high |
twisti@4323 | 2038 | && Rxfer_bits != Rcount |
twisti@4323 | 2039 | && Rxfer_bits != Rout_high |
twisti@4323 | 2040 | && Rout_high != Rin_low, |
twisti@4323 | 2041 | "register alias checks"); |
twisti@4323 | 2042 | |
twisti@4323 | 2043 | Label big_shift, done; |
twisti@4323 | 2044 | |
twisti@4323 | 2045 | // This code can be optimized to use the 64 bit shifts in V9. |
twisti@4323 | 2046 | // Here we use the 32 bit shifts. |
twisti@4323 | 2047 | |
twisti@4323 | 2048 | and3( Rcount, 0x3f, Rcount); // take least significant 6 bits |
twisti@4323 | 2049 | subcc(Rcount, 31, Ralt_count); |
twisti@4323 | 2050 | br(greater, true, pn, big_shift); |
twisti@4323 | 2051 | delayed()->dec(Ralt_count); |
twisti@4323 | 2052 | |
twisti@4323 | 2053 | // shift < 32 bits, Ralt_count = Rcount-31 |
twisti@4323 | 2054 | |
twisti@4323 | 2055 | // We get the transfer bits by shifting left by 32-count the high |
twisti@4323 | 2056 | // register. This is done by shifting left by 31-count and then by one |
twisti@4323 | 2057 | // more to take care of the special (rare) case where count is zero |
twisti@4323 | 2058 | // (shifting by 32 would not work). |
twisti@4323 | 2059 | |
twisti@4323 | 2060 | neg(Ralt_count); |
twisti@4323 | 2061 | if (Rcount != Rout_low) { |
twisti@4323 | 2062 | srl(Rin_low, Rcount, Rout_low); |
twisti@4323 | 2063 | } |
twisti@4323 | 2064 | |
twisti@4323 | 2065 | // The order of the next two instructions is critical in the case where |
twisti@4323 | 2066 | // Rin and Rout are the same and should not be reversed. |
twisti@4323 | 2067 | |
twisti@4323 | 2068 | sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count |
twisti@4323 | 2069 | srl(Rin_high, Rcount, Rout_high ); // high half |
twisti@4323 | 2070 | sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more |
twisti@4323 | 2071 | if (Rcount == Rout_low) { |
twisti@4323 | 2072 | srl(Rin_low, Rcount, Rout_low); |
twisti@4323 | 2073 | } |
twisti@4323 | 2074 | ba(done); |
twisti@4323 | 2075 | delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high |
twisti@4323 | 2076 | |
twisti@4323 | 2077 | // shift >= 32 bits, Ralt_count = Rcount-32 |
twisti@4323 | 2078 | bind(big_shift); |
twisti@4323 | 2079 | |
twisti@4323 | 2080 | srl(Rin_high, Ralt_count, Rout_low); |
twisti@4323 | 2081 | clr(Rout_high); |
twisti@4323 | 2082 | |
twisti@4323 | 2083 | bind( done ); |
twisti@4323 | 2084 | } |
twisti@4323 | 2085 | |
twisti@4323 | 2086 | #ifdef _LP64 |
twisti@4323 | 2087 | void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { |
twisti@4323 | 2088 | cmp(Ra, Rb); |
twisti@4323 | 2089 | mov(-1, Rresult); |
twisti@4323 | 2090 | movcc(equal, false, xcc, 0, Rresult); |
twisti@4323 | 2091 | movcc(greater, false, xcc, 1, Rresult); |
twisti@4323 | 2092 | } |
twisti@4323 | 2093 | #endif |
twisti@4323 | 2094 | |
twisti@4323 | 2095 | |
twisti@4323 | 2096 | void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) { |
twisti@4323 | 2097 | switch (size_in_bytes) { |
twisti@4323 | 2098 | case 8: ld_long(src, dst); break; |
twisti@4323 | 2099 | case 4: ld( src, dst); break; |
twisti@4323 | 2100 | case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break; |
twisti@4323 | 2101 | case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break; |
twisti@4323 | 2102 | default: ShouldNotReachHere(); |
twisti@4323 | 2103 | } |
twisti@4323 | 2104 | } |
twisti@4323 | 2105 | |
twisti@4323 | 2106 | void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) { |
twisti@4323 | 2107 | switch (size_in_bytes) { |
twisti@4323 | 2108 | case 8: st_long(src, dst); break; |
twisti@4323 | 2109 | case 4: st( src, dst); break; |
twisti@4323 | 2110 | case 2: sth( src, dst); break; |
twisti@4323 | 2111 | case 1: stb( src, dst); break; |
twisti@4323 | 2112 | default: ShouldNotReachHere(); |
twisti@4323 | 2113 | } |
twisti@4323 | 2114 | } |
twisti@4323 | 2115 | |
twisti@4323 | 2116 | |
twisti@4323 | 2117 | void MacroAssembler::float_cmp( bool is_float, int unordered_result, |
twisti@4323 | 2118 | FloatRegister Fa, FloatRegister Fb, |
twisti@4323 | 2119 | Register Rresult) { |
twisti@4323 | 2120 | |
twisti@4323 | 2121 | fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb); |
twisti@4323 | 2122 | |
twisti@4323 | 2123 | Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less; |
twisti@4323 | 2124 | Condition eq = f_equal; |
twisti@4323 | 2125 | Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater; |
twisti@4323 | 2126 | |
twisti@4323 | 2127 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 2128 | |
twisti@4323 | 2129 | mov(-1, Rresult); |
twisti@4323 | 2130 | movcc(eq, true, fcc0, 0, Rresult); |
twisti@4323 | 2131 | movcc(gt, true, fcc0, 1, Rresult); |
twisti@4323 | 2132 | |
twisti@4323 | 2133 | } else { |
twisti@4323 | 2134 | Label done; |
twisti@4323 | 2135 | |
twisti@4323 | 2136 | set( -1, Rresult ); |
twisti@4323 | 2137 | //fb(lt, true, pn, done); delayed()->set( -1, Rresult ); |
twisti@4323 | 2138 | fb( eq, true, pn, done); delayed()->set( 0, Rresult ); |
twisti@4323 | 2139 | fb( gt, true, pn, done); delayed()->set( 1, Rresult ); |
twisti@4323 | 2140 | |
twisti@4323 | 2141 | bind (done); |
twisti@4323 | 2142 | } |
twisti@4323 | 2143 | } |
twisti@4323 | 2144 | |
twisti@4323 | 2145 | |
twisti@4323 | 2146 | void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) |
twisti@4323 | 2147 | { |
twisti@4323 | 2148 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 2149 | Assembler::fneg(w, s, d); |
twisti@4323 | 2150 | } else { |
twisti@4323 | 2151 | if (w == FloatRegisterImpl::S) { |
twisti@4323 | 2152 | Assembler::fneg(w, s, d); |
twisti@4323 | 2153 | } else if (w == FloatRegisterImpl::D) { |
twisti@4323 | 2154 | // number() does a sanity check on the alignment. |
twisti@4323 | 2155 | assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && |
twisti@4323 | 2156 | ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); |
twisti@4323 | 2157 | |
twisti@4323 | 2158 | Assembler::fneg(FloatRegisterImpl::S, s, d); |
twisti@4323 | 2159 | Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); |
twisti@4323 | 2160 | } else { |
twisti@4323 | 2161 | assert(w == FloatRegisterImpl::Q, "Invalid float register width"); |
twisti@4323 | 2162 | |
twisti@4323 | 2163 | // number() does a sanity check on the alignment. |
twisti@4323 | 2164 | assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && |
twisti@4323 | 2165 | ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); |
twisti@4323 | 2166 | |
twisti@4323 | 2167 | Assembler::fneg(FloatRegisterImpl::S, s, d); |
twisti@4323 | 2168 | Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); |
twisti@4323 | 2169 | Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); |
twisti@4323 | 2170 | Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); |
twisti@4323 | 2171 | } |
twisti@4323 | 2172 | } |
twisti@4323 | 2173 | } |
twisti@4323 | 2174 | |
twisti@4323 | 2175 | void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) |
twisti@4323 | 2176 | { |
twisti@4323 | 2177 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 2178 | Assembler::fmov(w, s, d); |
twisti@4323 | 2179 | } else { |
twisti@4323 | 2180 | if (w == FloatRegisterImpl::S) { |
twisti@4323 | 2181 | Assembler::fmov(w, s, d); |
twisti@4323 | 2182 | } else if (w == FloatRegisterImpl::D) { |
twisti@4323 | 2183 | // number() does a sanity check on the alignment. |
twisti@4323 | 2184 | assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && |
twisti@4323 | 2185 | ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); |
twisti@4323 | 2186 | |
twisti@4323 | 2187 | Assembler::fmov(FloatRegisterImpl::S, s, d); |
twisti@4323 | 2188 | Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); |
twisti@4323 | 2189 | } else { |
twisti@4323 | 2190 | assert(w == FloatRegisterImpl::Q, "Invalid float register width"); |
twisti@4323 | 2191 | |
twisti@4323 | 2192 | // number() does a sanity check on the alignment. |
twisti@4323 | 2193 | assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && |
twisti@4323 | 2194 | ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); |
twisti@4323 | 2195 | |
twisti@4323 | 2196 | Assembler::fmov(FloatRegisterImpl::S, s, d); |
twisti@4323 | 2197 | Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); |
twisti@4323 | 2198 | Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); |
twisti@4323 | 2199 | Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); |
twisti@4323 | 2200 | } |
twisti@4323 | 2201 | } |
twisti@4323 | 2202 | } |
twisti@4323 | 2203 | |
twisti@4323 | 2204 | void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) |
twisti@4323 | 2205 | { |
twisti@4323 | 2206 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 2207 | Assembler::fabs(w, s, d); |
twisti@4323 | 2208 | } else { |
twisti@4323 | 2209 | if (w == FloatRegisterImpl::S) { |
twisti@4323 | 2210 | Assembler::fabs(w, s, d); |
twisti@4323 | 2211 | } else if (w == FloatRegisterImpl::D) { |
twisti@4323 | 2212 | // number() does a sanity check on the alignment. |
twisti@4323 | 2213 | assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && |
twisti@4323 | 2214 | ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); |
twisti@4323 | 2215 | |
twisti@4323 | 2216 | Assembler::fabs(FloatRegisterImpl::S, s, d); |
twisti@4323 | 2217 | Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); |
twisti@4323 | 2218 | } else { |
twisti@4323 | 2219 | assert(w == FloatRegisterImpl::Q, "Invalid float register width"); |
twisti@4323 | 2220 | |
twisti@4323 | 2221 | // number() does a sanity check on the alignment. |
twisti@4323 | 2222 | assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && |
twisti@4323 | 2223 | ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); |
twisti@4323 | 2224 | |
twisti@4323 | 2225 | Assembler::fabs(FloatRegisterImpl::S, s, d); |
twisti@4323 | 2226 | Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); |
twisti@4323 | 2227 | Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); |
twisti@4323 | 2228 | Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); |
twisti@4323 | 2229 | } |
twisti@4323 | 2230 | } |
twisti@4323 | 2231 | } |
twisti@4323 | 2232 | |
twisti@4323 | 2233 | void MacroAssembler::save_all_globals_into_locals() { |
twisti@4323 | 2234 | mov(G1,L1); |
twisti@4323 | 2235 | mov(G2,L2); |
twisti@4323 | 2236 | mov(G3,L3); |
twisti@4323 | 2237 | mov(G4,L4); |
twisti@4323 | 2238 | mov(G5,L5); |
twisti@4323 | 2239 | mov(G6,L6); |
twisti@4323 | 2240 | mov(G7,L7); |
twisti@4323 | 2241 | } |
twisti@4323 | 2242 | |
twisti@4323 | 2243 | void MacroAssembler::restore_globals_from_locals() { |
twisti@4323 | 2244 | mov(L1,G1); |
twisti@4323 | 2245 | mov(L2,G2); |
twisti@4323 | 2246 | mov(L3,G3); |
twisti@4323 | 2247 | mov(L4,G4); |
twisti@4323 | 2248 | mov(L5,G5); |
twisti@4323 | 2249 | mov(L6,G6); |
twisti@4323 | 2250 | mov(L7,G7); |
twisti@4323 | 2251 | } |
twisti@4323 | 2252 | |
twisti@4323 | 2253 | // Use for 64 bit operation. |
twisti@4323 | 2254 | void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) |
twisti@4323 | 2255 | { |
twisti@4323 | 2256 | // store ptr_reg as the new top value |
twisti@4323 | 2257 | #ifdef _LP64 |
twisti@4323 | 2258 | casx(top_ptr_reg, top_reg, ptr_reg); |
twisti@4323 | 2259 | #else |
twisti@4323 | 2260 | cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm); |
twisti@4323 | 2261 | #endif // _LP64 |
twisti@4323 | 2262 | } |
twisti@4323 | 2263 | |
twisti@4323 | 2264 | // [RGV] This routine does not handle 64 bit operations. |
twisti@4323 | 2265 | // use casx_under_lock() or casx directly!!! |
twisti@4323 | 2266 | void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) |
twisti@4323 | 2267 | { |
twisti@4323 | 2268 | // store ptr_reg as the new top value |
twisti@4323 | 2269 | if (VM_Version::v9_instructions_work()) { |
twisti@4323 | 2270 | cas(top_ptr_reg, top_reg, ptr_reg); |
twisti@4323 | 2271 | } else { |
twisti@4323 | 2272 | |
twisti@4323 | 2273 | // If the register is not an out nor global, it is not visible |
twisti@4323 | 2274 | // after the save. Allocate a register for it, save its |
twisti@4323 | 2275 | // value in the register save area (the save may not flush |
twisti@4323 | 2276 | // registers to the save area). |
twisti@4323 | 2277 | |
twisti@4323 | 2278 | Register top_ptr_reg_after_save; |
twisti@4323 | 2279 | Register top_reg_after_save; |
twisti@4323 | 2280 | Register ptr_reg_after_save; |
twisti@4323 | 2281 | |
twisti@4323 | 2282 | if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) { |
twisti@4323 | 2283 | top_ptr_reg_after_save = top_ptr_reg->after_save(); |
twisti@4323 | 2284 | } else { |
twisti@4323 | 2285 | Address reg_save_addr = top_ptr_reg->address_in_saved_window(); |
twisti@4323 | 2286 | top_ptr_reg_after_save = L0; |
twisti@4323 | 2287 | st(top_ptr_reg, reg_save_addr); |
twisti@4323 | 2288 | } |
twisti@4323 | 2289 | |
twisti@4323 | 2290 | if (top_reg->is_out() || top_reg->is_global()) { |
twisti@4323 | 2291 | top_reg_after_save = top_reg->after_save(); |
twisti@4323 | 2292 | } else { |
twisti@4323 | 2293 | Address reg_save_addr = top_reg->address_in_saved_window(); |
twisti@4323 | 2294 | top_reg_after_save = L1; |
twisti@4323 | 2295 | st(top_reg, reg_save_addr); |
twisti@4323 | 2296 | } |
twisti@4323 | 2297 | |
twisti@4323 | 2298 | if (ptr_reg->is_out() || ptr_reg->is_global()) { |
twisti@4323 | 2299 | ptr_reg_after_save = ptr_reg->after_save(); |
twisti@4323 | 2300 | } else { |
twisti@4323 | 2301 | Address reg_save_addr = ptr_reg->address_in_saved_window(); |
twisti@4323 | 2302 | ptr_reg_after_save = L2; |
twisti@4323 | 2303 | st(ptr_reg, reg_save_addr); |
twisti@4323 | 2304 | } |
twisti@4323 | 2305 | |
twisti@4323 | 2306 | const Register& lock_reg = L3; |
twisti@4323 | 2307 | const Register& lock_ptr_reg = L4; |
twisti@4323 | 2308 | const Register& value_reg = L5; |
twisti@4323 | 2309 | const Register& yield_reg = L6; |
twisti@4323 | 2310 | const Register& yieldall_reg = L7; |
twisti@4323 | 2311 | |
twisti@4323 | 2312 | save_frame(); |
twisti@4323 | 2313 | |
twisti@4323 | 2314 | if (top_ptr_reg_after_save == L0) { |
twisti@4323 | 2315 | ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save); |
twisti@4323 | 2316 | } |
twisti@4323 | 2317 | |
twisti@4323 | 2318 | if (top_reg_after_save == L1) { |
twisti@4323 | 2319 | ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save); |
twisti@4323 | 2320 | } |
twisti@4323 | 2321 | |
twisti@4323 | 2322 | if (ptr_reg_after_save == L2) { |
twisti@4323 | 2323 | ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save); |
twisti@4323 | 2324 | } |
twisti@4323 | 2325 | |
twisti@4323 | 2326 | Label(retry_get_lock); |
twisti@4323 | 2327 | Label(not_same); |
twisti@4323 | 2328 | Label(dont_yield); |
twisti@4323 | 2329 | |
twisti@4323 | 2330 | assert(lock_addr, "lock_address should be non null for v8"); |
twisti@4323 | 2331 | set((intptr_t)lock_addr, lock_ptr_reg); |
twisti@4323 | 2332 | // Initialize yield counter |
twisti@4323 | 2333 | mov(G0,yield_reg); |
twisti@4323 | 2334 | mov(G0, yieldall_reg); |
twisti@4323 | 2335 | set(StubRoutines::Sparc::locked, lock_reg); |
twisti@4323 | 2336 | |
twisti@4323 | 2337 | bind(retry_get_lock); |
twisti@4323 | 2338 | cmp_and_br_short(yield_reg, V8AtomicOperationUnderLockSpinCount, Assembler::less, Assembler::pt, dont_yield); |
twisti@4323 | 2339 | |
twisti@4323 | 2340 | if(use_call_vm) { |
twisti@4323 | 2341 | Untested("Need to verify global reg consistancy"); |
twisti@4323 | 2342 | call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg); |
twisti@4323 | 2343 | } else { |
twisti@4323 | 2344 | // Save the regs and make space for a C call |
twisti@4323 | 2345 | save(SP, -96, SP); |
twisti@4323 | 2346 | save_all_globals_into_locals(); |
twisti@4323 | 2347 | call(CAST_FROM_FN_PTR(address,os::yield_all)); |
twisti@4323 | 2348 | delayed()->mov(yieldall_reg, O0); |
twisti@4323 | 2349 | restore_globals_from_locals(); |
twisti@4323 | 2350 | restore(); |
twisti@4323 | 2351 | } |
twisti@4323 | 2352 | |
twisti@4323 | 2353 | // reset the counter |
twisti@4323 | 2354 | mov(G0,yield_reg); |
twisti@4323 | 2355 | add(yieldall_reg, 1, yieldall_reg); |
twisti@4323 | 2356 | |
twisti@4323 | 2357 | bind(dont_yield); |
twisti@4323 | 2358 | // try to get lock |
twisti@4323 | 2359 | Assembler::swap(lock_ptr_reg, 0, lock_reg); |
twisti@4323 | 2360 | |
twisti@4323 | 2361 | // did we get the lock? |
twisti@4323 | 2362 | cmp(lock_reg, StubRoutines::Sparc::unlocked); |
twisti@4323 | 2363 | br(Assembler::notEqual, true, Assembler::pn, retry_get_lock); |
twisti@4323 | 2364 | delayed()->add(yield_reg,1,yield_reg); |
twisti@4323 | 2365 | |
twisti@4323 | 2366 | // yes, got lock. do we have the same top? |
twisti@4323 | 2367 | ld(top_ptr_reg_after_save, 0, value_reg); |
twisti@4323 | 2368 | cmp_and_br_short(value_reg, top_reg_after_save, Assembler::notEqual, Assembler::pn, not_same); |
twisti@4323 | 2369 | |
twisti@4323 | 2370 | // yes, same top. |
twisti@4323 | 2371 | st(ptr_reg_after_save, top_ptr_reg_after_save, 0); |
twisti@4323 | 2372 | membar(Assembler::StoreStore); |
twisti@4323 | 2373 | |
twisti@4323 | 2374 | bind(not_same); |
twisti@4323 | 2375 | mov(value_reg, ptr_reg_after_save); |
twisti@4323 | 2376 | st(lock_reg, lock_ptr_reg, 0); // unlock |
twisti@4323 | 2377 | |
twisti@4323 | 2378 | restore(); |
twisti@4323 | 2379 | } |
twisti@4323 | 2380 | } |
twisti@4323 | 2381 | |
twisti@4323 | 2382 | RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
twisti@4323 | 2383 | Register tmp, |
twisti@4323 | 2384 | int offset) { |
twisti@4323 | 2385 | intptr_t value = *delayed_value_addr; |
twisti@4323 | 2386 | if (value != 0) |
twisti@4323 | 2387 | return RegisterOrConstant(value + offset); |
twisti@4323 | 2388 | |
twisti@4323 | 2389 | // load indirectly to solve generation ordering problem |
twisti@4323 | 2390 | AddressLiteral a(delayed_value_addr); |
twisti@4323 | 2391 | load_ptr_contents(a, tmp); |
twisti@4323 | 2392 | |
twisti@4323 | 2393 | #ifdef ASSERT |
twisti@4323 | 2394 | tst(tmp); |
twisti@4323 | 2395 | breakpoint_trap(zero, xcc); |
twisti@4323 | 2396 | #endif |
twisti@4323 | 2397 | |
twisti@4323 | 2398 | if (offset != 0) |
twisti@4323 | 2399 | add(tmp, offset, tmp); |
twisti@4323 | 2400 | |
twisti@4323 | 2401 | return RegisterOrConstant(tmp); |
twisti@4323 | 2402 | } |
twisti@4323 | 2403 | |
twisti@4323 | 2404 | |
twisti@4323 | 2405 | RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { |
twisti@4323 | 2406 | assert(d.register_or_noreg() != G0, "lost side effect"); |
twisti@4323 | 2407 | if ((s2.is_constant() && s2.as_constant() == 0) || |
twisti@4323 | 2408 | (s2.is_register() && s2.as_register() == G0)) { |
twisti@4323 | 2409 | // Do nothing, just move value. |
twisti@4323 | 2410 | if (s1.is_register()) { |
twisti@4323 | 2411 | if (d.is_constant()) d = temp; |
twisti@4323 | 2412 | mov(s1.as_register(), d.as_register()); |
twisti@4323 | 2413 | return d; |
twisti@4323 | 2414 | } else { |
twisti@4323 | 2415 | return s1; |
twisti@4323 | 2416 | } |
twisti@4323 | 2417 | } |
twisti@4323 | 2418 | |
twisti@4323 | 2419 | if (s1.is_register()) { |
twisti@4323 | 2420 | assert_different_registers(s1.as_register(), temp); |
twisti@4323 | 2421 | if (d.is_constant()) d = temp; |
twisti@4323 | 2422 | andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); |
twisti@4323 | 2423 | return d; |
twisti@4323 | 2424 | } else { |
twisti@4323 | 2425 | if (s2.is_register()) { |
twisti@4323 | 2426 | assert_different_registers(s2.as_register(), temp); |
twisti@4323 | 2427 | if (d.is_constant()) d = temp; |
twisti@4323 | 2428 | set(s1.as_constant(), temp); |
twisti@4323 | 2429 | andn(temp, s2.as_register(), d.as_register()); |
twisti@4323 | 2430 | return d; |
twisti@4323 | 2431 | } else { |
twisti@4323 | 2432 | intptr_t res = s1.as_constant() & ~s2.as_constant(); |
twisti@4323 | 2433 | return res; |
twisti@4323 | 2434 | } |
twisti@4323 | 2435 | } |
twisti@4323 | 2436 | } |
twisti@4323 | 2437 | |
twisti@4323 | 2438 | RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { |
twisti@4323 | 2439 | assert(d.register_or_noreg() != G0, "lost side effect"); |
twisti@4323 | 2440 | if ((s2.is_constant() && s2.as_constant() == 0) || |
twisti@4323 | 2441 | (s2.is_register() && s2.as_register() == G0)) { |
twisti@4323 | 2442 | // Do nothing, just move value. |
twisti@4323 | 2443 | if (s1.is_register()) { |
twisti@4323 | 2444 | if (d.is_constant()) d = temp; |
twisti@4323 | 2445 | mov(s1.as_register(), d.as_register()); |
twisti@4323 | 2446 | return d; |
twisti@4323 | 2447 | } else { |
twisti@4323 | 2448 | return s1; |
twisti@4323 | 2449 | } |
twisti@4323 | 2450 | } |
twisti@4323 | 2451 | |
twisti@4323 | 2452 | if (s1.is_register()) { |
twisti@4323 | 2453 | assert_different_registers(s1.as_register(), temp); |
twisti@4323 | 2454 | if (d.is_constant()) d = temp; |
twisti@4323 | 2455 | add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); |
twisti@4323 | 2456 | return d; |
twisti@4323 | 2457 | } else { |
twisti@4323 | 2458 | if (s2.is_register()) { |
twisti@4323 | 2459 | assert_different_registers(s2.as_register(), temp); |
twisti@4323 | 2460 | if (d.is_constant()) d = temp; |
twisti@4323 | 2461 | add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register()); |
twisti@4323 | 2462 | return d; |
twisti@4323 | 2463 | } else { |
twisti@4323 | 2464 | intptr_t res = s1.as_constant() + s2.as_constant(); |
twisti@4323 | 2465 | return res; |
twisti@4323 | 2466 | } |
twisti@4323 | 2467 | } |
twisti@4323 | 2468 | } |
twisti@4323 | 2469 | |
twisti@4323 | 2470 | RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { |
twisti@4323 | 2471 | assert(d.register_or_noreg() != G0, "lost side effect"); |
twisti@4323 | 2472 | if (!is_simm13(s2.constant_or_zero())) |
twisti@4323 | 2473 | s2 = (s2.as_constant() & 0xFF); |
twisti@4323 | 2474 | if ((s2.is_constant() && s2.as_constant() == 0) || |
twisti@4323 | 2475 | (s2.is_register() && s2.as_register() == G0)) { |
twisti@4323 | 2476 | // Do nothing, just move value. |
twisti@4323 | 2477 | if (s1.is_register()) { |
twisti@4323 | 2478 | if (d.is_constant()) d = temp; |
twisti@4323 | 2479 | mov(s1.as_register(), d.as_register()); |
twisti@4323 | 2480 | return d; |
twisti@4323 | 2481 | } else { |
twisti@4323 | 2482 | return s1; |
twisti@4323 | 2483 | } |
twisti@4323 | 2484 | } |
twisti@4323 | 2485 | |
twisti@4323 | 2486 | if (s1.is_register()) { |
twisti@4323 | 2487 | assert_different_registers(s1.as_register(), temp); |
twisti@4323 | 2488 | if (d.is_constant()) d = temp; |
twisti@4323 | 2489 | sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); |
twisti@4323 | 2490 | return d; |
twisti@4323 | 2491 | } else { |
twisti@4323 | 2492 | if (s2.is_register()) { |
twisti@4323 | 2493 | assert_different_registers(s2.as_register(), temp); |
twisti@4323 | 2494 | if (d.is_constant()) d = temp; |
twisti@4323 | 2495 | set(s1.as_constant(), temp); |
twisti@4323 | 2496 | sll_ptr(temp, s2.as_register(), d.as_register()); |
twisti@4323 | 2497 | return d; |
twisti@4323 | 2498 | } else { |
twisti@4323 | 2499 | intptr_t res = s1.as_constant() << s2.as_constant(); |
twisti@4323 | 2500 | return res; |
twisti@4323 | 2501 | } |
twisti@4323 | 2502 | } |
twisti@4323 | 2503 | } |
twisti@4323 | 2504 | |
twisti@4323 | 2505 | |
twisti@4323 | 2506 | // Look up the method for a megamorphic invokeinterface call. |
twisti@4323 | 2507 | // The target method is determined by <intf_klass, itable_index>. |
twisti@4323 | 2508 | // The receiver klass is in recv_klass. |
twisti@4323 | 2509 | // On success, the result will be in method_result, and execution falls through. |
twisti@4323 | 2510 | // On failure, execution transfers to the given label. |
twisti@4323 | 2511 | void MacroAssembler::lookup_interface_method(Register recv_klass, |
twisti@4323 | 2512 | Register intf_klass, |
twisti@4323 | 2513 | RegisterOrConstant itable_index, |
twisti@4323 | 2514 | Register method_result, |
twisti@4323 | 2515 | Register scan_temp, |
twisti@4323 | 2516 | Register sethi_temp, |
twisti@4323 | 2517 | Label& L_no_such_interface) { |
twisti@4323 | 2518 | assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
twisti@4323 | 2519 | assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
twisti@4323 | 2520 | "caller must use same register for non-constant itable index as for method"); |
twisti@4323 | 2521 | |
twisti@4323 | 2522 | Label L_no_such_interface_restore; |
twisti@4323 | 2523 | bool did_save = false; |
twisti@4323 | 2524 | if (scan_temp == noreg || sethi_temp == noreg) { |
twisti@4323 | 2525 | Register recv_2 = recv_klass->is_global() ? recv_klass : L0; |
twisti@4323 | 2526 | Register intf_2 = intf_klass->is_global() ? intf_klass : L1; |
twisti@4323 | 2527 | assert(method_result->is_global(), "must be able to return value"); |
twisti@4323 | 2528 | scan_temp = L2; |
twisti@4323 | 2529 | sethi_temp = L3; |
twisti@4323 | 2530 | save_frame_and_mov(0, recv_klass, recv_2, intf_klass, intf_2); |
twisti@4323 | 2531 | recv_klass = recv_2; |
twisti@4323 | 2532 | intf_klass = intf_2; |
twisti@4323 | 2533 | did_save = true; |
twisti@4323 | 2534 | } |
twisti@4323 | 2535 | |
twisti@4323 | 2536 | // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
twisti@4323 | 2537 | int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; |
twisti@4323 | 2538 | int scan_step = itableOffsetEntry::size() * wordSize; |
twisti@4323 | 2539 | int vte_size = vtableEntry::size() * wordSize; |
twisti@4323 | 2540 | |
twisti@4323 | 2541 | lduw(recv_klass, InstanceKlass::vtable_length_offset() * wordSize, scan_temp); |
twisti@4323 | 2542 | // %%% We should store the aligned, prescaled offset in the klassoop. |
twisti@4323 | 2543 | // Then the next several instructions would fold away. |
twisti@4323 | 2544 | |
twisti@4323 | 2545 | int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0); |
twisti@4323 | 2546 | int itb_offset = vtable_base; |
twisti@4323 | 2547 | if (round_to_unit != 0) { |
twisti@4323 | 2548 | // hoist first instruction of round_to(scan_temp, BytesPerLong): |
twisti@4323 | 2549 | itb_offset += round_to_unit - wordSize; |
twisti@4323 | 2550 | } |
twisti@4323 | 2551 | int itb_scale = exact_log2(vtableEntry::size() * wordSize); |
twisti@4323 | 2552 | sll(scan_temp, itb_scale, scan_temp); |
twisti@4323 | 2553 | add(scan_temp, itb_offset, scan_temp); |
twisti@4323 | 2554 | if (round_to_unit != 0) { |
twisti@4323 | 2555 | // Round up to align_object_offset boundary |
twisti@4323 | 2556 | // see code for InstanceKlass::start_of_itable! |
twisti@4323 | 2557 | // Was: round_to(scan_temp, BytesPerLong); |
twisti@4323 | 2558 | // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp); |
twisti@4323 | 2559 | and3(scan_temp, -round_to_unit, scan_temp); |
twisti@4323 | 2560 | } |
twisti@4323 | 2561 | add(recv_klass, scan_temp, scan_temp); |
twisti@4323 | 2562 | |
twisti@4323 | 2563 | // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
twisti@4323 | 2564 | RegisterOrConstant itable_offset = itable_index; |
twisti@4323 | 2565 | itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset); |
twisti@4323 | 2566 | itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset); |
twisti@4323 | 2567 | add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass); |
twisti@4323 | 2568 | |
twisti@4323 | 2569 | // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
twisti@4323 | 2570 | // if (scan->interface() == intf) { |
twisti@4323 | 2571 | // result = (klass + scan->offset() + itable_index); |
twisti@4323 | 2572 | // } |
twisti@4323 | 2573 | // } |
twisti@4323 | 2574 | Label L_search, L_found_method; |
twisti@4323 | 2575 | |
twisti@4323 | 2576 | for (int peel = 1; peel >= 0; peel--) { |
twisti@4323 | 2577 | // %%%% Could load both offset and interface in one ldx, if they were |
twisti@4323 | 2578 | // in the opposite order. This would save a load. |
twisti@4323 | 2579 | ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result); |
twisti@4323 | 2580 | |
twisti@4323 | 2581 | // Check that this entry is non-null. A null entry means that |
twisti@4323 | 2582 | // the receiver class doesn't implement the interface, and wasn't the |
twisti@4323 | 2583 | // same as when the caller was compiled. |
twisti@4323 | 2584 | bpr(Assembler::rc_z, false, Assembler::pn, method_result, did_save ? L_no_such_interface_restore : L_no_such_interface); |
twisti@4323 | 2585 | delayed()->cmp(method_result, intf_klass); |
twisti@4323 | 2586 | |
twisti@4323 | 2587 | if (peel) { |
twisti@4323 | 2588 | brx(Assembler::equal, false, Assembler::pt, L_found_method); |
twisti@4323 | 2589 | } else { |
twisti@4323 | 2590 | brx(Assembler::notEqual, false, Assembler::pn, L_search); |
twisti@4323 | 2591 | // (invert the test to fall through to found_method...) |
twisti@4323 | 2592 | } |
twisti@4323 | 2593 | delayed()->add(scan_temp, scan_step, scan_temp); |
twisti@4323 | 2594 | |
twisti@4323 | 2595 | if (!peel) break; |
twisti@4323 | 2596 | |
twisti@4323 | 2597 | bind(L_search); |
twisti@4323 | 2598 | } |
twisti@4323 | 2599 | |
twisti@4323 | 2600 | bind(L_found_method); |
twisti@4323 | 2601 | |
twisti@4323 | 2602 | // Got a hit. |
twisti@4323 | 2603 | int ito_offset = itableOffsetEntry::offset_offset_in_bytes(); |
twisti@4323 | 2604 | // scan_temp[-scan_step] points to the vtable offset we need |
twisti@4323 | 2605 | ito_offset -= scan_step; |
twisti@4323 | 2606 | lduw(scan_temp, ito_offset, scan_temp); |
twisti@4323 | 2607 | ld_ptr(recv_klass, scan_temp, method_result); |
twisti@4323 | 2608 | |
twisti@4323 | 2609 | if (did_save) { |
twisti@4323 | 2610 | Label L_done; |
twisti@4323 | 2611 | ba(L_done); |
twisti@4323 | 2612 | delayed()->restore(); |
twisti@4323 | 2613 | |
twisti@4323 | 2614 | bind(L_no_such_interface_restore); |
twisti@4323 | 2615 | ba(L_no_such_interface); |
twisti@4323 | 2616 | delayed()->restore(); |
twisti@4323 | 2617 | |
twisti@4323 | 2618 | bind(L_done); |
twisti@4323 | 2619 | } |
twisti@4323 | 2620 | } |
twisti@4323 | 2621 | |
twisti@4323 | 2622 | |
twisti@4323 | 2623 | // virtual method calling |
twisti@4323 | 2624 | void MacroAssembler::lookup_virtual_method(Register recv_klass, |
twisti@4323 | 2625 | RegisterOrConstant vtable_index, |
twisti@4323 | 2626 | Register method_result) { |
twisti@4323 | 2627 | assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg()); |
twisti@4323 | 2628 | Register sethi_temp = method_result; |
twisti@4323 | 2629 | const int base = (InstanceKlass::vtable_start_offset() * wordSize + |
twisti@4323 | 2630 | // method pointer offset within the vtable entry: |
twisti@4323 | 2631 | vtableEntry::method_offset_in_bytes()); |
twisti@4323 | 2632 | RegisterOrConstant vtable_offset = vtable_index; |
twisti@4323 | 2633 | // Each of the following three lines potentially generates an instruction. |
twisti@4323 | 2634 | // But the total number of address formation instructions will always be |
twisti@4323 | 2635 | // at most two, and will often be zero. In any case, it will be optimal. |
twisti@4323 | 2636 | // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x). |
twisti@4323 | 2637 | // If vtable_index is a constant, we will have at most (set B+X<<N,t; ld_ptr k,t). |
twisti@4323 | 2638 | vtable_offset = regcon_sll_ptr(vtable_index, exact_log2(vtableEntry::size() * wordSize), vtable_offset); |
twisti@4323 | 2639 | vtable_offset = regcon_inc_ptr(vtable_offset, base, vtable_offset, sethi_temp); |
twisti@4323 | 2640 | Address vtable_entry_addr(recv_klass, ensure_simm13_or_reg(vtable_offset, sethi_temp)); |
twisti@4323 | 2641 | ld_ptr(vtable_entry_addr, method_result); |
twisti@4323 | 2642 | } |
twisti@4323 | 2643 | |
twisti@4323 | 2644 | |
twisti@4323 | 2645 | void MacroAssembler::check_klass_subtype(Register sub_klass, |
twisti@4323 | 2646 | Register super_klass, |
twisti@4323 | 2647 | Register temp_reg, |
twisti@4323 | 2648 | Register temp2_reg, |
twisti@4323 | 2649 | Label& L_success) { |
twisti@4323 | 2650 | Register sub_2 = sub_klass; |
twisti@4323 | 2651 | Register sup_2 = super_klass; |
twisti@4323 | 2652 | if (!sub_2->is_global()) sub_2 = L0; |
twisti@4323 | 2653 | if (!sup_2->is_global()) sup_2 = L1; |
twisti@4323 | 2654 | bool did_save = false; |
twisti@4323 | 2655 | if (temp_reg == noreg || temp2_reg == noreg) { |
twisti@4323 | 2656 | temp_reg = L2; |
twisti@4323 | 2657 | temp2_reg = L3; |
twisti@4323 | 2658 | save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); |
twisti@4323 | 2659 | sub_klass = sub_2; |
twisti@4323 | 2660 | super_klass = sup_2; |
twisti@4323 | 2661 | did_save = true; |
twisti@4323 | 2662 | } |
twisti@4323 | 2663 | Label L_failure, L_pop_to_failure, L_pop_to_success; |
twisti@4323 | 2664 | check_klass_subtype_fast_path(sub_klass, super_klass, |
twisti@4323 | 2665 | temp_reg, temp2_reg, |
twisti@4323 | 2666 | (did_save ? &L_pop_to_success : &L_success), |
twisti@4323 | 2667 | (did_save ? &L_pop_to_failure : &L_failure), NULL); |
twisti@4323 | 2668 | |
twisti@4323 | 2669 | if (!did_save) |
twisti@4323 | 2670 | save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); |
twisti@4323 | 2671 | check_klass_subtype_slow_path(sub_2, sup_2, |
twisti@4323 | 2672 | L2, L3, L4, L5, |
twisti@4323 | 2673 | NULL, &L_pop_to_failure); |
twisti@4323 | 2674 | |
twisti@4323 | 2675 | // on success: |
twisti@4323 | 2676 | bind(L_pop_to_success); |
twisti@4323 | 2677 | restore(); |
twisti@4323 | 2678 | ba_short(L_success); |
twisti@4323 | 2679 | |
twisti@4323 | 2680 | // on failure: |
twisti@4323 | 2681 | bind(L_pop_to_failure); |
twisti@4323 | 2682 | restore(); |
twisti@4323 | 2683 | bind(L_failure); |
twisti@4323 | 2684 | } |
twisti@4323 | 2685 | |
twisti@4323 | 2686 | |
twisti@4323 | 2687 | void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
twisti@4323 | 2688 | Register super_klass, |
twisti@4323 | 2689 | Register temp_reg, |
twisti@4323 | 2690 | Register temp2_reg, |
twisti@4323 | 2691 | Label* L_success, |
twisti@4323 | 2692 | Label* L_failure, |
twisti@4323 | 2693 | Label* L_slow_path, |
twisti@4323 | 2694 | RegisterOrConstant super_check_offset) { |
twisti@4323 | 2695 | int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
twisti@4323 | 2696 | int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
twisti@4323 | 2697 | |
twisti@4323 | 2698 | bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
twisti@4323 | 2699 | bool need_slow_path = (must_load_sco || |
twisti@4323 | 2700 | super_check_offset.constant_or_zero() == sco_offset); |
twisti@4323 | 2701 | |
twisti@4323 | 2702 | assert_different_registers(sub_klass, super_klass, temp_reg); |
twisti@4323 | 2703 | if (super_check_offset.is_register()) { |
twisti@4323 | 2704 | assert_different_registers(sub_klass, super_klass, temp_reg, |
twisti@4323 | 2705 | super_check_offset.as_register()); |
twisti@4323 | 2706 | } else if (must_load_sco) { |
twisti@4323 | 2707 | assert(temp2_reg != noreg, "supply either a temp or a register offset"); |
twisti@4323 | 2708 | } |
twisti@4323 | 2709 | |
twisti@4323 | 2710 | Label L_fallthrough; |
twisti@4323 | 2711 | int label_nulls = 0; |
twisti@4323 | 2712 | if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
twisti@4323 | 2713 | if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
twisti@4323 | 2714 | if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
twisti@4323 | 2715 | assert(label_nulls <= 1 || |
twisti@4323 | 2716 | (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path), |
twisti@4323 | 2717 | "at most one NULL in the batch, usually"); |
twisti@4323 | 2718 | |
twisti@4323 | 2719 | // If the pointers are equal, we are done (e.g., String[] elements). |
twisti@4323 | 2720 | // This self-check enables sharing of secondary supertype arrays among |
twisti@4323 | 2721 | // non-primary types such as array-of-interface. Otherwise, each such |
twisti@4323 | 2722 | // type would need its own customized SSA. |
twisti@4323 | 2723 | // We move this check to the front of the fast path because many |
twisti@4323 | 2724 | // type checks are in fact trivially successful in this manner, |
twisti@4323 | 2725 | // so we get a nicely predicted branch right at the start of the check. |
twisti@4323 | 2726 | cmp(super_klass, sub_klass); |
twisti@4323 | 2727 | brx(Assembler::equal, false, Assembler::pn, *L_success); |
twisti@4323 | 2728 | delayed()->nop(); |
twisti@4323 | 2729 | |
twisti@4323 | 2730 | // Check the supertype display: |
twisti@4323 | 2731 | if (must_load_sco) { |
twisti@4323 | 2732 | // The super check offset is always positive... |
twisti@4323 | 2733 | lduw(super_klass, sco_offset, temp2_reg); |
twisti@4323 | 2734 | super_check_offset = RegisterOrConstant(temp2_reg); |
twisti@4323 | 2735 | // super_check_offset is register. |
twisti@4323 | 2736 | assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register()); |
twisti@4323 | 2737 | } |
twisti@4323 | 2738 | ld_ptr(sub_klass, super_check_offset, temp_reg); |
twisti@4323 | 2739 | cmp(super_klass, temp_reg); |
twisti@4323 | 2740 | |
twisti@4323 | 2741 | // This check has worked decisively for primary supers. |
twisti@4323 | 2742 | // Secondary supers are sought in the super_cache ('super_cache_addr'). |
twisti@4323 | 2743 | // (Secondary supers are interfaces and very deeply nested subtypes.) |
twisti@4323 | 2744 | // This works in the same check above because of a tricky aliasing |
twisti@4323 | 2745 | // between the super_cache and the primary super display elements. |
twisti@4323 | 2746 | // (The 'super_check_addr' can address either, as the case requires.) |
twisti@4323 | 2747 | // Note that the cache is updated below if it does not help us find |
twisti@4323 | 2748 | // what we need immediately. |
twisti@4323 | 2749 | // So if it was a primary super, we can just fail immediately. |
twisti@4323 | 2750 | // Otherwise, it's the slow path for us (no success at this point). |
twisti@4323 | 2751 | |
twisti@4323 | 2752 | // Hacked ba(), which may only be used just before L_fallthrough. |
twisti@4323 | 2753 | #define FINAL_JUMP(label) \ |
twisti@4323 | 2754 | if (&(label) != &L_fallthrough) { \ |
twisti@4323 | 2755 | ba(label); delayed()->nop(); \ |
twisti@4323 | 2756 | } |
twisti@4323 | 2757 | |
twisti@4323 | 2758 | if (super_check_offset.is_register()) { |
twisti@4323 | 2759 | brx(Assembler::equal, false, Assembler::pn, *L_success); |
twisti@4323 | 2760 | delayed()->cmp(super_check_offset.as_register(), sc_offset); |
twisti@4323 | 2761 | |
twisti@4323 | 2762 | if (L_failure == &L_fallthrough) { |
twisti@4323 | 2763 | brx(Assembler::equal, false, Assembler::pt, *L_slow_path); |
twisti@4323 | 2764 | delayed()->nop(); |
twisti@4323 | 2765 | } else { |
twisti@4323 | 2766 | brx(Assembler::notEqual, false, Assembler::pn, *L_failure); |
twisti@4323 | 2767 | delayed()->nop(); |
twisti@4323 | 2768 | FINAL_JUMP(*L_slow_path); |
twisti@4323 | 2769 | } |
twisti@4323 | 2770 | } else if (super_check_offset.as_constant() == sc_offset) { |
twisti@4323 | 2771 | // Need a slow path; fast failure is impossible. |
twisti@4323 | 2772 | if (L_slow_path == &L_fallthrough) { |
twisti@4323 | 2773 | brx(Assembler::equal, false, Assembler::pt, *L_success); |
twisti@4323 | 2774 | delayed()->nop(); |
twisti@4323 | 2775 | } else { |
twisti@4323 | 2776 | brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path); |
twisti@4323 | 2777 | delayed()->nop(); |
twisti@4323 | 2778 | FINAL_JUMP(*L_success); |
twisti@4323 | 2779 | } |
twisti@4323 | 2780 | } else { |
twisti@4323 | 2781 | // No slow path; it's a fast decision. |
twisti@4323 | 2782 | if (L_failure == &L_fallthrough) { |
twisti@4323 | 2783 | brx(Assembler::equal, false, Assembler::pt, *L_success); |
twisti@4323 | 2784 | delayed()->nop(); |
twisti@4323 | 2785 | } else { |
twisti@4323 | 2786 | brx(Assembler::notEqual, false, Assembler::pn, *L_failure); |
twisti@4323 | 2787 | delayed()->nop(); |
twisti@4323 | 2788 | FINAL_JUMP(*L_success); |
twisti@4323 | 2789 | } |
twisti@4323 | 2790 | } |
twisti@4323 | 2791 | |
twisti@4323 | 2792 | bind(L_fallthrough); |
twisti@4323 | 2793 | |
twisti@4323 | 2794 | #undef FINAL_JUMP |
twisti@4323 | 2795 | } |
twisti@4323 | 2796 | |
twisti@4323 | 2797 | |
twisti@4323 | 2798 | void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
twisti@4323 | 2799 | Register super_klass, |
twisti@4323 | 2800 | Register count_temp, |
twisti@4323 | 2801 | Register scan_temp, |
twisti@4323 | 2802 | Register scratch_reg, |
twisti@4323 | 2803 | Register coop_reg, |
twisti@4323 | 2804 | Label* L_success, |
twisti@4323 | 2805 | Label* L_failure) { |
twisti@4323 | 2806 | assert_different_registers(sub_klass, super_klass, |
twisti@4323 | 2807 | count_temp, scan_temp, scratch_reg, coop_reg); |
twisti@4323 | 2808 | |
twisti@4323 | 2809 | Label L_fallthrough, L_loop; |
twisti@4323 | 2810 | int label_nulls = 0; |
twisti@4323 | 2811 | if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
twisti@4323 | 2812 | if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
twisti@4323 | 2813 | assert(label_nulls <= 1, "at most one NULL in the batch"); |
twisti@4323 | 2814 | |
twisti@4323 | 2815 | // a couple of useful fields in sub_klass: |
twisti@4323 | 2816 | int ss_offset = in_bytes(Klass::secondary_supers_offset()); |
twisti@4323 | 2817 | int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
twisti@4323 | 2818 | |
twisti@4323 | 2819 | // Do a linear scan of the secondary super-klass chain. |
twisti@4323 | 2820 | // This code is rarely used, so simplicity is a virtue here. |
twisti@4323 | 2821 | |
twisti@4323 | 2822 | #ifndef PRODUCT |
twisti@4323 | 2823 | int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
twisti@4323 | 2824 | inc_counter((address) pst_counter, count_temp, scan_temp); |
twisti@4323 | 2825 | #endif |
twisti@4323 | 2826 | |
twisti@4323 | 2827 | // We will consult the secondary-super array. |
twisti@4323 | 2828 | ld_ptr(sub_klass, ss_offset, scan_temp); |
twisti@4323 | 2829 | |
twisti@4323 | 2830 | Register search_key = super_klass; |
twisti@4323 | 2831 | |
twisti@4323 | 2832 | // Load the array length. (Positive movl does right thing on LP64.) |
twisti@4323 | 2833 | lduw(scan_temp, Array<Klass*>::length_offset_in_bytes(), count_temp); |
twisti@4323 | 2834 | |
twisti@4323 | 2835 | // Check for empty secondary super list |
twisti@4323 | 2836 | tst(count_temp); |
twisti@4323 | 2837 | |
twisti@4323 | 2838 | // In the array of super classes elements are pointer sized. |
twisti@4323 | 2839 | int element_size = wordSize; |
twisti@4323 | 2840 | |
twisti@4323 | 2841 | // Top of search loop |
twisti@4323 | 2842 | bind(L_loop); |
twisti@4323 | 2843 | br(Assembler::equal, false, Assembler::pn, *L_failure); |
twisti@4323 | 2844 | delayed()->add(scan_temp, element_size, scan_temp); |
twisti@4323 | 2845 | |
twisti@4323 | 2846 | // Skip the array header in all array accesses. |
twisti@4323 | 2847 | int elem_offset = Array<Klass*>::base_offset_in_bytes(); |
twisti@4323 | 2848 | elem_offset -= element_size; // the scan pointer was pre-incremented also |
twisti@4323 | 2849 | |
twisti@4323 | 2850 | // Load next super to check |
twisti@4323 | 2851 | ld_ptr( scan_temp, elem_offset, scratch_reg ); |
twisti@4323 | 2852 | |
twisti@4323 | 2853 | // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list |
twisti@4323 | 2854 | cmp(scratch_reg, search_key); |
twisti@4323 | 2855 | |
twisti@4323 | 2856 | // A miss means we are NOT a subtype and need to keep looping |
twisti@4323 | 2857 | brx(Assembler::notEqual, false, Assembler::pn, L_loop); |
twisti@4323 | 2858 | delayed()->deccc(count_temp); // decrement trip counter in delay slot |
twisti@4323 | 2859 | |
twisti@4323 | 2860 | // Success. Cache the super we found and proceed in triumph. |
twisti@4323 | 2861 | st_ptr(super_klass, sub_klass, sc_offset); |
twisti@4323 | 2862 | |
twisti@4323 | 2863 | if (L_success != &L_fallthrough) { |
twisti@4323 | 2864 | ba(*L_success); |
twisti@4323 | 2865 | delayed()->nop(); |
twisti@4323 | 2866 | } |
twisti@4323 | 2867 | |
twisti@4323 | 2868 | bind(L_fallthrough); |
twisti@4323 | 2869 | } |
twisti@4323 | 2870 | |
twisti@4323 | 2871 | |
twisti@4323 | 2872 | RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot, |
twisti@4323 | 2873 | Register temp_reg, |
twisti@4323 | 2874 | int extra_slot_offset) { |
twisti@4323 | 2875 | // cf. TemplateTable::prepare_invoke(), if (load_receiver). |
twisti@4323 | 2876 | int stackElementSize = Interpreter::stackElementSize; |
twisti@4323 | 2877 | int offset = extra_slot_offset * stackElementSize; |
twisti@4323 | 2878 | if (arg_slot.is_constant()) { |
twisti@4323 | 2879 | offset += arg_slot.as_constant() * stackElementSize; |
twisti@4323 | 2880 | return offset; |
twisti@4323 | 2881 | } else { |
twisti@4323 | 2882 | assert(temp_reg != noreg, "must specify"); |
twisti@4323 | 2883 | sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg); |
twisti@4323 | 2884 | if (offset != 0) |
twisti@4323 | 2885 | add(temp_reg, offset, temp_reg); |
twisti@4323 | 2886 | return temp_reg; |
twisti@4323 | 2887 | } |
twisti@4323 | 2888 | } |
twisti@4323 | 2889 | |
twisti@4323 | 2890 | |
twisti@4323 | 2891 | Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, |
twisti@4323 | 2892 | Register temp_reg, |
twisti@4323 | 2893 | int extra_slot_offset) { |
twisti@4323 | 2894 | return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset)); |
twisti@4323 | 2895 | } |
twisti@4323 | 2896 | |
twisti@4323 | 2897 | |
twisti@4323 | 2898 | void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, |
twisti@4323 | 2899 | Register temp_reg, |
twisti@4323 | 2900 | Label& done, Label* slow_case, |
twisti@4323 | 2901 | BiasedLockingCounters* counters) { |
twisti@4323 | 2902 | assert(UseBiasedLocking, "why call this otherwise?"); |
twisti@4323 | 2903 | |
twisti@4323 | 2904 | if (PrintBiasedLockingStatistics) { |
twisti@4323 | 2905 | assert_different_registers(obj_reg, mark_reg, temp_reg, O7); |
twisti@4323 | 2906 | if (counters == NULL) |
twisti@4323 | 2907 | counters = BiasedLocking::counters(); |
twisti@4323 | 2908 | } |
twisti@4323 | 2909 | |
twisti@4323 | 2910 | Label cas_label; |
twisti@4323 | 2911 | |
twisti@4323 | 2912 | // Biased locking |
twisti@4323 | 2913 | // See whether the lock is currently biased toward our thread and |
twisti@4323 | 2914 | // whether the epoch is still valid |
twisti@4323 | 2915 | // Note that the runtime guarantees sufficient alignment of JavaThread |
twisti@4323 | 2916 | // pointers to allow age to be placed into low bits |
twisti@4323 | 2917 | assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); |
twisti@4323 | 2918 | and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); |
twisti@4323 | 2919 | cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label); |
twisti@4323 | 2920 | |
twisti@4323 | 2921 | load_klass(obj_reg, temp_reg); |
twisti@4323 | 2922 | ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); |
twisti@4323 | 2923 | or3(G2_thread, temp_reg, temp_reg); |
twisti@4323 | 2924 | xor3(mark_reg, temp_reg, temp_reg); |
twisti@4323 | 2925 | andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); |
twisti@4323 | 2926 | if (counters != NULL) { |
twisti@4323 | 2927 | cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); |
twisti@4323 | 2928 | // Reload mark_reg as we may need it later |
twisti@4323 | 2929 | ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg); |
twisti@4323 | 2930 | } |
twisti@4323 | 2931 | brx(Assembler::equal, true, Assembler::pt, done); |
twisti@4323 | 2932 | delayed()->nop(); |
twisti@4323 | 2933 | |
twisti@4323 | 2934 | Label try_revoke_bias; |
twisti@4323 | 2935 | Label try_rebias; |
twisti@4323 | 2936 | Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes()); |
twisti@4323 | 2937 | assert(mark_addr.disp() == 0, "cas must take a zero displacement"); |
twisti@4323 | 2938 | |
twisti@4323 | 2939 | // At this point we know that the header has the bias pattern and |
twisti@4323 | 2940 | // that we are not the bias owner in the current epoch. We need to |
twisti@4323 | 2941 | // figure out more details about the state of the header in order to |
twisti@4323 | 2942 | // know what operations can be legally performed on the object's |
twisti@4323 | 2943 | // header. |
twisti@4323 | 2944 | |
twisti@4323 | 2945 | // If the low three bits in the xor result aren't clear, that means |
twisti@4323 | 2946 | // the prototype header is no longer biased and we have to revoke |
twisti@4323 | 2947 | // the bias on this object. |
twisti@4323 | 2948 | btst(markOopDesc::biased_lock_mask_in_place, temp_reg); |
twisti@4323 | 2949 | brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); |
twisti@4323 | 2950 | |
twisti@4323 | 2951 | // Biasing is still enabled for this data type. See whether the |
twisti@4323 | 2952 | // epoch of the current bias is still valid, meaning that the epoch |
twisti@4323 | 2953 | // bits of the mark word are equal to the epoch bits of the |
twisti@4323 | 2954 | // prototype header. (Note that the prototype header's epoch bits |
twisti@4323 | 2955 | // only change at a safepoint.) If not, attempt to rebias the object |
twisti@4323 | 2956 | // toward the current thread. Note that we must be absolutely sure |
twisti@4323 | 2957 | // that the current epoch is invalid in order to do this because |
twisti@4323 | 2958 | // otherwise the manipulations it performs on the mark word are |
twisti@4323 | 2959 | // illegal. |
twisti@4323 | 2960 | delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); |
twisti@4323 | 2961 | brx(Assembler::notZero, false, Assembler::pn, try_rebias); |
twisti@4323 | 2962 | |
twisti@4323 | 2963 | // The epoch of the current bias is still valid but we know nothing |
twisti@4323 | 2964 | // about the owner; it might be set or it might be clear. Try to |
twisti@4323 | 2965 | // acquire the bias of the object using an atomic operation. If this |
twisti@4323 | 2966 | // fails we will go in to the runtime to revoke the object's bias. |
twisti@4323 | 2967 | // Note that we first construct the presumed unbiased header so we |
twisti@4323 | 2968 | // don't accidentally blow away another thread's valid bias. |
twisti@4323 | 2969 | delayed()->and3(mark_reg, |
twisti@4323 | 2970 | markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, |
twisti@4323 | 2971 | mark_reg); |
twisti@4323 | 2972 | or3(G2_thread, mark_reg, temp_reg); |
twisti@4323 | 2973 | casn(mark_addr.base(), mark_reg, temp_reg); |
twisti@4323 | 2974 | // If the biasing toward our thread failed, this means that |
twisti@4323 | 2975 | // another thread succeeded in biasing it toward itself and we |
twisti@4323 | 2976 | // need to revoke that bias. The revocation will occur in the |
twisti@4323 | 2977 | // interpreter runtime in the slow case. |
twisti@4323 | 2978 | cmp(mark_reg, temp_reg); |
twisti@4323 | 2979 | if (counters != NULL) { |
twisti@4323 | 2980 | cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); |
twisti@4323 | 2981 | } |
twisti@4323 | 2982 | if (slow_case != NULL) { |
twisti@4323 | 2983 | brx(Assembler::notEqual, true, Assembler::pn, *slow_case); |
twisti@4323 | 2984 | delayed()->nop(); |
twisti@4323 | 2985 | } |
twisti@4323 | 2986 | ba_short(done); |
twisti@4323 | 2987 | |
twisti@4323 | 2988 | bind(try_rebias); |
twisti@4323 | 2989 | // At this point we know the epoch has expired, meaning that the |
twisti@4323 | 2990 | // current "bias owner", if any, is actually invalid. Under these |
twisti@4323 | 2991 | // circumstances _only_, we are allowed to use the current header's |
twisti@4323 | 2992 | // value as the comparison value when doing the cas to acquire the |
twisti@4323 | 2993 | // bias in the current epoch. In other words, we allow transfer of |
twisti@4323 | 2994 | // the bias from one thread to another directly in this situation. |
twisti@4323 | 2995 | // |
twisti@4323 | 2996 | // FIXME: due to a lack of registers we currently blow away the age |
twisti@4323 | 2997 | // bits in this situation. Should attempt to preserve them. |
twisti@4323 | 2998 | load_klass(obj_reg, temp_reg); |
twisti@4323 | 2999 | ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); |
twisti@4323 | 3000 | or3(G2_thread, temp_reg, temp_reg); |
twisti@4323 | 3001 | casn(mark_addr.base(), mark_reg, temp_reg); |
twisti@4323 | 3002 | // If the biasing toward our thread failed, this means that |
twisti@4323 | 3003 | // another thread succeeded in biasing it toward itself and we |
twisti@4323 | 3004 | // need to revoke that bias. The revocation will occur in the |
twisti@4323 | 3005 | // interpreter runtime in the slow case. |
twisti@4323 | 3006 | cmp(mark_reg, temp_reg); |
twisti@4323 | 3007 | if (counters != NULL) { |
twisti@4323 | 3008 | cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); |
twisti@4323 | 3009 | } |
twisti@4323 | 3010 | if (slow_case != NULL) { |
twisti@4323 | 3011 | brx(Assembler::notEqual, true, Assembler::pn, *slow_case); |
twisti@4323 | 3012 | delayed()->nop(); |
twisti@4323 | 3013 | } |
twisti@4323 | 3014 | ba_short(done); |
twisti@4323 | 3015 | |
twisti@4323 | 3016 | bind(try_revoke_bias); |
twisti@4323 | 3017 | // The prototype mark in the klass doesn't have the bias bit set any |
twisti@4323 | 3018 | // more, indicating that objects of this data type are not supposed |
twisti@4323 | 3019 | // to be biased any more. We are going to try to reset the mark of |
twisti@4323 | 3020 | // this object to the prototype value and fall through to the |
twisti@4323 | 3021 | // CAS-based locking scheme. Note that if our CAS fails, it means |
twisti@4323 | 3022 | // that another thread raced us for the privilege of revoking the |
twisti@4323 | 3023 | // bias of this particular object, so it's okay to continue in the |
twisti@4323 | 3024 | // normal locking code. |
twisti@4323 | 3025 | // |
twisti@4323 | 3026 | // FIXME: due to a lack of registers we currently blow away the age |
twisti@4323 | 3027 | // bits in this situation. Should attempt to preserve them. |
twisti@4323 | 3028 | load_klass(obj_reg, temp_reg); |
twisti@4323 | 3029 | ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); |
twisti@4323 | 3030 | casn(mark_addr.base(), mark_reg, temp_reg); |
twisti@4323 | 3031 | // Fall through to the normal CAS-based lock, because no matter what |
twisti@4323 | 3032 | // the result of the above CAS, some thread must have succeeded in |
twisti@4323 | 3033 | // removing the bias bit from the object's header. |
twisti@4323 | 3034 | if (counters != NULL) { |
twisti@4323 | 3035 | cmp(mark_reg, temp_reg); |
twisti@4323 | 3036 | cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); |
twisti@4323 | 3037 | } |
twisti@4323 | 3038 | |
twisti@4323 | 3039 | bind(cas_label); |
twisti@4323 | 3040 | } |
twisti@4323 | 3041 | |
twisti@4323 | 3042 | void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, |
twisti@4323 | 3043 | bool allow_delay_slot_filling) { |
twisti@4323 | 3044 | // Check for biased locking unlock case, which is a no-op |
twisti@4323 | 3045 | // Note: we do not have to check the thread ID for two reasons. |
twisti@4323 | 3046 | // First, the interpreter checks for IllegalMonitorStateException at |
twisti@4323 | 3047 | // a higher level. Second, if the bias was revoked while we held the |
twisti@4323 | 3048 | // lock, the object could not be rebiased toward another thread, so |
twisti@4323 | 3049 | // the bias bit would be clear. |
twisti@4323 | 3050 | ld_ptr(mark_addr, temp_reg); |
twisti@4323 | 3051 | and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); |
twisti@4323 | 3052 | cmp(temp_reg, markOopDesc::biased_lock_pattern); |
twisti@4323 | 3053 | brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); |
twisti@4323 | 3054 | delayed(); |
twisti@4323 | 3055 | if (!allow_delay_slot_filling) { |
twisti@4323 | 3056 | nop(); |
twisti@4323 | 3057 | } |
twisti@4323 | 3058 | } |
twisti@4323 | 3059 | |
twisti@4323 | 3060 | |
twisti@4323 | 3061 | // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by |
twisti@4323 | 3062 | // Solaris/SPARC's "as". Another apt name would be cas_ptr() |
twisti@4323 | 3063 | |
twisti@4323 | 3064 | void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) { |
twisti@4323 | 3065 | casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); |
twisti@4323 | 3066 | } |
twisti@4323 | 3067 | |
twisti@4323 | 3068 | |
twisti@4323 | 3069 | |
twisti@4323 | 3070 | // compiler_lock_object() and compiler_unlock_object() are direct transliterations |
twisti@4323 | 3071 | // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. |
twisti@4323 | 3072 | // The code could be tightened up considerably. |
twisti@4323 | 3073 | // |
twisti@4323 | 3074 | // box->dhw disposition - post-conditions at DONE_LABEL. |
twisti@4323 | 3075 | // - Successful inflated lock: box->dhw != 0. |
twisti@4323 | 3076 | // Any non-zero value suffices. |
twisti@4323 | 3077 | // Consider G2_thread, rsp, boxReg, or unused_mark() |
twisti@4323 | 3078 | // - Successful Stack-lock: box->dhw == mark. |
twisti@4323 | 3079 | // box->dhw must contain the displaced mark word value |
twisti@4323 | 3080 | // - Failure -- icc.ZFlag == 0 and box->dhw is undefined. |
twisti@4323 | 3081 | // The slow-path fast_enter() and slow_enter() operators |
twisti@4323 | 3082 | // are responsible for setting box->dhw = NonZero (typically ::unused_mark). |
twisti@4323 | 3083 | // - Biased: box->dhw is undefined |
twisti@4323 | 3084 | // |
twisti@4323 | 3085 | // SPARC refworkload performance - specifically jetstream and scimark - are |
twisti@4323 | 3086 | // extremely sensitive to the size of the code emitted by compiler_lock_object |
twisti@4323 | 3087 | // and compiler_unlock_object. Critically, the key factor is code size, not path |
twisti@4323 | 3088 | // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the |
twisti@4323 | 3089 | // effect). |
twisti@4323 | 3090 | |
twisti@4323 | 3091 | |
twisti@4323 | 3092 | void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, |
twisti@4323 | 3093 | Register Rbox, Register Rscratch, |
twisti@4323 | 3094 | BiasedLockingCounters* counters, |
twisti@4323 | 3095 | bool try_bias) { |
twisti@4323 | 3096 | Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); |
twisti@4323 | 3097 | |
twisti@4323 | 3098 | verify_oop(Roop); |
twisti@4323 | 3099 | Label done ; |
twisti@4323 | 3100 | |
twisti@4323 | 3101 | if (counters != NULL) { |
twisti@4323 | 3102 | inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); |
twisti@4323 | 3103 | } |
twisti@4323 | 3104 | |
twisti@4323 | 3105 | if (EmitSync & 1) { |
twisti@4323 | 3106 | mov(3, Rscratch); |
twisti@4323 | 3107 | st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3108 | cmp(SP, G0); |
twisti@4323 | 3109 | return ; |
twisti@4323 | 3110 | } |
twisti@4323 | 3111 | |
twisti@4323 | 3112 | if (EmitSync & 2) { |
twisti@4323 | 3113 | |
twisti@4323 | 3114 | // Fetch object's markword |
twisti@4323 | 3115 | ld_ptr(mark_addr, Rmark); |
twisti@4323 | 3116 | |
twisti@4323 | 3117 | if (try_bias) { |
twisti@4323 | 3118 | biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
twisti@4323 | 3119 | } |
twisti@4323 | 3120 | |
twisti@4323 | 3121 | // Save Rbox in Rscratch to be used for the cas operation |
twisti@4323 | 3122 | mov(Rbox, Rscratch); |
twisti@4323 | 3123 | |
twisti@4323 | 3124 | // set Rmark to markOop | markOopDesc::unlocked_value |
twisti@4323 | 3125 | or3(Rmark, markOopDesc::unlocked_value, Rmark); |
twisti@4323 | 3126 | |
twisti@4323 | 3127 | // Initialize the box. (Must happen before we update the object mark!) |
twisti@4323 | 3128 | st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3129 | |
twisti@4323 | 3130 | // compare object markOop with Rmark and if equal exchange Rscratch with object markOop |
twisti@4323 | 3131 | assert(mark_addr.disp() == 0, "cas must take a zero displacement"); |
twisti@4323 | 3132 | casx_under_lock(mark_addr.base(), Rmark, Rscratch, |
twisti@4323 | 3133 | (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); |
twisti@4323 | 3134 | |
twisti@4323 | 3135 | // if compare/exchange succeeded we found an unlocked object and we now have locked it |
twisti@4323 | 3136 | // hence we are done |
twisti@4323 | 3137 | cmp(Rmark, Rscratch); |
twisti@4323 | 3138 | #ifdef _LP64 |
twisti@4323 | 3139 | sub(Rscratch, STACK_BIAS, Rscratch); |
twisti@4323 | 3140 | #endif |
twisti@4323 | 3141 | brx(Assembler::equal, false, Assembler::pt, done); |
twisti@4323 | 3142 | delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot |
twisti@4323 | 3143 | |
twisti@4323 | 3144 | // we did not find an unlocked object so see if this is a recursive case |
twisti@4323 | 3145 | // sub(Rscratch, SP, Rscratch); |
twisti@4323 | 3146 | assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); |
twisti@4323 | 3147 | andcc(Rscratch, 0xfffff003, Rscratch); |
twisti@4323 | 3148 | st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3149 | bind (done); |
twisti@4323 | 3150 | return ; |
twisti@4323 | 3151 | } |
twisti@4323 | 3152 | |
twisti@4323 | 3153 | Label Egress ; |
twisti@4323 | 3154 | |
twisti@4323 | 3155 | if (EmitSync & 256) { |
twisti@4323 | 3156 | Label IsInflated ; |
twisti@4323 | 3157 | |
twisti@4323 | 3158 | ld_ptr(mark_addr, Rmark); // fetch obj->mark |
twisti@4323 | 3159 | // Triage: biased, stack-locked, neutral, inflated |
twisti@4323 | 3160 | if (try_bias) { |
twisti@4323 | 3161 | biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
twisti@4323 | 3162 | // Invariant: if control reaches this point in the emitted stream |
twisti@4323 | 3163 | // then Rmark has not been modified. |
twisti@4323 | 3164 | } |
twisti@4323 | 3165 | |
twisti@4323 | 3166 | // Store mark into displaced mark field in the on-stack basic-lock "box" |
twisti@4323 | 3167 | // Critically, this must happen before the CAS |
twisti@4323 | 3168 | // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. |
twisti@4323 | 3169 | st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3170 | andcc(Rmark, 2, G0); |
twisti@4323 | 3171 | brx(Assembler::notZero, false, Assembler::pn, IsInflated); |
twisti@4323 | 3172 | delayed()-> |
twisti@4323 | 3173 | |
twisti@4323 | 3174 | // Try stack-lock acquisition. |
twisti@4323 | 3175 | // Beware: the 1st instruction is in a delay slot |
twisti@4323 | 3176 | mov(Rbox, Rscratch); |
twisti@4323 | 3177 | or3(Rmark, markOopDesc::unlocked_value, Rmark); |
twisti@4323 | 3178 | assert(mark_addr.disp() == 0, "cas must take a zero displacement"); |
twisti@4323 | 3179 | casn(mark_addr.base(), Rmark, Rscratch); |
twisti@4323 | 3180 | cmp(Rmark, Rscratch); |
twisti@4323 | 3181 | brx(Assembler::equal, false, Assembler::pt, done); |
twisti@4323 | 3182 | delayed()->sub(Rscratch, SP, Rscratch); |
twisti@4323 | 3183 | |
twisti@4323 | 3184 | // Stack-lock attempt failed - check for recursive stack-lock. |
twisti@4323 | 3185 | // See the comments below about how we might remove this case. |
twisti@4323 | 3186 | #ifdef _LP64 |
twisti@4323 | 3187 | sub(Rscratch, STACK_BIAS, Rscratch); |
twisti@4323 | 3188 | #endif |
twisti@4323 | 3189 | assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); |
twisti@4323 | 3190 | andcc(Rscratch, 0xfffff003, Rscratch); |
twisti@4323 | 3191 | br(Assembler::always, false, Assembler::pt, done); |
twisti@4323 | 3192 | delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3193 | |
twisti@4323 | 3194 | bind(IsInflated); |
twisti@4323 | 3195 | if (EmitSync & 64) { |
twisti@4323 | 3196 | // If m->owner != null goto IsLocked |
twisti@4323 | 3197 | // Pessimistic form: Test-and-CAS vs CAS |
twisti@4323 | 3198 | // The optimistic form avoids RTS->RTO cache line upgrades. |
twisti@4323 | 3199 | ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); |
twisti@4323 | 3200 | andcc(Rscratch, Rscratch, G0); |
twisti@4323 | 3201 | brx(Assembler::notZero, false, Assembler::pn, done); |
twisti@4323 | 3202 | delayed()->nop(); |
twisti@4323 | 3203 | // m->owner == null : it's unlocked. |
twisti@4323 | 3204 | } |
twisti@4323 | 3205 | |
twisti@4323 | 3206 | // Try to CAS m->owner from null to Self |
twisti@4323 | 3207 | // Invariant: if we acquire the lock then _recursions should be 0. |
twisti@4323 | 3208 | add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); |
twisti@4323 | 3209 | mov(G2_thread, Rscratch); |
twisti@4323 | 3210 | casn(Rmark, G0, Rscratch); |
twisti@4323 | 3211 | cmp(Rscratch, G0); |
twisti@4323 | 3212 | // Intentional fall-through into done |
twisti@4323 | 3213 | } else { |
twisti@4323 | 3214 | // Aggressively avoid the Store-before-CAS penalty |
twisti@4323 | 3215 | // Defer the store into box->dhw until after the CAS |
twisti@4323 | 3216 | Label IsInflated, Recursive ; |
twisti@4323 | 3217 | |
twisti@4323 | 3218 | // Anticipate CAS -- Avoid RTS->RTO upgrade |
twisti@4323 | 3219 | // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); |
twisti@4323 | 3220 | |
twisti@4323 | 3221 | ld_ptr(mark_addr, Rmark); // fetch obj->mark |
twisti@4323 | 3222 | // Triage: biased, stack-locked, neutral, inflated |
twisti@4323 | 3223 | |
twisti@4323 | 3224 | if (try_bias) { |
twisti@4323 | 3225 | biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
twisti@4323 | 3226 | // Invariant: if control reaches this point in the emitted stream |
twisti@4323 | 3227 | // then Rmark has not been modified. |
twisti@4323 | 3228 | } |
twisti@4323 | 3229 | andcc(Rmark, 2, G0); |
twisti@4323 | 3230 | brx(Assembler::notZero, false, Assembler::pn, IsInflated); |
twisti@4323 | 3231 | delayed()-> // Beware - dangling delay-slot |
twisti@4323 | 3232 | |
twisti@4323 | 3233 | // Try stack-lock acquisition. |
twisti@4323 | 3234 | // Transiently install BUSY (0) encoding in the mark word. |
twisti@4323 | 3235 | // if the CAS of 0 into the mark was successful then we execute: |
twisti@4323 | 3236 | // ST box->dhw = mark -- save fetched mark in on-stack basiclock box |
twisti@4323 | 3237 | // ST obj->mark = box -- overwrite transient 0 value |
twisti@4323 | 3238 | // This presumes TSO, of course. |
twisti@4323 | 3239 | |
twisti@4323 | 3240 | mov(0, Rscratch); |
twisti@4323 | 3241 | or3(Rmark, markOopDesc::unlocked_value, Rmark); |
twisti@4323 | 3242 | assert(mark_addr.disp() == 0, "cas must take a zero displacement"); |
twisti@4323 | 3243 | casn(mark_addr.base(), Rmark, Rscratch); |
twisti@4323 | 3244 | // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); |
twisti@4323 | 3245 | cmp(Rscratch, Rmark); |
twisti@4323 | 3246 | brx(Assembler::notZero, false, Assembler::pn, Recursive); |
twisti@4323 | 3247 | delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3248 | if (counters != NULL) { |
twisti@4323 | 3249 | cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); |
twisti@4323 | 3250 | } |
twisti@4323 | 3251 | ba(done); |
twisti@4323 | 3252 | delayed()->st_ptr(Rbox, mark_addr); |
twisti@4323 | 3253 | |
twisti@4323 | 3254 | bind(Recursive); |
twisti@4323 | 3255 | // Stack-lock attempt failed - check for recursive stack-lock. |
twisti@4323 | 3256 | // Tests show that we can remove the recursive case with no impact |
twisti@4323 | 3257 | // on refworkload 0.83. If we need to reduce the size of the code |
twisti@4323 | 3258 | // emitted by compiler_lock_object() the recursive case is perfect |
twisti@4323 | 3259 | // candidate. |
twisti@4323 | 3260 | // |
twisti@4323 | 3261 | // A more extreme idea is to always inflate on stack-lock recursion. |
twisti@4323 | 3262 | // This lets us eliminate the recursive checks in compiler_lock_object |
twisti@4323 | 3263 | // and compiler_unlock_object and the (box->dhw == 0) encoding. |
twisti@4323 | 3264 | // A brief experiment - requiring changes to synchronizer.cpp, interpreter, |
twisti@4323 | 3265 | // and showed a performance *increase*. In the same experiment I eliminated |
twisti@4323 | 3266 | // the fast-path stack-lock code from the interpreter and always passed |
twisti@4323 | 3267 | // control to the "slow" operators in synchronizer.cpp. |
twisti@4323 | 3268 | |
twisti@4323 | 3269 | // RScratch contains the fetched obj->mark value from the failed CASN. |
twisti@4323 | 3270 | #ifdef _LP64 |
twisti@4323 | 3271 | sub(Rscratch, STACK_BIAS, Rscratch); |
twisti@4323 | 3272 | #endif |
twisti@4323 | 3273 | sub(Rscratch, SP, Rscratch); |
twisti@4323 | 3274 | assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); |
twisti@4323 | 3275 | andcc(Rscratch, 0xfffff003, Rscratch); |
twisti@4323 | 3276 | if (counters != NULL) { |
twisti@4323 | 3277 | // Accounting needs the Rscratch register |
twisti@4323 | 3278 | st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3279 | cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); |
twisti@4323 | 3280 | ba_short(done); |
twisti@4323 | 3281 | } else { |
twisti@4323 | 3282 | ba(done); |
twisti@4323 | 3283 | delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3284 | } |
twisti@4323 | 3285 | |
twisti@4323 | 3286 | bind (IsInflated); |
twisti@4323 | 3287 | if (EmitSync & 64) { |
twisti@4323 | 3288 | // If m->owner != null goto IsLocked |
twisti@4323 | 3289 | // Test-and-CAS vs CAS |
twisti@4323 | 3290 | // Pessimistic form avoids futile (doomed) CAS attempts |
twisti@4323 | 3291 | // The optimistic form avoids RTS->RTO cache line upgrades. |
twisti@4323 | 3292 | ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); |
twisti@4323 | 3293 | andcc(Rscratch, Rscratch, G0); |
twisti@4323 | 3294 | brx(Assembler::notZero, false, Assembler::pn, done); |
twisti@4323 | 3295 | delayed()->nop(); |
twisti@4323 | 3296 | // m->owner == null : it's unlocked. |
twisti@4323 | 3297 | } |
twisti@4323 | 3298 | |
twisti@4323 | 3299 | // Try to CAS m->owner from null to Self |
twisti@4323 | 3300 | // Invariant: if we acquire the lock then _recursions should be 0. |
twisti@4323 | 3301 | add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); |
twisti@4323 | 3302 | mov(G2_thread, Rscratch); |
twisti@4323 | 3303 | casn(Rmark, G0, Rscratch); |
twisti@4323 | 3304 | cmp(Rscratch, G0); |
twisti@4323 | 3305 | // ST box->displaced_header = NonZero. |
twisti@4323 | 3306 | // Any non-zero value suffices: |
twisti@4323 | 3307 | // unused_mark(), G2_thread, RBox, RScratch, rsp, etc. |
twisti@4323 | 3308 | st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
twisti@4323 | 3309 | // Intentional fall-through into done |
twisti@4323 | 3310 | } |
twisti@4323 | 3311 | |
twisti@4323 | 3312 | bind (done); |
twisti@4323 | 3313 | } |
twisti@4323 | 3314 | |
twisti@4323 | 3315 | void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, |
twisti@4323 | 3316 | Register Rbox, Register Rscratch, |
twisti@4323 | 3317 | bool try_bias) { |
twisti@4323 | 3318 | Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); |
twisti@4323 | 3319 | |
twisti@4323 | 3320 | Label done ; |
twisti@4323 | 3321 | |
twisti@4323 | 3322 | if (EmitSync & 4) { |
twisti@4323 | 3323 | cmp(SP, G0); |
twisti@4323 | 3324 | return ; |
twisti@4323 | 3325 | } |
twisti@4323 | 3326 | |
twisti@4323 | 3327 | if (EmitSync & 8) { |
twisti@4323 | 3328 | if (try_bias) { |
twisti@4323 | 3329 | biased_locking_exit(mark_addr, Rscratch, done); |
twisti@4323 | 3330 | } |
twisti@4323 | 3331 | |
twisti@4323 | 3332 | // Test first if it is a fast recursive unlock |
twisti@4323 | 3333 | ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); |
twisti@4323 | 3334 | br_null_short(Rmark, Assembler::pt, done); |
twisti@4323 | 3335 | |
twisti@4323 | 3336 | // Check if it is still a light weight lock, this is is true if we see |
twisti@4323 | 3337 | // the stack address of the basicLock in the markOop of the object |
twisti@4323 | 3338 | assert(mark_addr.disp() == 0, "cas must take a zero displacement"); |
twisti@4323 | 3339 | casx_under_lock(mark_addr.base(), Rbox, Rmark, |
twisti@4323 | 3340 | (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); |
twisti@4323 | 3341 | ba(done); |
twisti@4323 | 3342 | delayed()->cmp(Rbox, Rmark); |
twisti@4323 | 3343 | bind(done); |
twisti@4323 | 3344 | return ; |
twisti@4323 | 3345 | } |
twisti@4323 | 3346 | |
twisti@4323 | 3347 | // Beware ... If the aggregate size of the code emitted by CLO and CUO is |
twisti@4323 | 3348 | // is too large performance rolls abruptly off a cliff. |
twisti@4323 | 3349 | // This could be related to inlining policies, code cache management, or |
twisti@4323 | 3350 | // I$ effects. |
twisti@4323 | 3351 | Label LStacked ; |
twisti@4323 | 3352 | |
twisti@4323 | 3353 | if (try_bias) { |
twisti@4323 | 3354 | // TODO: eliminate redundant LDs of obj->mark |
twisti@4323 | 3355 | biased_locking_exit(mark_addr, Rscratch, done); |
twisti@4323 | 3356 | } |
twisti@4323 | 3357 | |
twisti@4323 | 3358 | ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark); |
twisti@4323 | 3359 | ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); |
twisti@4323 | 3360 | andcc(Rscratch, Rscratch, G0); |
twisti@4323 | 3361 | brx(Assembler::zero, false, Assembler::pn, done); |
twisti@4323 | 3362 | delayed()->nop(); // consider: relocate fetch of mark, above, into this DS |
twisti@4323 | 3363 | andcc(Rmark, 2, G0); |
twisti@4323 | 3364 | brx(Assembler::zero, false, Assembler::pt, LStacked); |
twisti@4323 | 3365 | delayed()->nop(); |
twisti@4323 | 3366 | |
twisti@4323 | 3367 | // It's inflated |
twisti@4323 | 3368 | // Conceptually we need a #loadstore|#storestore "release" MEMBAR before |
twisti@4323 | 3369 | // the ST of 0 into _owner which releases the lock. This prevents loads |
twisti@4323 | 3370 | // and stores within the critical section from reordering (floating) |
twisti@4323 | 3371 | // past the store that releases the lock. But TSO is a strong memory model |
twisti@4323 | 3372 | // and that particular flavor of barrier is a noop, so we can safely elide it. |
twisti@4323 | 3373 | // Note that we use 1-0 locking by default for the inflated case. We |
twisti@4323 | 3374 | // close the resultant (and rare) race by having contented threads in |
twisti@4323 | 3375 | // monitorenter periodically poll _owner. |
twisti@4323 | 3376 | ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); |
twisti@4323 | 3377 | ld_ptr(Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox); |
twisti@4323 | 3378 | xor3(Rscratch, G2_thread, Rscratch); |
twisti@4323 | 3379 | orcc(Rbox, Rscratch, Rbox); |
twisti@4323 | 3380 | brx(Assembler::notZero, false, Assembler::pn, done); |
twisti@4323 | 3381 | delayed()-> |
twisti@4323 | 3382 | ld_ptr(Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch); |
twisti@4323 | 3383 | ld_ptr(Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox); |
twisti@4323 | 3384 | orcc(Rbox, Rscratch, G0); |
twisti@4323 | 3385 | if (EmitSync & 65536) { |
twisti@4323 | 3386 | Label LSucc ; |
twisti@4323 | 3387 | brx(Assembler::notZero, false, Assembler::pn, LSucc); |
twisti@4323 | 3388 | delayed()->nop(); |
twisti@4323 | 3389 | ba(done); |
twisti@4323 | 3390 | delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); |
twisti@4323 | 3391 | |
twisti@4323 | 3392 | bind(LSucc); |
twisti@4323 | 3393 | st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); |
twisti@4323 | 3394 | if (os::is_MP()) { membar (StoreLoad); } |
twisti@4323 | 3395 | ld_ptr(Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch); |
twisti@4323 | 3396 | andcc(Rscratch, Rscratch, G0); |
twisti@4323 | 3397 | brx(Assembler::notZero, false, Assembler::pt, done); |
twisti@4323 | 3398 | delayed()->andcc(G0, G0, G0); |
twisti@4323 | 3399 | add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); |
twisti@4323 | 3400 | mov(G2_thread, Rscratch); |
twisti@4323 | 3401 | casn(Rmark, G0, Rscratch); |
twisti@4323 | 3402 | // invert icc.zf and goto done |
twisti@4323 | 3403 | br_notnull(Rscratch, false, Assembler::pt, done); |
twisti@4323 | 3404 | delayed()->cmp(G0, G0); |
twisti@4323 | 3405 | ba(done); |
twisti@4323 | 3406 | delayed()->cmp(G0, 1); |
twisti@4323 | 3407 | } else { |
twisti@4323 | 3408 | brx(Assembler::notZero, false, Assembler::pn, done); |
twisti@4323 | 3409 | delayed()->nop(); |
twisti@4323 | 3410 | ba(done); |
twisti@4323 | 3411 | delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); |
twisti@4323 | 3412 | } |
twisti@4323 | 3413 | |
twisti@4323 | 3414 | bind (LStacked); |
twisti@4323 | 3415 | // Consider: we could replace the expensive CAS in the exit |
twisti@4323 | 3416 | // path with a simple ST of the displaced mark value fetched from |
twisti@4323 | 3417 | // the on-stack basiclock box. That admits a race where a thread T2 |
twisti@4323 | 3418 | // in the slow lock path -- inflating with monitor M -- could race a |
twisti@4323 | 3419 | // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. |
twisti@4323 | 3420 | // More precisely T1 in the stack-lock unlock path could "stomp" the |
twisti@4323 | 3421 | // inflated mark value M installed by T2, resulting in an orphan |
twisti@4323 | 3422 | // object monitor M and T2 becoming stranded. We can remedy that situation |
twisti@4323 | 3423 | // by having T2 periodically poll the object's mark word using timed wait |
twisti@4323 | 3424 | // operations. If T2 discovers that a stomp has occurred it vacates |
twisti@4323 | 3425 | // the monitor M and wakes any other threads stranded on the now-orphan M. |
twisti@4323 | 3426 | // In addition the monitor scavenger, which performs deflation, |
twisti@4323 | 3427 | // would also need to check for orpan monitors and stranded threads. |
twisti@4323 | 3428 | // |
twisti@4323 | 3429 | // Finally, inflation is also used when T2 needs to assign a hashCode |
twisti@4323 | 3430 | // to O and O is stack-locked by T1. The "stomp" race could cause |
twisti@4323 | 3431 | // an assigned hashCode value to be lost. We can avoid that condition |
twisti@4323 | 3432 | // and provide the necessary hashCode stability invariants by ensuring |
twisti@4323 | 3433 | // that hashCode generation is idempotent between copying GCs. |
twisti@4323 | 3434 | // For example we could compute the hashCode of an object O as |
twisti@4323 | 3435 | // O's heap address XOR some high quality RNG value that is refreshed |
twisti@4323 | 3436 | // at GC-time. The monitor scavenger would install the hashCode |
twisti@4323 | 3437 | // found in any orphan monitors. Again, the mechanism admits a |
twisti@4323 | 3438 | // lost-update "stomp" WAW race but detects and recovers as needed. |
twisti@4323 | 3439 | // |
twisti@4323 | 3440 | // A prototype implementation showed excellent results, although |
twisti@4323 | 3441 | // the scavenger and timeout code was rather involved. |
twisti@4323 | 3442 | |
twisti@4323 | 3443 | casn(mark_addr.base(), Rbox, Rscratch); |
twisti@4323 | 3444 | cmp(Rbox, Rscratch); |
twisti@4323 | 3445 | // Intentional fall through into done ... |
twisti@4323 | 3446 | |
twisti@4323 | 3447 | bind(done); |
twisti@4323 | 3448 | } |
twisti@4323 | 3449 | |
twisti@4323 | 3450 | |
twisti@4323 | 3451 | |
twisti@4323 | 3452 | void MacroAssembler::print_CPU_state() { |
twisti@4323 | 3453 | // %%%%% need to implement this |
twisti@4323 | 3454 | } |
twisti@4323 | 3455 | |
twisti@4323 | 3456 | void MacroAssembler::verify_FPU(int stack_depth, const char* s) { |
twisti@4323 | 3457 | // %%%%% need to implement this |
twisti@4323 | 3458 | } |
twisti@4323 | 3459 | |
twisti@4323 | 3460 | void MacroAssembler::push_IU_state() { |
twisti@4323 | 3461 | // %%%%% need to implement this |
twisti@4323 | 3462 | } |
twisti@4323 | 3463 | |
twisti@4323 | 3464 | |
twisti@4323 | 3465 | void MacroAssembler::pop_IU_state() { |
twisti@4323 | 3466 | // %%%%% need to implement this |
twisti@4323 | 3467 | } |
twisti@4323 | 3468 | |
twisti@4323 | 3469 | |
twisti@4323 | 3470 | void MacroAssembler::push_FPU_state() { |
twisti@4323 | 3471 | // %%%%% need to implement this |
twisti@4323 | 3472 | } |
twisti@4323 | 3473 | |
twisti@4323 | 3474 | |
twisti@4323 | 3475 | void MacroAssembler::pop_FPU_state() { |
twisti@4323 | 3476 | // %%%%% need to implement this |
twisti@4323 | 3477 | } |
twisti@4323 | 3478 | |
twisti@4323 | 3479 | |
twisti@4323 | 3480 | void MacroAssembler::push_CPU_state() { |
twisti@4323 | 3481 | // %%%%% need to implement this |
twisti@4323 | 3482 | } |
twisti@4323 | 3483 | |
twisti@4323 | 3484 | |
twisti@4323 | 3485 | void MacroAssembler::pop_CPU_state() { |
twisti@4323 | 3486 | // %%%%% need to implement this |
twisti@4323 | 3487 | } |
twisti@4323 | 3488 | |
twisti@4323 | 3489 | |
twisti@4323 | 3490 | |
twisti@4323 | 3491 | void MacroAssembler::verify_tlab() { |
twisti@4323 | 3492 | #ifdef ASSERT |
twisti@4323 | 3493 | if (UseTLAB && VerifyOops) { |
twisti@4323 | 3494 | Label next, next2, ok; |
twisti@4323 | 3495 | Register t1 = L0; |
twisti@4323 | 3496 | Register t2 = L1; |
twisti@4323 | 3497 | Register t3 = L2; |
twisti@4323 | 3498 | |
twisti@4323 | 3499 | save_frame(0); |
twisti@4323 | 3500 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); |
twisti@4323 | 3501 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); |
twisti@4323 | 3502 | or3(t1, t2, t3); |
twisti@4323 | 3503 | cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next); |
twisti@4323 | 3504 | STOP("assert(top >= start)"); |
twisti@4323 | 3505 | should_not_reach_here(); |
twisti@4323 | 3506 | |
twisti@4323 | 3507 | bind(next); |
twisti@4323 | 3508 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); |
twisti@4323 | 3509 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); |
twisti@4323 | 3510 | or3(t3, t2, t3); |
twisti@4323 | 3511 | cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2); |
twisti@4323 | 3512 | STOP("assert(top <= end)"); |
twisti@4323 | 3513 | should_not_reach_here(); |
twisti@4323 | 3514 | |
twisti@4323 | 3515 | bind(next2); |
twisti@4323 | 3516 | and3(t3, MinObjAlignmentInBytesMask, t3); |
twisti@4323 | 3517 | cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok); |
twisti@4323 | 3518 | STOP("assert(aligned)"); |
twisti@4323 | 3519 | should_not_reach_here(); |
twisti@4323 | 3520 | |
twisti@4323 | 3521 | bind(ok); |
twisti@4323 | 3522 | restore(); |
twisti@4323 | 3523 | } |
twisti@4323 | 3524 | #endif |
twisti@4323 | 3525 | } |
twisti@4323 | 3526 | |
twisti@4323 | 3527 | |
twisti@4323 | 3528 | void MacroAssembler::eden_allocate( |
twisti@4323 | 3529 | Register obj, // result: pointer to object after successful allocation |
twisti@4323 | 3530 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
twisti@4323 | 3531 | int con_size_in_bytes, // object size in bytes if known at compile time |
twisti@4323 | 3532 | Register t1, // temp register |
twisti@4323 | 3533 | Register t2, // temp register |
twisti@4323 | 3534 | Label& slow_case // continuation point if fast allocation fails |
twisti@4323 | 3535 | ){ |
twisti@4323 | 3536 | // make sure arguments make sense |
twisti@4323 | 3537 | assert_different_registers(obj, var_size_in_bytes, t1, t2); |
twisti@4323 | 3538 | assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); |
twisti@4323 | 3539 | assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); |
twisti@4323 | 3540 | |
twisti@4323 | 3541 | if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
twisti@4323 | 3542 | // No allocation in the shared eden. |
twisti@4323 | 3543 | ba_short(slow_case); |
twisti@4323 | 3544 | } else { |
twisti@4323 | 3545 | // get eden boundaries |
twisti@4323 | 3546 | // note: we need both top & top_addr! |
twisti@4323 | 3547 | const Register top_addr = t1; |
twisti@4323 | 3548 | const Register end = t2; |
twisti@4323 | 3549 | |
twisti@4323 | 3550 | CollectedHeap* ch = Universe::heap(); |
twisti@4323 | 3551 | set((intx)ch->top_addr(), top_addr); |
twisti@4323 | 3552 | intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); |
twisti@4323 | 3553 | ld_ptr(top_addr, delta, end); |
twisti@4323 | 3554 | ld_ptr(top_addr, 0, obj); |
twisti@4323 | 3555 | |
twisti@4323 | 3556 | // try to allocate |
twisti@4323 | 3557 | Label retry; |
twisti@4323 | 3558 | bind(retry); |
twisti@4323 | 3559 | #ifdef ASSERT |
twisti@4323 | 3560 | // make sure eden top is properly aligned |
twisti@4323 | 3561 | { |
twisti@4323 | 3562 | Label L; |
twisti@4323 | 3563 | btst(MinObjAlignmentInBytesMask, obj); |
twisti@4323 | 3564 | br(Assembler::zero, false, Assembler::pt, L); |
twisti@4323 | 3565 | delayed()->nop(); |
twisti@4323 | 3566 | STOP("eden top is not properly aligned"); |
twisti@4323 | 3567 | bind(L); |
twisti@4323 | 3568 | } |
twisti@4323 | 3569 | #endif // ASSERT |
twisti@4323 | 3570 | const Register free = end; |
twisti@4323 | 3571 | sub(end, obj, free); // compute amount of free space |
twisti@4323 | 3572 | if (var_size_in_bytes->is_valid()) { |
twisti@4323 | 3573 | // size is unknown at compile time |
twisti@4323 | 3574 | cmp(free, var_size_in_bytes); |
twisti@4323 | 3575 | br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case |
twisti@4323 | 3576 | delayed()->add(obj, var_size_in_bytes, end); |
twisti@4323 | 3577 | } else { |
twisti@4323 | 3578 | // size is known at compile time |
twisti@4323 | 3579 | cmp(free, con_size_in_bytes); |
twisti@4323 | 3580 | br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case |
twisti@4323 | 3581 | delayed()->add(obj, con_size_in_bytes, end); |
twisti@4323 | 3582 | } |
twisti@4323 | 3583 | // Compare obj with the value at top_addr; if still equal, swap the value of |
twisti@4323 | 3584 | // end with the value at top_addr. If not equal, read the value at top_addr |
twisti@4323 | 3585 | // into end. |
twisti@4323 | 3586 | casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); |
twisti@4323 | 3587 | // if someone beat us on the allocation, try again, otherwise continue |
twisti@4323 | 3588 | cmp(obj, end); |
twisti@4323 | 3589 | brx(Assembler::notEqual, false, Assembler::pn, retry); |
twisti@4323 | 3590 | delayed()->mov(end, obj); // nop if successfull since obj == end |
twisti@4323 | 3591 | |
twisti@4323 | 3592 | #ifdef ASSERT |
twisti@4323 | 3593 | // make sure eden top is properly aligned |
twisti@4323 | 3594 | { |
twisti@4323 | 3595 | Label L; |
twisti@4323 | 3596 | const Register top_addr = t1; |
twisti@4323 | 3597 | |
twisti@4323 | 3598 | set((intx)ch->top_addr(), top_addr); |
twisti@4323 | 3599 | ld_ptr(top_addr, 0, top_addr); |
twisti@4323 | 3600 | btst(MinObjAlignmentInBytesMask, top_addr); |
twisti@4323 | 3601 | br(Assembler::zero, false, Assembler::pt, L); |
twisti@4323 | 3602 | delayed()->nop(); |
twisti@4323 | 3603 | STOP("eden top is not properly aligned"); |
twisti@4323 | 3604 | bind(L); |
twisti@4323 | 3605 | } |
twisti@4323 | 3606 | #endif // ASSERT |
twisti@4323 | 3607 | } |
twisti@4323 | 3608 | } |
twisti@4323 | 3609 | |
twisti@4323 | 3610 | |
twisti@4323 | 3611 | void MacroAssembler::tlab_allocate( |
twisti@4323 | 3612 | Register obj, // result: pointer to object after successful allocation |
twisti@4323 | 3613 | Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
twisti@4323 | 3614 | int con_size_in_bytes, // object size in bytes if known at compile time |
twisti@4323 | 3615 | Register t1, // temp register |
twisti@4323 | 3616 | Label& slow_case // continuation point if fast allocation fails |
twisti@4323 | 3617 | ){ |
twisti@4323 | 3618 | // make sure arguments make sense |
twisti@4323 | 3619 | assert_different_registers(obj, var_size_in_bytes, t1); |
twisti@4323 | 3620 | assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); |
twisti@4323 | 3621 | assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); |
twisti@4323 | 3622 | |
twisti@4323 | 3623 | const Register free = t1; |
twisti@4323 | 3624 | |
twisti@4323 | 3625 | verify_tlab(); |
twisti@4323 | 3626 | |
twisti@4323 | 3627 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); |
twisti@4323 | 3628 | |
twisti@4323 | 3629 | // calculate amount of free space |
twisti@4323 | 3630 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); |
twisti@4323 | 3631 | sub(free, obj, free); |
twisti@4323 | 3632 | |
twisti@4323 | 3633 | Label done; |
twisti@4323 | 3634 | if (var_size_in_bytes == noreg) { |
twisti@4323 | 3635 | cmp(free, con_size_in_bytes); |
twisti@4323 | 3636 | } else { |
twisti@4323 | 3637 | cmp(free, var_size_in_bytes); |
twisti@4323 | 3638 | } |
twisti@4323 | 3639 | br(Assembler::less, false, Assembler::pn, slow_case); |
twisti@4323 | 3640 | // calculate the new top pointer |
twisti@4323 | 3641 | if (var_size_in_bytes == noreg) { |
twisti@4323 | 3642 | delayed()->add(obj, con_size_in_bytes, free); |
twisti@4323 | 3643 | } else { |
twisti@4323 | 3644 | delayed()->add(obj, var_size_in_bytes, free); |
twisti@4323 | 3645 | } |
twisti@4323 | 3646 | |
twisti@4323 | 3647 | bind(done); |
twisti@4323 | 3648 | |
twisti@4323 | 3649 | #ifdef ASSERT |
twisti@4323 | 3650 | // make sure new free pointer is properly aligned |
twisti@4323 | 3651 | { |
twisti@4323 | 3652 | Label L; |
twisti@4323 | 3653 | btst(MinObjAlignmentInBytesMask, free); |
twisti@4323 | 3654 | br(Assembler::zero, false, Assembler::pt, L); |
twisti@4323 | 3655 | delayed()->nop(); |
twisti@4323 | 3656 | STOP("updated TLAB free is not properly aligned"); |
twisti@4323 | 3657 | bind(L); |
twisti@4323 | 3658 | } |
twisti@4323 | 3659 | #endif // ASSERT |
twisti@4323 | 3660 | |
twisti@4323 | 3661 | // update the tlab top pointer |
twisti@4323 | 3662 | st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); |
twisti@4323 | 3663 | verify_tlab(); |
twisti@4323 | 3664 | } |
twisti@4323 | 3665 | |
twisti@4323 | 3666 | |
twisti@4323 | 3667 | void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { |
twisti@4323 | 3668 | Register top = O0; |
twisti@4323 | 3669 | Register t1 = G1; |
twisti@4323 | 3670 | Register t2 = G3; |
twisti@4323 | 3671 | Register t3 = O1; |
twisti@4323 | 3672 | assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); |
twisti@4323 | 3673 | Label do_refill, discard_tlab; |
twisti@4323 | 3674 | |
twisti@4323 | 3675 | if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
twisti@4323 | 3676 | // No allocation in the shared eden. |
twisti@4323 | 3677 | ba_short(slow_case); |
twisti@4323 | 3678 | } |
twisti@4323 | 3679 | |
twisti@4323 | 3680 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); |
twisti@4323 | 3681 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); |
twisti@4323 | 3682 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); |
twisti@4323 | 3683 | |
twisti@4323 | 3684 | // calculate amount of free space |
twisti@4323 | 3685 | sub(t1, top, t1); |
twisti@4323 | 3686 | srl_ptr(t1, LogHeapWordSize, t1); |
twisti@4323 | 3687 | |
twisti@4323 | 3688 | // Retain tlab and allocate object in shared space if |
twisti@4323 | 3689 | // the amount free in the tlab is too large to discard. |
twisti@4323 | 3690 | cmp(t1, t2); |
twisti@4323 | 3691 | brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); |
twisti@4323 | 3692 | |
twisti@4323 | 3693 | // increment waste limit to prevent getting stuck on this slow path |
twisti@4323 | 3694 | delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); |
twisti@4323 | 3695 | st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); |
twisti@4323 | 3696 | if (TLABStats) { |
twisti@4323 | 3697 | // increment number of slow_allocations |
twisti@4323 | 3698 | ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); |
twisti@4323 | 3699 | add(t2, 1, t2); |
twisti@4323 | 3700 | stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); |
twisti@4323 | 3701 | } |
twisti@4323 | 3702 | ba_short(try_eden); |
twisti@4323 | 3703 | |
twisti@4323 | 3704 | bind(discard_tlab); |
twisti@4323 | 3705 | if (TLABStats) { |
twisti@4323 | 3706 | // increment number of refills |
twisti@4323 | 3707 | ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); |
twisti@4323 | 3708 | add(t2, 1, t2); |
twisti@4323 | 3709 | stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); |
twisti@4323 | 3710 | // accumulate wastage |
twisti@4323 | 3711 | ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); |
twisti@4323 | 3712 | add(t2, t1, t2); |
twisti@4323 | 3713 | stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); |
twisti@4323 | 3714 | } |
twisti@4323 | 3715 | |
twisti@4323 | 3716 | // if tlab is currently allocated (top or end != null) then |
twisti@4323 | 3717 | // fill [top, end + alignment_reserve) with array object |
twisti@4323 | 3718 | br_null_short(top, Assembler::pn, do_refill); |
twisti@4323 | 3719 | |
twisti@4323 | 3720 | set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); |
twisti@4323 | 3721 | st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word |
twisti@4323 | 3722 | // set klass to intArrayKlass |
twisti@4323 | 3723 | sub(t1, typeArrayOopDesc::header_size(T_INT), t1); |
twisti@4323 | 3724 | add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); |
twisti@4323 | 3725 | sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); |
twisti@4323 | 3726 | st(t1, top, arrayOopDesc::length_offset_in_bytes()); |
twisti@4323 | 3727 | set((intptr_t)Universe::intArrayKlassObj_addr(), t2); |
twisti@4323 | 3728 | ld_ptr(t2, 0, t2); |
twisti@4323 | 3729 | // store klass last. concurrent gcs assumes klass length is valid if |
twisti@4323 | 3730 | // klass field is not null. |
twisti@4323 | 3731 | store_klass(t2, top); |
twisti@4323 | 3732 | verify_oop(top); |
twisti@4323 | 3733 | |
twisti@4323 | 3734 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1); |
twisti@4323 | 3735 | sub(top, t1, t1); // size of tlab's allocated portion |
twisti@4323 | 3736 | incr_allocated_bytes(t1, t2, t3); |
twisti@4323 | 3737 | |
twisti@4323 | 3738 | // refill the tlab with an eden allocation |
twisti@4323 | 3739 | bind(do_refill); |
twisti@4323 | 3740 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); |
twisti@4323 | 3741 | sll_ptr(t1, LogHeapWordSize, t1); |
twisti@4323 | 3742 | // allocate new tlab, address returned in top |
twisti@4323 | 3743 | eden_allocate(top, t1, 0, t2, t3, slow_case); |
twisti@4323 | 3744 | |
twisti@4323 | 3745 | st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); |
twisti@4323 | 3746 | st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); |
twisti@4323 | 3747 | #ifdef ASSERT |
twisti@4323 | 3748 | // check that tlab_size (t1) is still valid |
twisti@4323 | 3749 | { |
twisti@4323 | 3750 | Label ok; |
twisti@4323 | 3751 | ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); |
twisti@4323 | 3752 | sll_ptr(t2, LogHeapWordSize, t2); |
twisti@4323 | 3753 | cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok); |
twisti@4323 | 3754 | STOP("assert(t1 == tlab_size)"); |
twisti@4323 | 3755 | should_not_reach_here(); |
twisti@4323 | 3756 | |
twisti@4323 | 3757 | bind(ok); |
twisti@4323 | 3758 | } |
twisti@4323 | 3759 | #endif // ASSERT |
twisti@4323 | 3760 | add(top, t1, top); // t1 is tlab_size |
twisti@4323 | 3761 | sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); |
twisti@4323 | 3762 | st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); |
twisti@4323 | 3763 | verify_tlab(); |
twisti@4323 | 3764 | ba_short(retry); |
twisti@4323 | 3765 | } |
twisti@4323 | 3766 | |
twisti@4323 | 3767 | void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes, |
twisti@4323 | 3768 | Register t1, Register t2) { |
twisti@4323 | 3769 | // Bump total bytes allocated by this thread |
twisti@4323 | 3770 | assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch |
twisti@4323 | 3771 | assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2); |
twisti@4323 | 3772 | // v8 support has gone the way of the dodo |
twisti@4323 | 3773 | ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1); |
twisti@4323 | 3774 | add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1); |
twisti@4323 | 3775 | stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset())); |
twisti@4323 | 3776 | } |
twisti@4323 | 3777 | |
twisti@4323 | 3778 | Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
twisti@4323 | 3779 | switch (cond) { |
twisti@4323 | 3780 | // Note some conditions are synonyms for others |
twisti@4323 | 3781 | case Assembler::never: return Assembler::always; |
twisti@4323 | 3782 | case Assembler::zero: return Assembler::notZero; |
twisti@4323 | 3783 | case Assembler::lessEqual: return Assembler::greater; |
twisti@4323 | 3784 | case Assembler::less: return Assembler::greaterEqual; |
twisti@4323 | 3785 | case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; |
twisti@4323 | 3786 | case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; |
twisti@4323 | 3787 | case Assembler::negative: return Assembler::positive; |
twisti@4323 | 3788 | case Assembler::overflowSet: return Assembler::overflowClear; |
twisti@4323 | 3789 | case Assembler::always: return Assembler::never; |
twisti@4323 | 3790 | case Assembler::notZero: return Assembler::zero; |
twisti@4323 | 3791 | case Assembler::greater: return Assembler::lessEqual; |
twisti@4323 | 3792 | case Assembler::greaterEqual: return Assembler::less; |
twisti@4323 | 3793 | case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; |
twisti@4323 | 3794 | case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; |
twisti@4323 | 3795 | case Assembler::positive: return Assembler::negative; |
twisti@4323 | 3796 | case Assembler::overflowClear: return Assembler::overflowSet; |
twisti@4323 | 3797 | } |
twisti@4323 | 3798 | |
twisti@4323 | 3799 | ShouldNotReachHere(); return Assembler::overflowClear; |
twisti@4323 | 3800 | } |
twisti@4323 | 3801 | |
twisti@4323 | 3802 | void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, |
twisti@4323 | 3803 | Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { |
twisti@4323 | 3804 | Condition negated_cond = negate_condition(cond); |
twisti@4323 | 3805 | Label L; |
twisti@4323 | 3806 | brx(negated_cond, false, Assembler::pt, L); |
twisti@4323 | 3807 | delayed()->nop(); |
twisti@4323 | 3808 | inc_counter(counter_ptr, Rtmp1, Rtmp2); |
twisti@4323 | 3809 | bind(L); |
twisti@4323 | 3810 | } |
twisti@4323 | 3811 | |
twisti@4323 | 3812 | void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) { |
twisti@4323 | 3813 | AddressLiteral addrlit(counter_addr); |
twisti@4323 | 3814 | sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register. |
twisti@4323 | 3815 | Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits. |
twisti@4323 | 3816 | ld(addr, Rtmp2); |
twisti@4323 | 3817 | inc(Rtmp2); |
twisti@4323 | 3818 | st(Rtmp2, addr); |
twisti@4323 | 3819 | } |
twisti@4323 | 3820 | |
twisti@4323 | 3821 | void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) { |
twisti@4323 | 3822 | inc_counter((address) counter_addr, Rtmp1, Rtmp2); |
twisti@4323 | 3823 | } |
twisti@4323 | 3824 | |
twisti@4323 | 3825 | SkipIfEqual::SkipIfEqual( |
twisti@4323 | 3826 | MacroAssembler* masm, Register temp, const bool* flag_addr, |
twisti@4323 | 3827 | Assembler::Condition condition) { |
twisti@4323 | 3828 | _masm = masm; |
twisti@4323 | 3829 | AddressLiteral flag(flag_addr); |
twisti@4323 | 3830 | _masm->sethi(flag, temp); |
twisti@4323 | 3831 | _masm->ldub(temp, flag.low10(), temp); |
twisti@4323 | 3832 | _masm->tst(temp); |
twisti@4323 | 3833 | _masm->br(condition, false, Assembler::pt, _label); |
twisti@4323 | 3834 | _masm->delayed()->nop(); |
twisti@4323 | 3835 | } |
twisti@4323 | 3836 | |
twisti@4323 | 3837 | SkipIfEqual::~SkipIfEqual() { |
twisti@4323 | 3838 | _masm->bind(_label); |
twisti@4323 | 3839 | } |
twisti@4323 | 3840 | |
twisti@4323 | 3841 | |
twisti@4323 | 3842 | // Writes to stack successive pages until offset reached to check for |
twisti@4323 | 3843 | // stack overflow + shadow pages. This clobbers tsp and scratch. |
twisti@4323 | 3844 | void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, |
twisti@4323 | 3845 | Register Rscratch) { |
twisti@4323 | 3846 | // Use stack pointer in temp stack pointer |
twisti@4323 | 3847 | mov(SP, Rtsp); |
twisti@4323 | 3848 | |
twisti@4323 | 3849 | // Bang stack for total size given plus stack shadow page size. |
twisti@4323 | 3850 | // Bang one page at a time because a large size can overflow yellow and |
twisti@4323 | 3851 | // red zones (the bang will fail but stack overflow handling can't tell that |
twisti@4323 | 3852 | // it was a stack overflow bang vs a regular segv). |
twisti@4323 | 3853 | int offset = os::vm_page_size(); |
twisti@4323 | 3854 | Register Roffset = Rscratch; |
twisti@4323 | 3855 | |
twisti@4323 | 3856 | Label loop; |
twisti@4323 | 3857 | bind(loop); |
twisti@4323 | 3858 | set((-offset)+STACK_BIAS, Rscratch); |
twisti@4323 | 3859 | st(G0, Rtsp, Rscratch); |
twisti@4323 | 3860 | set(offset, Roffset); |
twisti@4323 | 3861 | sub(Rsize, Roffset, Rsize); |
twisti@4323 | 3862 | cmp(Rsize, G0); |
twisti@4323 | 3863 | br(Assembler::greater, false, Assembler::pn, loop); |
twisti@4323 | 3864 | delayed()->sub(Rtsp, Roffset, Rtsp); |
twisti@4323 | 3865 | |
twisti@4323 | 3866 | // Bang down shadow pages too. |
twisti@4323 | 3867 | // The -1 because we already subtracted 1 page. |
twisti@4323 | 3868 | for (int i = 0; i< StackShadowPages-1; i++) { |
twisti@4323 | 3869 | set((-i*offset)+STACK_BIAS, Rscratch); |
twisti@4323 | 3870 | st(G0, Rtsp, Rscratch); |
twisti@4323 | 3871 | } |
twisti@4323 | 3872 | } |
twisti@4323 | 3873 | |
twisti@4323 | 3874 | /////////////////////////////////////////////////////////////////////////////////// |
jprovino@4542 | 3875 | #if INCLUDE_ALL_GCS |
twisti@4323 | 3876 | |
twisti@4323 | 3877 | static address satb_log_enqueue_with_frame = NULL; |
twisti@4323 | 3878 | static u_char* satb_log_enqueue_with_frame_end = NULL; |
twisti@4323 | 3879 | |
twisti@4323 | 3880 | static address satb_log_enqueue_frameless = NULL; |
twisti@4323 | 3881 | static u_char* satb_log_enqueue_frameless_end = NULL; |
twisti@4323 | 3882 | |
twisti@4323 | 3883 | static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions? |
twisti@4323 | 3884 | |
twisti@4323 | 3885 | static void generate_satb_log_enqueue(bool with_frame) { |
twisti@4323 | 3886 | BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize); |
twisti@4323 | 3887 | CodeBuffer buf(bb); |
twisti@4323 | 3888 | MacroAssembler masm(&buf); |
twisti@4323 | 3889 | |
twisti@4323 | 3890 | #define __ masm. |
twisti@4323 | 3891 | |
twisti@4323 | 3892 | address start = __ pc(); |
twisti@4323 | 3893 | Register pre_val; |
twisti@4323 | 3894 | |
twisti@4323 | 3895 | Label refill, restart; |
twisti@4323 | 3896 | if (with_frame) { |
twisti@4323 | 3897 | __ save_frame(0); |
twisti@4323 | 3898 | pre_val = I0; // Was O0 before the save. |
twisti@4323 | 3899 | } else { |
twisti@4323 | 3900 | pre_val = O0; |
twisti@4323 | 3901 | } |
twisti@4323 | 3902 | |
twisti@4323 | 3903 | int satb_q_index_byte_offset = |
twisti@4323 | 3904 | in_bytes(JavaThread::satb_mark_queue_offset() + |
twisti@4323 | 3905 | PtrQueue::byte_offset_of_index()); |
twisti@4323 | 3906 | |
twisti@4323 | 3907 | int satb_q_buf_byte_offset = |
twisti@4323 | 3908 | in_bytes(JavaThread::satb_mark_queue_offset() + |
twisti@4323 | 3909 | PtrQueue::byte_offset_of_buf()); |
twisti@4323 | 3910 | |
twisti@4323 | 3911 | assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) && |
twisti@4323 | 3912 | in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t), |
twisti@4323 | 3913 | "check sizes in assembly below"); |
twisti@4323 | 3914 | |
twisti@4323 | 3915 | __ bind(restart); |
twisti@4323 | 3916 | |
twisti@4323 | 3917 | // Load the index into the SATB buffer. PtrQueue::_index is a size_t |
twisti@4323 | 3918 | // so ld_ptr is appropriate. |
twisti@4323 | 3919 | __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0); |
twisti@4323 | 3920 | |
twisti@4323 | 3921 | // index == 0? |
twisti@4323 | 3922 | __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); |
twisti@4323 | 3923 | |
twisti@4323 | 3924 | __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1); |
twisti@4323 | 3925 | __ sub(L0, oopSize, L0); |
twisti@4323 | 3926 | |
twisti@4323 | 3927 | __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0 |
twisti@4323 | 3928 | if (!with_frame) { |
twisti@4323 | 3929 | // Use return-from-leaf |
twisti@4323 | 3930 | __ retl(); |
twisti@4323 | 3931 | __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset); |
twisti@4323 | 3932 | } else { |
twisti@4323 | 3933 | // Not delayed. |
twisti@4323 | 3934 | __ st_ptr(L0, G2_thread, satb_q_index_byte_offset); |
twisti@4323 | 3935 | } |
twisti@4323 | 3936 | if (with_frame) { |
twisti@4323 | 3937 | __ ret(); |
twisti@4323 | 3938 | __ delayed()->restore(); |
twisti@4323 | 3939 | } |
twisti@4323 | 3940 | __ bind(refill); |
twisti@4323 | 3941 | |
twisti@4323 | 3942 | address handle_zero = |
twisti@4323 | 3943 | CAST_FROM_FN_PTR(address, |
twisti@4323 | 3944 | &SATBMarkQueueSet::handle_zero_index_for_thread); |
twisti@4323 | 3945 | // This should be rare enough that we can afford to save all the |
twisti@4323 | 3946 | // scratch registers that the calling context might be using. |
twisti@4323 | 3947 | __ mov(G1_scratch, L0); |
twisti@4323 | 3948 | __ mov(G3_scratch, L1); |
twisti@4323 | 3949 | __ mov(G4, L2); |
twisti@4323 | 3950 | // We need the value of O0 above (for the write into the buffer), so we |
twisti@4323 | 3951 | // save and restore it. |
twisti@4323 | 3952 | __ mov(O0, L3); |
twisti@4323 | 3953 | // Since the call will overwrite O7, we save and restore that, as well. |
twisti@4323 | 3954 | __ mov(O7, L4); |
twisti@4323 | 3955 | __ call_VM_leaf(L5, handle_zero, G2_thread); |
twisti@4323 | 3956 | __ mov(L0, G1_scratch); |
twisti@4323 | 3957 | __ mov(L1, G3_scratch); |
twisti@4323 | 3958 | __ mov(L2, G4); |
twisti@4323 | 3959 | __ mov(L3, O0); |
twisti@4323 | 3960 | __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); |
twisti@4323 | 3961 | __ delayed()->mov(L4, O7); |
twisti@4323 | 3962 | |
twisti@4323 | 3963 | if (with_frame) { |
twisti@4323 | 3964 | satb_log_enqueue_with_frame = start; |
twisti@4323 | 3965 | satb_log_enqueue_with_frame_end = __ pc(); |
twisti@4323 | 3966 | } else { |
twisti@4323 | 3967 | satb_log_enqueue_frameless = start; |
twisti@4323 | 3968 | satb_log_enqueue_frameless_end = __ pc(); |
twisti@4323 | 3969 | } |
twisti@4323 | 3970 | |
twisti@4323 | 3971 | #undef __ |
twisti@4323 | 3972 | } |
twisti@4323 | 3973 | |
twisti@4323 | 3974 | static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) { |
twisti@4323 | 3975 | if (with_frame) { |
twisti@4323 | 3976 | if (satb_log_enqueue_with_frame == 0) { |
twisti@4323 | 3977 | generate_satb_log_enqueue(with_frame); |
twisti@4323 | 3978 | assert(satb_log_enqueue_with_frame != 0, "postcondition."); |
twisti@4323 | 3979 | if (G1SATBPrintStubs) { |
twisti@4323 | 3980 | tty->print_cr("Generated with-frame satb enqueue:"); |
twisti@4323 | 3981 | Disassembler::decode((u_char*)satb_log_enqueue_with_frame, |
twisti@4323 | 3982 | satb_log_enqueue_with_frame_end, |
twisti@4323 | 3983 | tty); |
twisti@4323 | 3984 | } |
twisti@4323 | 3985 | } |
twisti@4323 | 3986 | } else { |
twisti@4323 | 3987 | if (satb_log_enqueue_frameless == 0) { |
twisti@4323 | 3988 | generate_satb_log_enqueue(with_frame); |
twisti@4323 | 3989 | assert(satb_log_enqueue_frameless != 0, "postcondition."); |
twisti@4323 | 3990 | if (G1SATBPrintStubs) { |
twisti@4323 | 3991 | tty->print_cr("Generated frameless satb enqueue:"); |
twisti@4323 | 3992 | Disassembler::decode((u_char*)satb_log_enqueue_frameless, |
twisti@4323 | 3993 | satb_log_enqueue_frameless_end, |
twisti@4323 | 3994 | tty); |
twisti@4323 | 3995 | } |
twisti@4323 | 3996 | } |
twisti@4323 | 3997 | } |
twisti@4323 | 3998 | } |
twisti@4323 | 3999 | |
twisti@4323 | 4000 | void MacroAssembler::g1_write_barrier_pre(Register obj, |
twisti@4323 | 4001 | Register index, |
twisti@4323 | 4002 | int offset, |
twisti@4323 | 4003 | Register pre_val, |
twisti@4323 | 4004 | Register tmp, |
twisti@4323 | 4005 | bool preserve_o_regs) { |
twisti@4323 | 4006 | Label filtered; |
twisti@4323 | 4007 | |
twisti@4323 | 4008 | if (obj == noreg) { |
twisti@4323 | 4009 | // We are not loading the previous value so make |
twisti@4323 | 4010 | // sure that we don't trash the value in pre_val |
twisti@4323 | 4011 | // with the code below. |
twisti@4323 | 4012 | assert_different_registers(pre_val, tmp); |
twisti@4323 | 4013 | } else { |
twisti@4323 | 4014 | // We will be loading the previous value |
twisti@4323 | 4015 | // in this code so... |
twisti@4323 | 4016 | assert(offset == 0 || index == noreg, "choose one"); |
twisti@4323 | 4017 | assert(pre_val == noreg, "check this code"); |
twisti@4323 | 4018 | } |
twisti@4323 | 4019 | |
twisti@4323 | 4020 | // Is marking active? |
twisti@4323 | 4021 | if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
twisti@4323 | 4022 | ld(G2, |
twisti@4323 | 4023 | in_bytes(JavaThread::satb_mark_queue_offset() + |
twisti@4323 | 4024 | PtrQueue::byte_offset_of_active()), |
twisti@4323 | 4025 | tmp); |
twisti@4323 | 4026 | } else { |
twisti@4323 | 4027 | guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, |
twisti@4323 | 4028 | "Assumption"); |
twisti@4323 | 4029 | ldsb(G2, |
twisti@4323 | 4030 | in_bytes(JavaThread::satb_mark_queue_offset() + |
twisti@4323 | 4031 | PtrQueue::byte_offset_of_active()), |
twisti@4323 | 4032 | tmp); |
twisti@4323 | 4033 | } |
twisti@4323 | 4034 | |
twisti@4323 | 4035 | // Is marking active? |
twisti@4323 | 4036 | cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); |
twisti@4323 | 4037 | |
twisti@4323 | 4038 | // Do we need to load the previous value? |
twisti@4323 | 4039 | if (obj != noreg) { |
twisti@4323 | 4040 | // Load the previous value... |
twisti@4323 | 4041 | if (index == noreg) { |
twisti@4323 | 4042 | if (Assembler::is_simm13(offset)) { |
twisti@4323 | 4043 | load_heap_oop(obj, offset, tmp); |
twisti@4323 | 4044 | } else { |
twisti@4323 | 4045 | set(offset, tmp); |
twisti@4323 | 4046 | load_heap_oop(obj, tmp, tmp); |
twisti@4323 | 4047 | } |
twisti@4323 | 4048 | } else { |
twisti@4323 | 4049 | load_heap_oop(obj, index, tmp); |
twisti@4323 | 4050 | } |
twisti@4323 | 4051 | // Previous value has been loaded into tmp |
twisti@4323 | 4052 | pre_val = tmp; |
twisti@4323 | 4053 | } |
twisti@4323 | 4054 | |
twisti@4323 | 4055 | assert(pre_val != noreg, "must have a real register"); |
twisti@4323 | 4056 | |
twisti@4323 | 4057 | // Is the previous value null? |
twisti@4323 | 4058 | cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered); |
twisti@4323 | 4059 | |
twisti@4323 | 4060 | // OK, it's not filtered, so we'll need to call enqueue. In the normal |
twisti@4323 | 4061 | // case, pre_val will be a scratch G-reg, but there are some cases in |
twisti@4323 | 4062 | // which it's an O-reg. In the first case, do a normal call. In the |
twisti@4323 | 4063 | // latter, do a save here and call the frameless version. |
twisti@4323 | 4064 | |
twisti@4323 | 4065 | guarantee(pre_val->is_global() || pre_val->is_out(), |
twisti@4323 | 4066 | "Or we need to think harder."); |
twisti@4323 | 4067 | |
twisti@4323 | 4068 | if (pre_val->is_global() && !preserve_o_regs) { |
twisti@4323 | 4069 | generate_satb_log_enqueue_if_necessary(true); // with frame |
twisti@4323 | 4070 | |
twisti@4323 | 4071 | call(satb_log_enqueue_with_frame); |
twisti@4323 | 4072 | delayed()->mov(pre_val, O0); |
twisti@4323 | 4073 | } else { |
twisti@4323 | 4074 | generate_satb_log_enqueue_if_necessary(false); // frameless |
twisti@4323 | 4075 | |
twisti@4323 | 4076 | save_frame(0); |
twisti@4323 | 4077 | call(satb_log_enqueue_frameless); |
twisti@4323 | 4078 | delayed()->mov(pre_val->after_save(), O0); |
twisti@4323 | 4079 | restore(); |
twisti@4323 | 4080 | } |
twisti@4323 | 4081 | |
twisti@4323 | 4082 | bind(filtered); |
twisti@4323 | 4083 | } |
twisti@4323 | 4084 | |
twisti@4323 | 4085 | static address dirty_card_log_enqueue = 0; |
twisti@4323 | 4086 | static u_char* dirty_card_log_enqueue_end = 0; |
twisti@4323 | 4087 | |
twisti@4323 | 4088 | // This gets to assume that o0 contains the object address. |
twisti@4323 | 4089 | static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) { |
twisti@4323 | 4090 | BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2); |
twisti@4323 | 4091 | CodeBuffer buf(bb); |
twisti@4323 | 4092 | MacroAssembler masm(&buf); |
twisti@4323 | 4093 | #define __ masm. |
twisti@4323 | 4094 | address start = __ pc(); |
twisti@4323 | 4095 | |
twisti@4323 | 4096 | Label not_already_dirty, restart, refill; |
twisti@4323 | 4097 | |
twisti@4323 | 4098 | #ifdef _LP64 |
twisti@4323 | 4099 | __ srlx(O0, CardTableModRefBS::card_shift, O0); |
twisti@4323 | 4100 | #else |
twisti@4323 | 4101 | __ srl(O0, CardTableModRefBS::card_shift, O0); |
twisti@4323 | 4102 | #endif |
twisti@4323 | 4103 | AddressLiteral addrlit(byte_map_base); |
twisti@4323 | 4104 | __ set(addrlit, O1); // O1 := <card table base> |
twisti@4323 | 4105 | __ ldub(O0, O1, O2); // O2 := [O0 + O1] |
twisti@4323 | 4106 | |
twisti@4323 | 4107 | assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code"); |
twisti@4323 | 4108 | __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty); |
twisti@4323 | 4109 | |
twisti@4323 | 4110 | // We didn't take the branch, so we're already dirty: return. |
twisti@4323 | 4111 | // Use return-from-leaf |
twisti@4323 | 4112 | __ retl(); |
twisti@4323 | 4113 | __ delayed()->nop(); |
twisti@4323 | 4114 | |
twisti@4323 | 4115 | // Not dirty. |
twisti@4323 | 4116 | __ bind(not_already_dirty); |
twisti@4323 | 4117 | |
twisti@4323 | 4118 | // Get O0 + O1 into a reg by itself |
twisti@4323 | 4119 | __ add(O0, O1, O3); |
twisti@4323 | 4120 | |
twisti@4323 | 4121 | // First, dirty it. |
twisti@4323 | 4122 | __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty). |
twisti@4323 | 4123 | |
twisti@4323 | 4124 | int dirty_card_q_index_byte_offset = |
twisti@4323 | 4125 | in_bytes(JavaThread::dirty_card_queue_offset() + |
twisti@4323 | 4126 | PtrQueue::byte_offset_of_index()); |
twisti@4323 | 4127 | int dirty_card_q_buf_byte_offset = |
twisti@4323 | 4128 | in_bytes(JavaThread::dirty_card_queue_offset() + |
twisti@4323 | 4129 | PtrQueue::byte_offset_of_buf()); |
twisti@4323 | 4130 | __ bind(restart); |
twisti@4323 | 4131 | |
twisti@4323 | 4132 | // Load the index into the update buffer. PtrQueue::_index is |
twisti@4323 | 4133 | // a size_t so ld_ptr is appropriate here. |
twisti@4323 | 4134 | __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0); |
twisti@4323 | 4135 | |
twisti@4323 | 4136 | // index == 0? |
twisti@4323 | 4137 | __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); |
twisti@4323 | 4138 | |
twisti@4323 | 4139 | __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1); |
twisti@4323 | 4140 | __ sub(L0, oopSize, L0); |
twisti@4323 | 4141 | |
twisti@4323 | 4142 | __ st_ptr(O3, L1, L0); // [_buf + index] := I0 |
twisti@4323 | 4143 | // Use return-from-leaf |
twisti@4323 | 4144 | __ retl(); |
twisti@4323 | 4145 | __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset); |
twisti@4323 | 4146 | |
twisti@4323 | 4147 | __ bind(refill); |
twisti@4323 | 4148 | address handle_zero = |
twisti@4323 | 4149 | CAST_FROM_FN_PTR(address, |
twisti@4323 | 4150 | &DirtyCardQueueSet::handle_zero_index_for_thread); |
twisti@4323 | 4151 | // This should be rare enough that we can afford to save all the |
twisti@4323 | 4152 | // scratch registers that the calling context might be using. |
twisti@4323 | 4153 | __ mov(G1_scratch, L3); |
twisti@4323 | 4154 | __ mov(G3_scratch, L5); |
twisti@4323 | 4155 | // We need the value of O3 above (for the write into the buffer), so we |
twisti@4323 | 4156 | // save and restore it. |
twisti@4323 | 4157 | __ mov(O3, L6); |
twisti@4323 | 4158 | // Since the call will overwrite O7, we save and restore that, as well. |
twisti@4323 | 4159 | __ mov(O7, L4); |
twisti@4323 | 4160 | |
twisti@4323 | 4161 | __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread); |
twisti@4323 | 4162 | __ mov(L3, G1_scratch); |
twisti@4323 | 4163 | __ mov(L5, G3_scratch); |
twisti@4323 | 4164 | __ mov(L6, O3); |
twisti@4323 | 4165 | __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); |
twisti@4323 | 4166 | __ delayed()->mov(L4, O7); |
twisti@4323 | 4167 | |
twisti@4323 | 4168 | dirty_card_log_enqueue = start; |
twisti@4323 | 4169 | dirty_card_log_enqueue_end = __ pc(); |
twisti@4323 | 4170 | // XXX Should have a guarantee here about not going off the end! |
twisti@4323 | 4171 | // Does it already do so? Do an experiment... |
twisti@4323 | 4172 | |
twisti@4323 | 4173 | #undef __ |
twisti@4323 | 4174 | |
twisti@4323 | 4175 | } |
twisti@4323 | 4176 | |
twisti@4323 | 4177 | static inline void |
twisti@4323 | 4178 | generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) { |
twisti@4323 | 4179 | if (dirty_card_log_enqueue == 0) { |
twisti@4323 | 4180 | generate_dirty_card_log_enqueue(byte_map_base); |
twisti@4323 | 4181 | assert(dirty_card_log_enqueue != 0, "postcondition."); |
twisti@4323 | 4182 | if (G1SATBPrintStubs) { |
twisti@4323 | 4183 | tty->print_cr("Generated dirty_card enqueue:"); |
twisti@4323 | 4184 | Disassembler::decode((u_char*)dirty_card_log_enqueue, |
twisti@4323 | 4185 | dirty_card_log_enqueue_end, |
twisti@4323 | 4186 | tty); |
twisti@4323 | 4187 | } |
twisti@4323 | 4188 | } |
twisti@4323 | 4189 | } |
twisti@4323 | 4190 | |
twisti@4323 | 4191 | |
twisti@4323 | 4192 | void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) { |
twisti@4323 | 4193 | |
twisti@4323 | 4194 | Label filtered; |
twisti@4323 | 4195 | MacroAssembler* post_filter_masm = this; |
twisti@4323 | 4196 | |
twisti@4323 | 4197 | if (new_val == G0) return; |
twisti@4323 | 4198 | |
twisti@4323 | 4199 | G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set(); |
twisti@4323 | 4200 | assert(bs->kind() == BarrierSet::G1SATBCT || |
twisti@4323 | 4201 | bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier"); |
twisti@4323 | 4202 | |
twisti@4323 | 4203 | if (G1RSBarrierRegionFilter) { |
twisti@4323 | 4204 | xor3(store_addr, new_val, tmp); |
twisti@4323 | 4205 | #ifdef _LP64 |
twisti@4323 | 4206 | srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp); |
twisti@4323 | 4207 | #else |
twisti@4323 | 4208 | srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp); |
twisti@4323 | 4209 | #endif |
twisti@4323 | 4210 | |
twisti@4323 | 4211 | // XXX Should I predict this taken or not? Does it matter? |
twisti@4323 | 4212 | cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); |
twisti@4323 | 4213 | } |
twisti@4323 | 4214 | |
twisti@4323 | 4215 | // If the "store_addr" register is an "in" or "local" register, move it to |
twisti@4323 | 4216 | // a scratch reg so we can pass it as an argument. |
twisti@4323 | 4217 | bool use_scr = !(store_addr->is_global() || store_addr->is_out()); |
twisti@4323 | 4218 | // Pick a scratch register different from "tmp". |
twisti@4323 | 4219 | Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); |
twisti@4323 | 4220 | // Make sure we use up the delay slot! |
twisti@4323 | 4221 | if (use_scr) { |
twisti@4323 | 4222 | post_filter_masm->mov(store_addr, scr); |
twisti@4323 | 4223 | } else { |
twisti@4323 | 4224 | post_filter_masm->nop(); |
twisti@4323 | 4225 | } |
twisti@4323 | 4226 | generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); |
twisti@4323 | 4227 | save_frame(0); |
twisti@4323 | 4228 | call(dirty_card_log_enqueue); |
twisti@4323 | 4229 | if (use_scr) { |
twisti@4323 | 4230 | delayed()->mov(scr, O0); |
twisti@4323 | 4231 | } else { |
twisti@4323 | 4232 | delayed()->mov(store_addr->after_save(), O0); |
twisti@4323 | 4233 | } |
twisti@4323 | 4234 | restore(); |
twisti@4323 | 4235 | |
twisti@4323 | 4236 | bind(filtered); |
twisti@4323 | 4237 | } |
twisti@4323 | 4238 | |
jprovino@4542 | 4239 | #endif // INCLUDE_ALL_GCS |
twisti@4323 | 4240 | /////////////////////////////////////////////////////////////////////////////////// |
twisti@4323 | 4241 | |
twisti@4323 | 4242 | void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) { |
twisti@4323 | 4243 | // If we're writing constant NULL, we can skip the write barrier. |
twisti@4323 | 4244 | if (new_val == G0) return; |
twisti@4323 | 4245 | CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); |
twisti@4323 | 4246 | assert(bs->kind() == BarrierSet::CardTableModRef || |
twisti@4323 | 4247 | bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); |
twisti@4323 | 4248 | card_table_write(bs->byte_map_base, tmp, store_addr); |
twisti@4323 | 4249 | } |
twisti@4323 | 4250 | |
twisti@4323 | 4251 | void MacroAssembler::load_klass(Register src_oop, Register klass) { |
twisti@4323 | 4252 | // The number of bytes in this code is used by |
twisti@4323 | 4253 | // MachCallDynamicJavaNode::ret_addr_offset() |
twisti@4323 | 4254 | // if this changes, change that. |
twisti@4323 | 4255 | if (UseCompressedKlassPointers) { |
twisti@4323 | 4256 | lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass); |
twisti@4323 | 4257 | decode_klass_not_null(klass); |
twisti@4323 | 4258 | } else { |
twisti@4323 | 4259 | ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass); |
twisti@4323 | 4260 | } |
twisti@4323 | 4261 | } |
twisti@4323 | 4262 | |
twisti@4323 | 4263 | void MacroAssembler::store_klass(Register klass, Register dst_oop) { |
twisti@4323 | 4264 | if (UseCompressedKlassPointers) { |
twisti@4323 | 4265 | assert(dst_oop != klass, "not enough registers"); |
twisti@4323 | 4266 | encode_klass_not_null(klass); |
twisti@4323 | 4267 | st(klass, dst_oop, oopDesc::klass_offset_in_bytes()); |
twisti@4323 | 4268 | } else { |
twisti@4323 | 4269 | st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes()); |
twisti@4323 | 4270 | } |
twisti@4323 | 4271 | } |
twisti@4323 | 4272 | |
twisti@4323 | 4273 | void MacroAssembler::store_klass_gap(Register s, Register d) { |
twisti@4323 | 4274 | if (UseCompressedKlassPointers) { |
twisti@4323 | 4275 | assert(s != d, "not enough registers"); |
twisti@4323 | 4276 | st(s, d, oopDesc::klass_gap_offset_in_bytes()); |
twisti@4323 | 4277 | } |
twisti@4323 | 4278 | } |
twisti@4323 | 4279 | |
twisti@4323 | 4280 | void MacroAssembler::load_heap_oop(const Address& s, Register d) { |
twisti@4323 | 4281 | if (UseCompressedOops) { |
twisti@4323 | 4282 | lduw(s, d); |
twisti@4323 | 4283 | decode_heap_oop(d); |
twisti@4323 | 4284 | } else { |
twisti@4323 | 4285 | ld_ptr(s, d); |
twisti@4323 | 4286 | } |
twisti@4323 | 4287 | } |
twisti@4323 | 4288 | |
twisti@4323 | 4289 | void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { |
twisti@4323 | 4290 | if (UseCompressedOops) { |
twisti@4323 | 4291 | lduw(s1, s2, d); |
twisti@4323 | 4292 | decode_heap_oop(d, d); |
twisti@4323 | 4293 | } else { |
twisti@4323 | 4294 | ld_ptr(s1, s2, d); |
twisti@4323 | 4295 | } |
twisti@4323 | 4296 | } |
twisti@4323 | 4297 | |
twisti@4323 | 4298 | void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { |
twisti@4323 | 4299 | if (UseCompressedOops) { |
twisti@4323 | 4300 | lduw(s1, simm13a, d); |
twisti@4323 | 4301 | decode_heap_oop(d, d); |
twisti@4323 | 4302 | } else { |
twisti@4323 | 4303 | ld_ptr(s1, simm13a, d); |
twisti@4323 | 4304 | } |
twisti@4323 | 4305 | } |
twisti@4323 | 4306 | |
twisti@4323 | 4307 | void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) { |
twisti@4323 | 4308 | if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d); |
twisti@4323 | 4309 | else load_heap_oop(s1, s2.as_register(), d); |
twisti@4323 | 4310 | } |
twisti@4323 | 4311 | |
twisti@4323 | 4312 | void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { |
twisti@4323 | 4313 | if (UseCompressedOops) { |
twisti@4323 | 4314 | assert(s1 != d && s2 != d, "not enough registers"); |
twisti@4323 | 4315 | encode_heap_oop(d); |
twisti@4323 | 4316 | st(d, s1, s2); |
twisti@4323 | 4317 | } else { |
twisti@4323 | 4318 | st_ptr(d, s1, s2); |
twisti@4323 | 4319 | } |
twisti@4323 | 4320 | } |
twisti@4323 | 4321 | |
twisti@4323 | 4322 | void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { |
twisti@4323 | 4323 | if (UseCompressedOops) { |
twisti@4323 | 4324 | assert(s1 != d, "not enough registers"); |
twisti@4323 | 4325 | encode_heap_oop(d); |
twisti@4323 | 4326 | st(d, s1, simm13a); |
twisti@4323 | 4327 | } else { |
twisti@4323 | 4328 | st_ptr(d, s1, simm13a); |
twisti@4323 | 4329 | } |
twisti@4323 | 4330 | } |
twisti@4323 | 4331 | |
twisti@4323 | 4332 | void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { |
twisti@4323 | 4333 | if (UseCompressedOops) { |
twisti@4323 | 4334 | assert(a.base() != d, "not enough registers"); |
twisti@4323 | 4335 | encode_heap_oop(d); |
twisti@4323 | 4336 | st(d, a, offset); |
twisti@4323 | 4337 | } else { |
twisti@4323 | 4338 | st_ptr(d, a, offset); |
twisti@4323 | 4339 | } |
twisti@4323 | 4340 | } |
twisti@4323 | 4341 | |
twisti@4323 | 4342 | |
twisti@4323 | 4343 | void MacroAssembler::encode_heap_oop(Register src, Register dst) { |
twisti@4323 | 4344 | assert (UseCompressedOops, "must be compressed"); |
twisti@4323 | 4345 | assert (Universe::heap() != NULL, "java heap should be initialized"); |
twisti@4323 | 4346 | assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
twisti@4323 | 4347 | verify_oop(src); |
twisti@4323 | 4348 | if (Universe::narrow_oop_base() == NULL) { |
twisti@4323 | 4349 | srlx(src, LogMinObjAlignmentInBytes, dst); |
twisti@4323 | 4350 | return; |
twisti@4323 | 4351 | } |
twisti@4323 | 4352 | Label done; |
twisti@4323 | 4353 | if (src == dst) { |
twisti@4323 | 4354 | // optimize for frequent case src == dst |
twisti@4323 | 4355 | bpr(rc_nz, true, Assembler::pt, src, done); |
twisti@4323 | 4356 | delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken |
twisti@4323 | 4357 | bind(done); |
twisti@4323 | 4358 | srlx(src, LogMinObjAlignmentInBytes, dst); |
twisti@4323 | 4359 | } else { |
twisti@4323 | 4360 | bpr(rc_z, false, Assembler::pn, src, done); |
twisti@4323 | 4361 | delayed() -> mov(G0, dst); |
twisti@4323 | 4362 | // could be moved before branch, and annulate delay, |
twisti@4323 | 4363 | // but may add some unneeded work decoding null |
twisti@4323 | 4364 | sub(src, G6_heapbase, dst); |
twisti@4323 | 4365 | srlx(dst, LogMinObjAlignmentInBytes, dst); |
twisti@4323 | 4366 | bind(done); |
twisti@4323 | 4367 | } |
twisti@4323 | 4368 | } |
twisti@4323 | 4369 | |
twisti@4323 | 4370 | |
twisti@4323 | 4371 | void MacroAssembler::encode_heap_oop_not_null(Register r) { |
twisti@4323 | 4372 | assert (UseCompressedOops, "must be compressed"); |
twisti@4323 | 4373 | assert (Universe::heap() != NULL, "java heap should be initialized"); |
twisti@4323 | 4374 | assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
twisti@4323 | 4375 | verify_oop(r); |
twisti@4323 | 4376 | if (Universe::narrow_oop_base() != NULL) |
twisti@4323 | 4377 | sub(r, G6_heapbase, r); |
twisti@4323 | 4378 | srlx(r, LogMinObjAlignmentInBytes, r); |
twisti@4323 | 4379 | } |
twisti@4323 | 4380 | |
twisti@4323 | 4381 | void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) { |
twisti@4323 | 4382 | assert (UseCompressedOops, "must be compressed"); |
twisti@4323 | 4383 | assert (Universe::heap() != NULL, "java heap should be initialized"); |
twisti@4323 | 4384 | assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
twisti@4323 | 4385 | verify_oop(src); |
twisti@4323 | 4386 | if (Universe::narrow_oop_base() == NULL) { |
twisti@4323 | 4387 | srlx(src, LogMinObjAlignmentInBytes, dst); |
twisti@4323 | 4388 | } else { |
twisti@4323 | 4389 | sub(src, G6_heapbase, dst); |
twisti@4323 | 4390 | srlx(dst, LogMinObjAlignmentInBytes, dst); |
twisti@4323 | 4391 | } |
twisti@4323 | 4392 | } |
twisti@4323 | 4393 | |
twisti@4323 | 4394 | // Same algorithm as oops.inline.hpp decode_heap_oop. |
twisti@4323 | 4395 | void MacroAssembler::decode_heap_oop(Register src, Register dst) { |
twisti@4323 | 4396 | assert (UseCompressedOops, "must be compressed"); |
twisti@4323 | 4397 | assert (Universe::heap() != NULL, "java heap should be initialized"); |
twisti@4323 | 4398 | assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
twisti@4323 | 4399 | sllx(src, LogMinObjAlignmentInBytes, dst); |
twisti@4323 | 4400 | if (Universe::narrow_oop_base() != NULL) { |
twisti@4323 | 4401 | Label done; |
twisti@4323 | 4402 | bpr(rc_nz, true, Assembler::pt, dst, done); |
twisti@4323 | 4403 | delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken |
twisti@4323 | 4404 | bind(done); |
twisti@4323 | 4405 | } |
twisti@4323 | 4406 | verify_oop(dst); |
twisti@4323 | 4407 | } |
twisti@4323 | 4408 | |
twisti@4323 | 4409 | void MacroAssembler::decode_heap_oop_not_null(Register r) { |
twisti@4323 | 4410 | // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
twisti@4323 | 4411 | // pd_code_size_limit. |
twisti@4323 | 4412 | // Also do not verify_oop as this is called by verify_oop. |
twisti@4323 | 4413 | assert (UseCompressedOops, "must be compressed"); |
twisti@4323 | 4414 | assert (Universe::heap() != NULL, "java heap should be initialized"); |
twisti@4323 | 4415 | assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
twisti@4323 | 4416 | sllx(r, LogMinObjAlignmentInBytes, r); |
twisti@4323 | 4417 | if (Universe::narrow_oop_base() != NULL) |
twisti@4323 | 4418 | add(r, G6_heapbase, r); |
twisti@4323 | 4419 | } |
twisti@4323 | 4420 | |
twisti@4323 | 4421 | void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) { |
twisti@4323 | 4422 | // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
twisti@4323 | 4423 | // pd_code_size_limit. |
twisti@4323 | 4424 | // Also do not verify_oop as this is called by verify_oop. |
twisti@4323 | 4425 | assert (UseCompressedOops, "must be compressed"); |
twisti@4323 | 4426 | assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
twisti@4323 | 4427 | sllx(src, LogMinObjAlignmentInBytes, dst); |
twisti@4323 | 4428 | if (Universe::narrow_oop_base() != NULL) |
twisti@4323 | 4429 | add(dst, G6_heapbase, dst); |
twisti@4323 | 4430 | } |
twisti@4323 | 4431 | |
twisti@4323 | 4432 | void MacroAssembler::encode_klass_not_null(Register r) { |
twisti@4323 | 4433 | assert(Metaspace::is_initialized(), "metaspace should be initialized"); |
twisti@4323 | 4434 | assert (UseCompressedKlassPointers, "must be compressed"); |
twisti@4323 | 4435 | assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
twisti@4323 | 4436 | if (Universe::narrow_klass_base() != NULL) |
twisti@4323 | 4437 | sub(r, G6_heapbase, r); |
twisti@4323 | 4438 | srlx(r, LogKlassAlignmentInBytes, r); |
twisti@4323 | 4439 | } |
twisti@4323 | 4440 | |
twisti@4323 | 4441 | void MacroAssembler::encode_klass_not_null(Register src, Register dst) { |
twisti@4323 | 4442 | assert(Metaspace::is_initialized(), "metaspace should be initialized"); |
twisti@4323 | 4443 | assert (UseCompressedKlassPointers, "must be compressed"); |
twisti@4323 | 4444 | assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
twisti@4323 | 4445 | if (Universe::narrow_klass_base() == NULL) { |
twisti@4323 | 4446 | srlx(src, LogKlassAlignmentInBytes, dst); |
twisti@4323 | 4447 | } else { |
twisti@4323 | 4448 | sub(src, G6_heapbase, dst); |
twisti@4323 | 4449 | srlx(dst, LogKlassAlignmentInBytes, dst); |
twisti@4323 | 4450 | } |
twisti@4323 | 4451 | } |
twisti@4323 | 4452 | |
twisti@4323 | 4453 | void MacroAssembler::decode_klass_not_null(Register r) { |
twisti@4323 | 4454 | assert(Metaspace::is_initialized(), "metaspace should be initialized"); |
twisti@4323 | 4455 | // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
twisti@4323 | 4456 | // pd_code_size_limit. |
twisti@4323 | 4457 | assert (UseCompressedKlassPointers, "must be compressed"); |
twisti@4323 | 4458 | assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
twisti@4323 | 4459 | sllx(r, LogKlassAlignmentInBytes, r); |
twisti@4323 | 4460 | if (Universe::narrow_klass_base() != NULL) |
twisti@4323 | 4461 | add(r, G6_heapbase, r); |
twisti@4323 | 4462 | } |
twisti@4323 | 4463 | |
twisti@4323 | 4464 | void MacroAssembler::decode_klass_not_null(Register src, Register dst) { |
twisti@4323 | 4465 | assert(Metaspace::is_initialized(), "metaspace should be initialized"); |
twisti@4323 | 4466 | // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
twisti@4323 | 4467 | // pd_code_size_limit. |
twisti@4323 | 4468 | assert (UseCompressedKlassPointers, "must be compressed"); |
twisti@4323 | 4469 | assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
twisti@4323 | 4470 | sllx(src, LogKlassAlignmentInBytes, dst); |
twisti@4323 | 4471 | if (Universe::narrow_klass_base() != NULL) |
twisti@4323 | 4472 | add(dst, G6_heapbase, dst); |
twisti@4323 | 4473 | } |
twisti@4323 | 4474 | |
twisti@4323 | 4475 | void MacroAssembler::reinit_heapbase() { |
twisti@4323 | 4476 | if (UseCompressedOops || UseCompressedKlassPointers) { |
twisti@4323 | 4477 | AddressLiteral base(Universe::narrow_ptrs_base_addr()); |
twisti@4323 | 4478 | load_ptr_contents(base, G6_heapbase); |
twisti@4323 | 4479 | } |
twisti@4323 | 4480 | } |
twisti@4323 | 4481 | |
twisti@4323 | 4482 | // Compare char[] arrays aligned to 4 bytes. |
twisti@4323 | 4483 | void MacroAssembler::char_arrays_equals(Register ary1, Register ary2, |
twisti@4323 | 4484 | Register limit, Register result, |
twisti@4323 | 4485 | Register chr1, Register chr2, Label& Ldone) { |
twisti@4323 | 4486 | Label Lvector, Lloop; |
twisti@4323 | 4487 | assert(chr1 == result, "should be the same"); |
twisti@4323 | 4488 | |
twisti@4323 | 4489 | // Note: limit contains number of bytes (2*char_elements) != 0. |
twisti@4323 | 4490 | andcc(limit, 0x2, chr1); // trailing character ? |
twisti@4323 | 4491 | br(Assembler::zero, false, Assembler::pt, Lvector); |
twisti@4323 | 4492 | delayed()->nop(); |
twisti@4323 | 4493 | |
twisti@4323 | 4494 | // compare the trailing char |
twisti@4323 | 4495 | sub(limit, sizeof(jchar), limit); |
twisti@4323 | 4496 | lduh(ary1, limit, chr1); |
twisti@4323 | 4497 | lduh(ary2, limit, chr2); |
twisti@4323 | 4498 | cmp(chr1, chr2); |
twisti@4323 | 4499 | br(Assembler::notEqual, true, Assembler::pt, Ldone); |
twisti@4323 | 4500 | delayed()->mov(G0, result); // not equal |
twisti@4323 | 4501 | |
twisti@4323 | 4502 | // only one char ? |
twisti@4323 | 4503 | cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn); |
twisti@4323 | 4504 | delayed()->add(G0, 1, result); // zero-length arrays are equal |
twisti@4323 | 4505 | |
twisti@4323 | 4506 | // word by word compare, dont't need alignment check |
twisti@4323 | 4507 | bind(Lvector); |
twisti@4323 | 4508 | // Shift ary1 and ary2 to the end of the arrays, negate limit |
twisti@4323 | 4509 | add(ary1, limit, ary1); |
twisti@4323 | 4510 | add(ary2, limit, ary2); |
twisti@4323 | 4511 | neg(limit, limit); |
twisti@4323 | 4512 | |
twisti@4323 | 4513 | lduw(ary1, limit, chr1); |
twisti@4323 | 4514 | bind(Lloop); |
twisti@4323 | 4515 | lduw(ary2, limit, chr2); |
twisti@4323 | 4516 | cmp(chr1, chr2); |
twisti@4323 | 4517 | br(Assembler::notEqual, true, Assembler::pt, Ldone); |
twisti@4323 | 4518 | delayed()->mov(G0, result); // not equal |
twisti@4323 | 4519 | inccc(limit, 2*sizeof(jchar)); |
twisti@4323 | 4520 | // annul LDUW if branch is not taken to prevent access past end of array |
twisti@4323 | 4521 | br(Assembler::notZero, true, Assembler::pt, Lloop); |
twisti@4323 | 4522 | delayed()->lduw(ary1, limit, chr1); // hoisted |
twisti@4323 | 4523 | |
twisti@4323 | 4524 | // Caller should set it: |
twisti@4323 | 4525 | // add(G0, 1, result); // equals |
twisti@4323 | 4526 | } |
twisti@4323 | 4527 | |
twisti@4323 | 4528 | // Use BIS for zeroing (count is in bytes). |
twisti@4323 | 4529 | void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) { |
twisti@4323 | 4530 | assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing"); |
twisti@4323 | 4531 | Register end = count; |
twisti@4323 | 4532 | int cache_line_size = VM_Version::prefetch_data_size(); |
twisti@4323 | 4533 | // Minimum count when BIS zeroing can be used since |
twisti@4323 | 4534 | // it needs membar which is expensive. |
twisti@4323 | 4535 | int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit); |
twisti@4323 | 4536 | |
twisti@4323 | 4537 | Label small_loop; |
twisti@4323 | 4538 | // Check if count is negative (dead code) or zero. |
twisti@4323 | 4539 | // Note, count uses 64bit in 64 bit VM. |
twisti@4323 | 4540 | cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone); |
twisti@4323 | 4541 | |
twisti@4323 | 4542 | // Use BIS zeroing only for big arrays since it requires membar. |
twisti@4323 | 4543 | if (Assembler::is_simm13(block_zero_size)) { // < 4096 |
twisti@4323 | 4544 | cmp(count, block_zero_size); |
twisti@4323 | 4545 | } else { |
twisti@4323 | 4546 | set(block_zero_size, temp); |
twisti@4323 | 4547 | cmp(count, temp); |
twisti@4323 | 4548 | } |
twisti@4323 | 4549 | br(Assembler::lessUnsigned, false, Assembler::pt, small_loop); |
twisti@4323 | 4550 | delayed()->add(to, count, end); |
twisti@4323 | 4551 | |
twisti@4323 | 4552 | // Note: size is >= three (32 bytes) cache lines. |
twisti@4323 | 4553 | |
twisti@4323 | 4554 | // Clean the beginning of space up to next cache line. |
twisti@4323 | 4555 | for (int offs = 0; offs < cache_line_size; offs += 8) { |
twisti@4323 | 4556 | stx(G0, to, offs); |
twisti@4323 | 4557 | } |
twisti@4323 | 4558 | |
twisti@4323 | 4559 | // align to next cache line |
twisti@4323 | 4560 | add(to, cache_line_size, to); |
twisti@4323 | 4561 | and3(to, -cache_line_size, to); |
twisti@4323 | 4562 | |
twisti@4323 | 4563 | // Note: size left >= two (32 bytes) cache lines. |
twisti@4323 | 4564 | |
twisti@4323 | 4565 | // BIS should not be used to zero tail (64 bytes) |
twisti@4323 | 4566 | // to avoid zeroing a header of the following object. |
twisti@4323 | 4567 | sub(end, (cache_line_size*2)-8, end); |
twisti@4323 | 4568 | |
twisti@4323 | 4569 | Label bis_loop; |
twisti@4323 | 4570 | bind(bis_loop); |
twisti@4323 | 4571 | stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); |
twisti@4323 | 4572 | add(to, cache_line_size, to); |
twisti@4323 | 4573 | cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop); |
twisti@4323 | 4574 | |
twisti@4323 | 4575 | // BIS needs membar. |
twisti@4323 | 4576 | membar(Assembler::StoreLoad); |
twisti@4323 | 4577 | |
twisti@4323 | 4578 | add(end, (cache_line_size*2)-8, end); // restore end |
twisti@4323 | 4579 | cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone); |
twisti@4323 | 4580 | |
twisti@4323 | 4581 | // Clean the tail. |
twisti@4323 | 4582 | bind(small_loop); |
twisti@4323 | 4583 | stx(G0, to, 0); |
twisti@4323 | 4584 | add(to, 8, to); |
twisti@4323 | 4585 | cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop); |
twisti@4323 | 4586 | nop(); // Separate short branches |
twisti@4323 | 4587 | } |