Tue, 17 Oct 2017 12:58:25 +0800
merge
aoqi@0 | 1 | /* |
aoqi@0 | 2 | * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
aoqi@0 | 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
aoqi@0 | 4 | * |
aoqi@0 | 5 | * This code is free software; you can redistribute it and/or modify it |
aoqi@0 | 6 | * under the terms of the GNU General Public License version 2 only, as |
aoqi@0 | 7 | * published by the Free Software Foundation. |
aoqi@0 | 8 | * |
aoqi@0 | 9 | * This code is distributed in the hope that it will be useful, but WITHOUT |
aoqi@0 | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
aoqi@0 | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
aoqi@0 | 12 | * version 2 for more details (a copy is included in the LICENSE file that |
aoqi@0 | 13 | * accompanied this code). |
aoqi@0 | 14 | * |
aoqi@0 | 15 | * You should have received a copy of the GNU General Public License version |
aoqi@0 | 16 | * 2 along with this work; if not, write to the Free Software Foundation, |
aoqi@0 | 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
aoqi@0 | 18 | * |
aoqi@0 | 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
aoqi@0 | 20 | * or visit www.oracle.com if you need additional information or have any |
aoqi@0 | 21 | * questions. |
aoqi@0 | 22 | * |
aoqi@0 | 23 | */ |
aoqi@0 | 24 | |
aoqi@0 | 25 | #include "precompiled.hpp" |
aoqi@0 | 26 | #include "asm/macroAssembler.inline.hpp" |
aoqi@0 | 27 | #include "memory/resourceArea.hpp" |
aoqi@0 | 28 | #include "runtime/java.hpp" |
aoqi@0 | 29 | #include "runtime/stubCodeGenerator.hpp" |
aoqi@0 | 30 | #include "vm_version_sparc.hpp" |
aoqi@0 | 31 | #ifdef TARGET_OS_FAMILY_linux |
aoqi@0 | 32 | # include "os_linux.inline.hpp" |
aoqi@0 | 33 | #endif |
aoqi@0 | 34 | #ifdef TARGET_OS_FAMILY_solaris |
aoqi@0 | 35 | # include "os_solaris.inline.hpp" |
aoqi@0 | 36 | #endif |
aoqi@0 | 37 | |
aoqi@0 | 38 | int VM_Version::_features = VM_Version::unknown_m; |
aoqi@0 | 39 | const char* VM_Version::_features_str = ""; |
iveresov@7767 | 40 | unsigned int VM_Version::_L2_data_cache_line_size = 0; |
aoqi@0 | 41 | |
aoqi@0 | 42 | void VM_Version::initialize() { |
aoqi@0 | 43 | _features = determine_features(); |
aoqi@0 | 44 | PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
aoqi@0 | 45 | PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
aoqi@0 | 46 | PrefetchFieldsAhead = prefetch_fields_ahead(); |
aoqi@0 | 47 | |
aoqi@0 | 48 | assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); |
aoqi@0 | 49 | if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
aoqi@0 | 50 | if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; |
aoqi@0 | 51 | |
aoqi@0 | 52 | // Allocation prefetch settings |
aoqi@0 | 53 | intx cache_line_size = prefetch_data_size(); |
aoqi@0 | 54 | if( cache_line_size > AllocatePrefetchStepSize ) |
aoqi@0 | 55 | AllocatePrefetchStepSize = cache_line_size; |
aoqi@0 | 56 | |
aoqi@0 | 57 | assert(AllocatePrefetchLines > 0, "invalid value"); |
aoqi@0 | 58 | if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
aoqi@0 | 59 | AllocatePrefetchLines = 3; |
aoqi@0 | 60 | assert(AllocateInstancePrefetchLines > 0, "invalid value"); |
aoqi@0 | 61 | if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM |
aoqi@0 | 62 | AllocateInstancePrefetchLines = 1; |
aoqi@0 | 63 | |
aoqi@0 | 64 | AllocatePrefetchDistance = allocate_prefetch_distance(); |
aoqi@0 | 65 | AllocatePrefetchStyle = allocate_prefetch_style(); |
aoqi@0 | 66 | |
aoqi@0 | 67 | assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && |
aoqi@0 | 68 | (AllocatePrefetchDistance > 0), "invalid value"); |
aoqi@0 | 69 | if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || |
aoqi@0 | 70 | (AllocatePrefetchDistance <= 0)) { |
aoqi@0 | 71 | AllocatePrefetchDistance = AllocatePrefetchStepSize; |
aoqi@0 | 72 | } |
aoqi@0 | 73 | |
aoqi@0 | 74 | if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
aoqi@0 | 75 | warning("BIS instructions are not available on this CPU"); |
aoqi@0 | 76 | FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); |
aoqi@0 | 77 | } |
aoqi@0 | 78 | |
aoqi@0 | 79 | guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
aoqi@0 | 80 | |
aoqi@0 | 81 | assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); |
aoqi@0 | 82 | if (ArraycopySrcPrefetchDistance >= 4096) |
aoqi@0 | 83 | ArraycopySrcPrefetchDistance = 4064; |
aoqi@0 | 84 | assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); |
aoqi@0 | 85 | if (ArraycopyDstPrefetchDistance >= 4096) |
aoqi@0 | 86 | ArraycopyDstPrefetchDistance = 4064; |
aoqi@0 | 87 | |
aoqi@0 | 88 | UseSSE = 0; // Only on x86 and x64 |
aoqi@0 | 89 | |
aoqi@0 | 90 | _supports_cx8 = has_v9(); |
aoqi@0 | 91 | _supports_atomic_getset4 = true; // swap instruction |
aoqi@0 | 92 | |
aoqi@0 | 93 | // There are Fujitsu Sparc64 CPUs which support blk_init as well so |
aoqi@0 | 94 | // we have to take this check out of the 'is_niagara()' block below. |
aoqi@0 | 95 | if (has_blk_init()) { |
aoqi@0 | 96 | // When using CMS or G1, we cannot use memset() in BOT updates |
aoqi@0 | 97 | // because the sun4v/CMT version in libc_psr uses BIS which |
aoqi@0 | 98 | // exposes "phantom zeros" to concurrent readers. See 6948537. |
aoqi@0 | 99 | if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { |
aoqi@0 | 100 | FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
aoqi@0 | 101 | } |
aoqi@0 | 102 | // Issue a stern warning if the user has explicitly set |
aoqi@0 | 103 | // UseMemSetInBOT (it is known to cause issues), but allow |
aoqi@0 | 104 | // use for experimentation and debugging. |
aoqi@0 | 105 | if (UseConcMarkSweepGC || UseG1GC) { |
aoqi@0 | 106 | if (UseMemSetInBOT) { |
aoqi@0 | 107 | assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); |
aoqi@0 | 108 | warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" |
aoqi@0 | 109 | " on sun4v; please understand that you are using at your own risk!"); |
aoqi@0 | 110 | } |
aoqi@0 | 111 | } |
aoqi@0 | 112 | } |
aoqi@0 | 113 | |
aoqi@0 | 114 | if (is_niagara()) { |
aoqi@0 | 115 | // Indirect branch is the same cost as direct |
aoqi@0 | 116 | if (FLAG_IS_DEFAULT(UseInlineCaches)) { |
aoqi@0 | 117 | FLAG_SET_DEFAULT(UseInlineCaches, false); |
aoqi@0 | 118 | } |
aoqi@0 | 119 | // Align loops on a single instruction boundary. |
aoqi@0 | 120 | if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |
aoqi@0 | 121 | FLAG_SET_DEFAULT(OptoLoopAlignment, 4); |
aoqi@0 | 122 | } |
aoqi@0 | 123 | #ifdef _LP64 |
aoqi@0 | 124 | // 32-bit oops don't make sense for the 64-bit VM on sparc |
aoqi@0 | 125 | // since the 32-bit VM has the same registers and smaller objects. |
aoqi@0 | 126 | Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
aoqi@0 | 127 | Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
aoqi@0 | 128 | #endif // _LP64 |
aoqi@0 | 129 | #ifdef COMPILER2 |
aoqi@0 | 130 | // Indirect branch is the same cost as direct |
aoqi@0 | 131 | if (FLAG_IS_DEFAULT(UseJumpTables)) { |
aoqi@0 | 132 | FLAG_SET_DEFAULT(UseJumpTables, true); |
aoqi@0 | 133 | } |
aoqi@0 | 134 | // Single-issue, so entry and loop tops are |
aoqi@0 | 135 | // aligned on a single instruction boundary |
aoqi@0 | 136 | if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { |
aoqi@0 | 137 | FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
aoqi@0 | 138 | } |
aoqi@0 | 139 | if (is_niagara_plus()) { |
aoqi@0 | 140 | if (has_blk_init() && UseTLAB && |
aoqi@0 | 141 | FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
aoqi@0 | 142 | // Use BIS instruction for TLAB allocation prefetch. |
aoqi@0 | 143 | FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); |
aoqi@0 | 144 | if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
aoqi@0 | 145 | FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); |
aoqi@0 | 146 | } |
aoqi@0 | 147 | if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
aoqi@0 | 148 | // Use smaller prefetch distance with BIS |
aoqi@0 | 149 | FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
aoqi@0 | 150 | } |
aoqi@0 | 151 | } |
aoqi@0 | 152 | if (is_T4()) { |
aoqi@0 | 153 | // Double number of prefetched cache lines on T4 |
aoqi@0 | 154 | // since L2 cache line size is smaller (32 bytes). |
aoqi@0 | 155 | if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { |
aoqi@0 | 156 | FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); |
aoqi@0 | 157 | } |
aoqi@0 | 158 | if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { |
aoqi@0 | 159 | FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); |
aoqi@0 | 160 | } |
aoqi@0 | 161 | } |
aoqi@0 | 162 | if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
aoqi@0 | 163 | // Use different prefetch distance without BIS |
aoqi@0 | 164 | FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
aoqi@0 | 165 | } |
aoqi@0 | 166 | if (AllocatePrefetchInstr == 1) { |
aoqi@0 | 167 | // Need a space at the end of TLAB for BIS since it |
aoqi@0 | 168 | // will fault when accessing memory outside of heap. |
aoqi@0 | 169 | |
aoqi@0 | 170 | // +1 for rounding up to next cache line, +1 to be safe |
aoqi@0 | 171 | int lines = AllocatePrefetchLines + 2; |
aoqi@0 | 172 | int step_size = AllocatePrefetchStepSize; |
aoqi@0 | 173 | int distance = AllocatePrefetchDistance; |
aoqi@0 | 174 | _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; |
aoqi@0 | 175 | } |
aoqi@0 | 176 | } |
aoqi@0 | 177 | #endif |
aoqi@0 | 178 | } |
aoqi@0 | 179 | |
aoqi@0 | 180 | // Use hardware population count instruction if available. |
aoqi@0 | 181 | if (has_hardware_popc()) { |
aoqi@0 | 182 | if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
aoqi@0 | 183 | FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
aoqi@0 | 184 | } |
aoqi@0 | 185 | } else if (UsePopCountInstruction) { |
aoqi@0 | 186 | warning("POPC instruction is not available on this CPU"); |
aoqi@0 | 187 | FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
aoqi@0 | 188 | } |
aoqi@0 | 189 | |
aoqi@0 | 190 | // T4 and newer Sparc cpus have new compare and branch instruction. |
aoqi@0 | 191 | if (has_cbcond()) { |
aoqi@0 | 192 | if (FLAG_IS_DEFAULT(UseCBCond)) { |
aoqi@0 | 193 | FLAG_SET_DEFAULT(UseCBCond, true); |
aoqi@0 | 194 | } |
aoqi@0 | 195 | } else if (UseCBCond) { |
aoqi@0 | 196 | warning("CBCOND instruction is not available on this CPU"); |
aoqi@0 | 197 | FLAG_SET_DEFAULT(UseCBCond, false); |
aoqi@0 | 198 | } |
aoqi@0 | 199 | |
aoqi@0 | 200 | assert(BlockZeroingLowLimit > 0, "invalid value"); |
iveresov@7135 | 201 | if (has_block_zeroing() && cache_line_size > 0) { |
aoqi@0 | 202 | if (FLAG_IS_DEFAULT(UseBlockZeroing)) { |
aoqi@0 | 203 | FLAG_SET_DEFAULT(UseBlockZeroing, true); |
aoqi@0 | 204 | } |
aoqi@0 | 205 | } else if (UseBlockZeroing) { |
aoqi@0 | 206 | warning("BIS zeroing instructions are not available on this CPU"); |
aoqi@0 | 207 | FLAG_SET_DEFAULT(UseBlockZeroing, false); |
aoqi@0 | 208 | } |
aoqi@0 | 209 | |
aoqi@0 | 210 | assert(BlockCopyLowLimit > 0, "invalid value"); |
iveresov@7135 | 211 | if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache |
aoqi@0 | 212 | if (FLAG_IS_DEFAULT(UseBlockCopy)) { |
aoqi@0 | 213 | FLAG_SET_DEFAULT(UseBlockCopy, true); |
aoqi@0 | 214 | } |
aoqi@0 | 215 | } else if (UseBlockCopy) { |
aoqi@0 | 216 | warning("BIS instructions are not available or expensive on this CPU"); |
aoqi@0 | 217 | FLAG_SET_DEFAULT(UseBlockCopy, false); |
aoqi@0 | 218 | } |
aoqi@0 | 219 | |
aoqi@0 | 220 | #ifdef COMPILER2 |
aoqi@0 | 221 | // T4 and newer Sparc cpus have fast RDPC. |
aoqi@0 | 222 | if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { |
aoqi@0 | 223 | FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
aoqi@0 | 224 | } |
aoqi@0 | 225 | |
aoqi@0 | 226 | // Currently not supported anywhere. |
aoqi@0 | 227 | FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
aoqi@0 | 228 | |
aoqi@0 | 229 | MaxVectorSize = 8; |
aoqi@0 | 230 | |
aoqi@0 | 231 | assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
aoqi@0 | 232 | #endif |
aoqi@0 | 233 | |
aoqi@0 | 234 | assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
aoqi@0 | 235 | assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
aoqi@0 | 236 | |
aoqi@0 | 237 | char buf[512]; |
kvn@7027 | 238 | jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
aoqi@0 | 239 | (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
aoqi@0 | 240 | (has_hardware_popc() ? ", popc" : ""), |
aoqi@0 | 241 | (has_vis1() ? ", vis1" : ""), |
aoqi@0 | 242 | (has_vis2() ? ", vis2" : ""), |
aoqi@0 | 243 | (has_vis3() ? ", vis3" : ""), |
aoqi@0 | 244 | (has_blk_init() ? ", blk_init" : ""), |
aoqi@0 | 245 | (has_cbcond() ? ", cbcond" : ""), |
aoqi@0 | 246 | (has_aes() ? ", aes" : ""), |
kvn@7027 | 247 | (has_sha1() ? ", sha1" : ""), |
kvn@7027 | 248 | (has_sha256() ? ", sha256" : ""), |
kvn@7027 | 249 | (has_sha512() ? ", sha512" : ""), |
aoqi@0 | 250 | (is_ultra3() ? ", ultra3" : ""), |
aoqi@0 | 251 | (is_sun4v() ? ", sun4v" : ""), |
aoqi@0 | 252 | (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), |
aoqi@0 | 253 | (is_sparc64() ? ", sparc64" : ""), |
aoqi@0 | 254 | (!has_hardware_mul32() ? ", no-mul32" : ""), |
aoqi@0 | 255 | (!has_hardware_div32() ? ", no-div32" : ""), |
aoqi@0 | 256 | (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
aoqi@0 | 257 | |
aoqi@0 | 258 | // buf is started with ", " or is empty |
aoqi@0 | 259 | _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); |
aoqi@0 | 260 | |
aoqi@0 | 261 | // UseVIS is set to the smallest of what hardware supports and what |
aoqi@0 | 262 | // the command line requires. I.e., you cannot set UseVIS to 3 on |
aoqi@0 | 263 | // older UltraSparc which do not support it. |
aoqi@0 | 264 | if (UseVIS > 3) UseVIS=3; |
aoqi@0 | 265 | if (UseVIS < 0) UseVIS=0; |
aoqi@0 | 266 | if (!has_vis3()) // Drop to 2 if no VIS3 support |
aoqi@0 | 267 | UseVIS = MIN2((intx)2,UseVIS); |
aoqi@0 | 268 | if (!has_vis2()) // Drop to 1 if no VIS2 support |
aoqi@0 | 269 | UseVIS = MIN2((intx)1,UseVIS); |
aoqi@0 | 270 | if (!has_vis1()) // Drop to 0 if no VIS1 support |
aoqi@0 | 271 | UseVIS = 0; |
aoqi@0 | 272 | |
aoqi@0 | 273 | // SPARC T4 and above should have support for AES instructions |
aoqi@0 | 274 | if (has_aes()) { |
aoqi@0 | 275 | if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3 |
aoqi@0 | 276 | if (FLAG_IS_DEFAULT(UseAES)) { |
aoqi@0 | 277 | FLAG_SET_DEFAULT(UseAES, true); |
aoqi@0 | 278 | } |
aoqi@0 | 279 | if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
aoqi@0 | 280 | FLAG_SET_DEFAULT(UseAESIntrinsics, true); |
aoqi@0 | 281 | } |
aoqi@0 | 282 | // we disable both the AES flags if either of them is disabled on the command line |
aoqi@0 | 283 | if (!UseAES || !UseAESIntrinsics) { |
aoqi@0 | 284 | FLAG_SET_DEFAULT(UseAES, false); |
aoqi@0 | 285 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
aoqi@0 | 286 | } |
aoqi@0 | 287 | } else { |
aoqi@0 | 288 | if (UseAES || UseAESIntrinsics) { |
aoqi@0 | 289 | warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
aoqi@0 | 290 | if (UseAES) { |
aoqi@0 | 291 | FLAG_SET_DEFAULT(UseAES, false); |
aoqi@0 | 292 | } |
aoqi@0 | 293 | if (UseAESIntrinsics) { |
aoqi@0 | 294 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
aoqi@0 | 295 | } |
aoqi@0 | 296 | } |
aoqi@0 | 297 | } |
aoqi@0 | 298 | } else if (UseAES || UseAESIntrinsics) { |
aoqi@0 | 299 | warning("AES instructions are not available on this CPU"); |
aoqi@0 | 300 | if (UseAES) { |
aoqi@0 | 301 | FLAG_SET_DEFAULT(UseAES, false); |
aoqi@0 | 302 | } |
aoqi@0 | 303 | if (UseAESIntrinsics) { |
aoqi@0 | 304 | FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
aoqi@0 | 305 | } |
aoqi@0 | 306 | } |
aoqi@0 | 307 | |
kvn@7027 | 308 | // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times |
kvn@7027 | 309 | if (has_sha1() || has_sha256() || has_sha512()) { |
kvn@7027 | 310 | if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions |
kvn@7027 | 311 | if (FLAG_IS_DEFAULT(UseSHA)) { |
kvn@7027 | 312 | FLAG_SET_DEFAULT(UseSHA, true); |
kvn@7027 | 313 | } |
kvn@7027 | 314 | } else { |
kvn@7027 | 315 | if (UseSHA) { |
kvn@7027 | 316 | warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); |
kvn@7027 | 317 | FLAG_SET_DEFAULT(UseSHA, false); |
kvn@7027 | 318 | } |
kvn@7027 | 319 | } |
kvn@7027 | 320 | } else if (UseSHA) { |
kvn@7027 | 321 | warning("SHA instructions are not available on this CPU"); |
kvn@7027 | 322 | FLAG_SET_DEFAULT(UseSHA, false); |
kvn@7027 | 323 | } |
kvn@7027 | 324 | |
kvn@7027 | 325 | if (!UseSHA) { |
kvn@7027 | 326 | FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
kvn@7027 | 327 | FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
kvn@7027 | 328 | FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
kvn@7027 | 329 | } else { |
kvn@7027 | 330 | if (has_sha1()) { |
kvn@7027 | 331 | if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { |
kvn@7027 | 332 | FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); |
kvn@7027 | 333 | } |
kvn@7027 | 334 | } else if (UseSHA1Intrinsics) { |
kvn@7027 | 335 | warning("SHA1 instruction is not available on this CPU."); |
kvn@7027 | 336 | FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
kvn@7027 | 337 | } |
kvn@7027 | 338 | if (has_sha256()) { |
kvn@7027 | 339 | if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { |
kvn@7027 | 340 | FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); |
kvn@7027 | 341 | } |
kvn@7027 | 342 | } else if (UseSHA256Intrinsics) { |
kvn@7027 | 343 | warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU."); |
kvn@7027 | 344 | FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
kvn@7027 | 345 | } |
kvn@7027 | 346 | |
kvn@7027 | 347 | if (has_sha512()) { |
kvn@7027 | 348 | if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { |
kvn@7027 | 349 | FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); |
kvn@7027 | 350 | } |
kvn@7027 | 351 | } else if (UseSHA512Intrinsics) { |
kvn@7027 | 352 | warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU."); |
kvn@7027 | 353 | FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
kvn@7027 | 354 | } |
kvn@7027 | 355 | if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
kvn@7027 | 356 | FLAG_SET_DEFAULT(UseSHA, false); |
kvn@7027 | 357 | } |
kvn@7027 | 358 | } |
kvn@7027 | 359 | |
aoqi@0 | 360 | if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
aoqi@0 | 361 | (cache_line_size > ContendedPaddingWidth)) |
aoqi@0 | 362 | ContendedPaddingWidth = cache_line_size; |
aoqi@0 | 363 | |
aoqi@0 | 364 | #ifndef PRODUCT |
aoqi@0 | 365 | if (PrintMiscellaneous && Verbose) { |
iveresov@7767 | 366 | tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); |
aoqi@0 | 367 | tty->print("Allocation"); |
aoqi@0 | 368 | if (AllocatePrefetchStyle <= 0) { |
aoqi@0 | 369 | tty->print_cr(": no prefetching"); |
aoqi@0 | 370 | } else { |
aoqi@0 | 371 | tty->print(" prefetching: "); |
aoqi@0 | 372 | if (AllocatePrefetchInstr == 0) { |
aoqi@0 | 373 | tty->print("PREFETCH"); |
aoqi@0 | 374 | } else if (AllocatePrefetchInstr == 1) { |
aoqi@0 | 375 | tty->print("BIS"); |
aoqi@0 | 376 | } |
aoqi@0 | 377 | if (AllocatePrefetchLines > 1) { |
aoqi@0 | 378 | tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
aoqi@0 | 379 | } else { |
aoqi@0 | 380 | tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
aoqi@0 | 381 | } |
aoqi@0 | 382 | } |
aoqi@0 | 383 | if (PrefetchCopyIntervalInBytes > 0) { |
aoqi@0 | 384 | tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
aoqi@0 | 385 | } |
aoqi@0 | 386 | if (PrefetchScanIntervalInBytes > 0) { |
aoqi@0 | 387 | tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
aoqi@0 | 388 | } |
aoqi@0 | 389 | if (PrefetchFieldsAhead > 0) { |
aoqi@0 | 390 | tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
aoqi@0 | 391 | } |
aoqi@0 | 392 | if (ContendedPaddingWidth > 0) { |
aoqi@0 | 393 | tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
aoqi@0 | 394 | } |
aoqi@0 | 395 | } |
aoqi@0 | 396 | #endif // PRODUCT |
aoqi@0 | 397 | } |
aoqi@0 | 398 | |
aoqi@0 | 399 | void VM_Version::print_features() { |
aoqi@0 | 400 | tty->print_cr("Version:%s", cpu_features()); |
aoqi@0 | 401 | } |
aoqi@0 | 402 | |
aoqi@0 | 403 | int VM_Version::determine_features() { |
aoqi@0 | 404 | if (UseV8InstrsOnly) { |
aoqi@0 | 405 | NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) |
aoqi@0 | 406 | return generic_v8_m; |
aoqi@0 | 407 | } |
aoqi@0 | 408 | |
aoqi@0 | 409 | int features = platform_features(unknown_m); // platform_features() is os_arch specific |
aoqi@0 | 410 | |
aoqi@0 | 411 | if (features == unknown_m) { |
aoqi@0 | 412 | features = generic_v9_m; |
aoqi@0 | 413 | warning("Cannot recognize SPARC version. Default to V9"); |
aoqi@0 | 414 | } |
aoqi@0 | 415 | |
aoqi@0 | 416 | assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
aoqi@0 | 417 | if (UseNiagaraInstrs) { // Force code generation for Niagara |
aoqi@0 | 418 | if (is_T_family(features)) { |
aoqi@0 | 419 | // Happy to accomodate... |
aoqi@0 | 420 | } else { |
aoqi@0 | 421 | NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) |
aoqi@0 | 422 | features |= T_family_m; |
aoqi@0 | 423 | } |
aoqi@0 | 424 | } else { |
aoqi@0 | 425 | if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
aoqi@0 | 426 | NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
aoqi@0 | 427 | features &= ~(T_family_m | T1_model_m); |
aoqi@0 | 428 | } else { |
aoqi@0 | 429 | // Happy to accomodate... |
aoqi@0 | 430 | } |
aoqi@0 | 431 | } |
aoqi@0 | 432 | |
aoqi@0 | 433 | return features; |
aoqi@0 | 434 | } |
aoqi@0 | 435 | |
aoqi@0 | 436 | static int saved_features = 0; |
aoqi@0 | 437 | |
aoqi@0 | 438 | void VM_Version::allow_all() { |
aoqi@0 | 439 | saved_features = _features; |
aoqi@0 | 440 | _features = all_features_m; |
aoqi@0 | 441 | } |
aoqi@0 | 442 | |
aoqi@0 | 443 | void VM_Version::revert() { |
aoqi@0 | 444 | _features = saved_features; |
aoqi@0 | 445 | } |
aoqi@0 | 446 | |
aoqi@0 | 447 | unsigned int VM_Version::calc_parallel_worker_threads() { |
aoqi@0 | 448 | unsigned int result; |
aoqi@0 | 449 | if (is_M_series()) { |
aoqi@0 | 450 | // for now, use same gc thread calculation for M-series as for niagara-plus |
aoqi@0 | 451 | // in future, we may want to tweak parameters for nof_parallel_worker_thread |
aoqi@0 | 452 | result = nof_parallel_worker_threads(5, 16, 8); |
aoqi@0 | 453 | } else if (is_niagara_plus()) { |
aoqi@0 | 454 | result = nof_parallel_worker_threads(5, 16, 8); |
aoqi@0 | 455 | } else { |
aoqi@0 | 456 | result = nof_parallel_worker_threads(5, 8, 8); |
aoqi@0 | 457 | } |
aoqi@0 | 458 | return result; |
aoqi@0 | 459 | } |