Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
Merge
Tue, 13 Apr 2010 13:01:37 -0700
- author
- jrose
- date
- Tue, 13 Apr 2010 13:01:37 -0700
- changeset 1806
- fc3cd2277dc7
- parent 1797
- e4c77b879561
- parent 1805
- 213fbcf54799
- child 1807
- e16cca0aa5e1
- child 1812
- ef74d6d1ac1e
Merge
1.1 --- a/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Fri Apr 09 15:01:49 2010 -0700 1.2 +++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Tue Apr 13 13:01:37 2010 -0700 1.3 @@ -1728,9 +1728,13 @@ 1.4 ShouldNotReachHere(); 1.5 } 1.6 } else if (code == lir_cmp_l2i) { 1.7 +#ifdef _LP64 1.8 + __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); 1.9 +#else 1.10 __ lcmp(left->as_register_hi(), left->as_register_lo(), 1.11 right->as_register_hi(), right->as_register_lo(), 1.12 dst->as_register()); 1.13 +#endif 1.14 } else { 1.15 ShouldNotReachHere(); 1.16 } 1.17 @@ -2849,7 +2853,7 @@ 1.18 1.19 1.20 void LIR_Assembler::align_backward_branch_target() { 1.21 - __ align(16); 1.22 + __ align(OptoLoopAlignment); 1.23 } 1.24 1.25
2.1 --- a/src/cpu/sparc/vm/c2_globals_sparc.hpp Fri Apr 09 15:01:49 2010 -0700 2.2 +++ b/src/cpu/sparc/vm/c2_globals_sparc.hpp Tue Apr 13 13:01:37 2010 -0700 2.3 @@ -60,9 +60,6 @@ 2.4 define_pd_global(intx, INTPRESSURE, 48); // large register set 2.5 define_pd_global(intx, InteriorEntryAlignment, 16); // = CodeEntryAlignment 2.6 define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K)); 2.7 -// The default setting 16/16 seems to work best. 2.8 -// (For _228_jack 16/16 is 2% better than 4/4, 16/4, 32/32, 32/16, or 16/32.) 2.9 -define_pd_global(intx, OptoLoopAlignment, 16); // = 4*wordSize 2.10 define_pd_global(intx, RegisterCostAreaRatio, 12000); 2.11 define_pd_global(bool, UseTLAB, true); 2.12 define_pd_global(bool, ResizeTLAB, true);
3.1 --- a/src/cpu/sparc/vm/globals_sparc.hpp Fri Apr 09 15:01:49 2010 -0700 3.2 +++ b/src/cpu/sparc/vm/globals_sparc.hpp Tue Apr 13 13:01:37 2010 -0700 3.3 @@ -40,6 +40,9 @@ 3.4 define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs past to check cast 3.5 3.6 define_pd_global(intx, CodeEntryAlignment, 32); 3.7 +// The default setting 16/16 seems to work best. 3.8 +// (For _228_jack 16/16 is 2% better than 4/4, 16/4, 32/32, 32/16, or 16/32.) 3.9 +define_pd_global(intx, OptoLoopAlignment, 16); // = 4*wordSize 3.10 define_pd_global(intx, InlineFrequencyCount, 50); // we can use more inlining on the SPARC 3.11 define_pd_global(intx, InlineSmallCode, 1500); 3.12 #ifdef _LP64
4.1 --- a/src/cpu/sparc/vm/sparc.ad Fri Apr 09 15:01:49 2010 -0700 4.2 +++ b/src/cpu/sparc/vm/sparc.ad Tue Apr 13 13:01:37 2010 -0700 4.3 @@ -471,6 +471,9 @@ 4.4 source %{ 4.5 #define __ _masm. 4.6 4.7 +// Block initializing store 4.8 +#define ASI_BLK_INIT_QUAD_LDD_P 0xE2 4.9 + 4.10 // tertiary op of a LoadP or StoreP encoding 4.11 #define REGP_OP true 4.12 4.13 @@ -6147,6 +6150,7 @@ 4.14 %} 4.15 4.16 instruct prefetchw( memory mem ) %{ 4.17 + predicate(AllocatePrefetchStyle != 3 ); 4.18 match( PrefetchWrite mem ); 4.19 ins_cost(MEMORY_REF_COST); 4.20 4.21 @@ -6156,6 +6160,23 @@ 4.22 ins_pipe(iload_mem); 4.23 %} 4.24 4.25 +// Use BIS instruction to prefetch. 4.26 +instruct prefetchw_bis( memory mem ) %{ 4.27 + predicate(AllocatePrefetchStyle == 3); 4.28 + match( PrefetchWrite mem ); 4.29 + ins_cost(MEMORY_REF_COST); 4.30 + 4.31 + format %{ "STXA G0,$mem\t! // Block initializing store" %} 4.32 + ins_encode %{ 4.33 + Register base = as_Register($mem$$base); 4.34 + int disp = $mem$$disp; 4.35 + if (disp != 0) { 4.36 + __ add(base, AllocatePrefetchStepSize, base); 4.37 + } 4.38 + __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); 4.39 + %} 4.40 + ins_pipe(istore_mem_reg); 4.41 +%} 4.42 4.43 //----------Store Instructions------------------------------------------------- 4.44 // Store Byte
5.1 --- a/src/cpu/sparc/vm/stubGenerator_sparc.cpp Fri Apr 09 15:01:49 2010 -0700 5.2 +++ b/src/cpu/sparc/vm/stubGenerator_sparc.cpp Tue Apr 13 13:01:37 2010 -0700 5.3 @@ -1148,7 +1148,7 @@ 5.4 __ andn(from, 7, from); // Align address 5.5 __ ldx(from, 0, O3); 5.6 __ inc(from, 8); 5.7 - __ align(16); 5.8 + __ align(OptoLoopAlignment); 5.9 __ BIND(L_loop); 5.10 __ ldx(from, 0, O4); 5.11 __ deccc(count, count_dec); // Can we do next iteration after this one? 5.12 @@ -1220,7 +1220,7 @@ 5.13 // 5.14 __ andn(end_from, 7, end_from); // Align address 5.15 __ ldx(end_from, 0, O3); 5.16 - __ align(16); 5.17 + __ align(OptoLoopAlignment); 5.18 __ BIND(L_loop); 5.19 __ ldx(end_from, -8, O4); 5.20 __ deccc(count, count_dec); // Can we do next iteration after this one? 5.21 @@ -1349,7 +1349,7 @@ 5.22 __ BIND(L_copy_byte); 5.23 __ br_zero(Assembler::zero, false, Assembler::pt, count, L_exit); 5.24 __ delayed()->nop(); 5.25 - __ align(16); 5.26 + __ align(OptoLoopAlignment); 5.27 __ BIND(L_copy_byte_loop); 5.28 __ ldub(from, offset, O3); 5.29 __ deccc(count); 5.30 @@ -1445,7 +1445,7 @@ 5.31 L_aligned_copy, L_copy_byte); 5.32 } 5.33 // copy 4 elements (16 bytes) at a time 5.34 - __ align(16); 5.35 + __ align(OptoLoopAlignment); 5.36 __ BIND(L_aligned_copy); 5.37 __ dec(end_from, 16); 5.38 __ ldx(end_from, 8, O3); 5.39 @@ -1461,7 +1461,7 @@ 5.40 __ BIND(L_copy_byte); 5.41 __ br_zero(Assembler::zero, false, Assembler::pt, count, L_exit); 5.42 __ delayed()->nop(); 5.43 - __ align(16); 5.44 + __ align(OptoLoopAlignment); 5.45 __ BIND(L_copy_byte_loop); 5.46 __ dec(end_from); 5.47 __ dec(end_to); 5.48 @@ -1577,7 +1577,7 @@ 5.49 __ BIND(L_copy_2_bytes); 5.50 __ br_zero(Assembler::zero, false, Assembler::pt, count, L_exit); 5.51 __ delayed()->nop(); 5.52 - __ align(16); 5.53 + __ align(OptoLoopAlignment); 5.54 __ BIND(L_copy_2_bytes_loop); 5.55 __ lduh(from, offset, O3); 5.56 __ deccc(count); 5.57 @@ -1684,7 +1684,7 @@ 5.58 L_aligned_copy, L_copy_2_bytes); 5.59 } 5.60 // copy 4 elements (16 bytes) at a time 5.61 - __ align(16); 5.62 + __ align(OptoLoopAlignment); 5.63 __ BIND(L_aligned_copy); 5.64 __ dec(end_from, 16); 5.65 __ ldx(end_from, 8, O3); 5.66 @@ -1781,7 +1781,7 @@ 5.67 // copy with shift 4 elements (16 bytes) at a time 5.68 __ dec(count, 4); // The cmp at the beginning guaranty count >= 4 5.69 5.70 - __ align(16); 5.71 + __ align(OptoLoopAlignment); 5.72 __ BIND(L_copy_16_bytes); 5.73 __ ldx(from, 4, O4); 5.74 __ deccc(count, 4); // Can we do next iteration after this one? 5.75 @@ -1907,7 +1907,7 @@ 5.76 // to form 2 aligned 8-bytes chunks to store. 5.77 // 5.78 __ ldx(end_from, -4, O3); 5.79 - __ align(16); 5.80 + __ align(OptoLoopAlignment); 5.81 __ BIND(L_copy_16_bytes); 5.82 __ ldx(end_from, -12, O4); 5.83 __ deccc(count, 4); 5.84 @@ -1929,7 +1929,7 @@ 5.85 __ delayed()->inc(count, 4); 5.86 5.87 // copy 4 elements (16 bytes) at a time 5.88 - __ align(16); 5.89 + __ align(OptoLoopAlignment); 5.90 __ BIND(L_aligned_copy); 5.91 __ dec(end_from, 16); 5.92 __ ldx(end_from, 8, O3); 5.93 @@ -2000,6 +2000,27 @@ 5.94 // to: O1 5.95 // count: O2 treated as signed 5.96 // 5.97 + // count -= 2; 5.98 + // if ( count >= 0 ) { // >= 2 elements 5.99 + // if ( count > 6) { // >= 8 elements 5.100 + // count -= 6; // original count - 8 5.101 + // do { 5.102 + // copy_8_elements; 5.103 + // count -= 8; 5.104 + // } while ( count >= 0 ); 5.105 + // count += 6; 5.106 + // } 5.107 + // if ( count >= 0 ) { // >= 2 elements 5.108 + // do { 5.109 + // copy_2_elements; 5.110 + // } while ( (count=count-2) >= 0 ); 5.111 + // } 5.112 + // } 5.113 + // count += 2; 5.114 + // if ( count != 0 ) { // 1 element left 5.115 + // copy_1_element; 5.116 + // } 5.117 + // 5.118 void generate_disjoint_long_copy_core(bool aligned) { 5.119 Label L_copy_8_bytes, L_copy_16_bytes, L_exit; 5.120 const Register from = O0; // source array address 5.121 @@ -2012,7 +2033,39 @@ 5.122 __ mov(G0, offset0); // offset from start of arrays (0) 5.123 __ brx(Assembler::negative, false, Assembler::pn, L_copy_8_bytes ); 5.124 __ delayed()->add(offset0, 8, offset8); 5.125 - __ align(16); 5.126 + 5.127 + // Copy by 64 bytes chunks 5.128 + Label L_copy_64_bytes; 5.129 + const Register from64 = O3; // source address 5.130 + const Register to64 = G3; // destination address 5.131 + __ subcc(count, 6, O3); 5.132 + __ brx(Assembler::negative, false, Assembler::pt, L_copy_16_bytes ); 5.133 + __ delayed()->mov(to, to64); 5.134 + // Now we can use O4(offset0), O5(offset8) as temps 5.135 + __ mov(O3, count); 5.136 + __ mov(from, from64); 5.137 + 5.138 + __ align(OptoLoopAlignment); 5.139 + __ BIND(L_copy_64_bytes); 5.140 + for( int off = 0; off < 64; off += 16 ) { 5.141 + __ ldx(from64, off+0, O4); 5.142 + __ ldx(from64, off+8, O5); 5.143 + __ stx(O4, to64, off+0); 5.144 + __ stx(O5, to64, off+8); 5.145 + } 5.146 + __ deccc(count, 8); 5.147 + __ inc(from64, 64); 5.148 + __ brx(Assembler::greaterEqual, false, Assembler::pt, L_copy_64_bytes); 5.149 + __ delayed()->inc(to64, 64); 5.150 + 5.151 + // Restore O4(offset0), O5(offset8) 5.152 + __ sub(from64, from, offset0); 5.153 + __ inccc(count, 6); 5.154 + __ brx(Assembler::negative, false, Assembler::pn, L_copy_8_bytes ); 5.155 + __ delayed()->add(offset0, 8, offset8); 5.156 + 5.157 + // Copy by 16 bytes chunks 5.158 + __ align(OptoLoopAlignment); 5.159 __ BIND(L_copy_16_bytes); 5.160 __ ldx(from, offset0, O3); 5.161 __ ldx(from, offset8, G3); 5.162 @@ -2023,6 +2076,7 @@ 5.163 __ brx(Assembler::greaterEqual, false, Assembler::pt, L_copy_16_bytes); 5.164 __ delayed()->inc(offset8, 16); 5.165 5.166 + // Copy last 8 bytes 5.167 __ BIND(L_copy_8_bytes); 5.168 __ inccc(count, 2); 5.169 __ brx(Assembler::zero, true, Assembler::pn, L_exit ); 5.170 @@ -2085,7 +2139,7 @@ 5.171 __ brx(Assembler::lessEqual, false, Assembler::pn, L_copy_8_bytes ); 5.172 __ delayed()->sllx(count, LogBytesPerLong, offset8); 5.173 __ sub(offset8, 8, offset0); 5.174 - __ align(16); 5.175 + __ align(OptoLoopAlignment); 5.176 __ BIND(L_copy_16_bytes); 5.177 __ ldx(from, offset8, O2); 5.178 __ ldx(from, offset0, O3); 5.179 @@ -2351,7 +2405,7 @@ 5.180 // (O5 = 0; ; O5 += wordSize) --- offset from src, dest arrays 5.181 // (O2 = len; O2 != 0; O2--) --- number of oops *remaining* 5.182 // G3, G4, G5 --- current oop, oop.klass, oop.klass.super 5.183 - __ align(16); 5.184 + __ align(OptoLoopAlignment); 5.185 5.186 __ BIND(store_element); 5.187 __ deccc(G1_remain); // decrement the count
6.1 --- a/src/cpu/sparc/vm/vm_version_sparc.cpp Fri Apr 09 15:01:49 2010 -0700 6.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp Tue Apr 13 13:01:37 2010 -0700 6.3 @@ -86,14 +86,24 @@ 6.4 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { 6.5 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); 6.6 } 6.7 + if (is_niagara1_plus()) { 6.8 + if (AllocatePrefetchStyle > 0 && FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 6.9 + // Use BIS instruction for allocation prefetch. 6.10 + FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); 6.11 + if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 6.12 + // Use smaller prefetch distance on N2 with BIS 6.13 + FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); 6.14 + } 6.15 + } 6.16 + if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 6.17 + // Use different prefetch distance without BIS 6.18 + FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 6.19 + } 6.20 + } 6.21 +#endif 6.22 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { 6.23 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); 6.24 } 6.25 - if (is_niagara1_plus() && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 6.26 - // Use smaller prefetch distance on N2 6.27 - FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 6.28 - } 6.29 -#endif 6.30 } 6.31 6.32 // Use hardware population count instruction if available.
7.1 --- a/src/cpu/x86/vm/assembler_x86.cpp Fri Apr 09 15:01:49 2010 -0700 7.2 +++ b/src/cpu/x86/vm/assembler_x86.cpp Tue Apr 13 13:01:37 2010 -0700 7.3 @@ -3365,6 +3365,13 @@ 7.4 7.5 #else // LP64 7.6 7.7 +void Assembler::set_byte_if_not_zero(Register dst) { 7.8 + int enc = prefix_and_encode(dst->encoding(), true); 7.9 + emit_byte(0x0F); 7.10 + emit_byte(0x95); 7.11 + emit_byte(0xE0 | enc); 7.12 +} 7.13 + 7.14 // 64bit only pieces of the assembler 7.15 // This should only be used by 64bit instructions that can use rip-relative 7.16 // it cannot be used by instructions that want an immediate value.
8.1 --- a/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp Fri Apr 09 15:01:49 2010 -0700 8.2 +++ b/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp Tue Apr 13 13:01:37 2010 -0700 8.3 @@ -2690,19 +2690,14 @@ 8.4 } else { 8.5 assert(code == lir_cmp_l2i, "check"); 8.6 #ifdef _LP64 8.7 - Register dest = dst->as_register(); 8.8 - __ xorptr(dest, dest); 8.9 - Label high, done; 8.10 - __ cmpptr(left->as_register_lo(), right->as_register_lo()); 8.11 - __ jcc(Assembler::equal, done); 8.12 - __ jcc(Assembler::greater, high); 8.13 - __ decrement(dest); 8.14 - __ jmp(done); 8.15 - __ bind(high); 8.16 - __ increment(dest); 8.17 - 8.18 - __ bind(done); 8.19 - 8.20 + Label done; 8.21 + Register dest = dst->as_register(); 8.22 + __ cmpptr(left->as_register_lo(), right->as_register_lo()); 8.23 + __ movl(dest, -1); 8.24 + __ jccb(Assembler::less, done); 8.25 + __ set_byte_if_not_zero(dest); 8.26 + __ movzbl(dest, dest); 8.27 + __ bind(done); 8.28 #else 8.29 __ lcmp2int(left->as_register_hi(), 8.30 left->as_register_lo(),
9.1 --- a/src/cpu/x86/vm/c1_Runtime1_x86.cpp Fri Apr 09 15:01:49 2010 -0700 9.2 +++ b/src/cpu/x86/vm/c1_Runtime1_x86.cpp Tue Apr 13 13:01:37 2010 -0700 9.3 @@ -781,7 +781,7 @@ 9.4 9.5 // Restore SP from BP if the exception PC is a MethodHandle call site. 9.6 NOT_LP64(__ get_thread(thread);) 9.7 - __ cmpl(Address(thread, JavaThread::is_method_handle_exception_offset()), 0); 9.8 + __ cmpl(Address(thread, JavaThread::is_method_handle_return_offset()), 0); 9.9 __ cmovptr(Assembler::notEqual, rsp, rbp); 9.10 9.11 // continue at exception handler (return address removed)
10.1 --- a/src/cpu/x86/vm/c2_globals_x86.hpp Fri Apr 09 15:01:49 2010 -0700 10.2 +++ b/src/cpu/x86/vm/c2_globals_x86.hpp Tue Apr 13 13:01:37 2010 -0700 10.3 @@ -80,7 +80,6 @@ 10.4 // Ergonomics related flags 10.5 define_pd_global(uint64_t,MaxRAM, 4ULL*G); 10.6 #endif // AMD64 10.7 -define_pd_global(intx, OptoLoopAlignment, 16); 10.8 define_pd_global(intx, RegisterCostAreaRatio, 16000); 10.9 10.10 // Peephole and CISC spilling both break the graph, and so makes the
11.1 --- a/src/cpu/x86/vm/globals_x86.hpp Fri Apr 09 15:01:49 2010 -0700 11.2 +++ b/src/cpu/x86/vm/globals_x86.hpp Tue Apr 13 13:01:37 2010 -0700 11.3 @@ -45,6 +45,7 @@ 11.4 #else 11.5 define_pd_global(intx, CodeEntryAlignment, 16); 11.6 #endif // COMPILER2 11.7 +define_pd_global(intx, OptoLoopAlignment, 16); 11.8 define_pd_global(intx, InlineFrequencyCount, 100); 11.9 define_pd_global(intx, InlineSmallCode, 1000); 11.10
12.1 --- a/src/cpu/x86/vm/runtime_x86_32.cpp Fri Apr 09 15:01:49 2010 -0700 12.2 +++ b/src/cpu/x86/vm/runtime_x86_32.cpp Tue Apr 13 13:01:37 2010 -0700 12.3 @@ -115,8 +115,8 @@ 12.4 12.5 // rax: exception handler for given <exception oop/exception pc> 12.6 12.7 - // Restore SP from BP if the exception PC is a MethodHandle call. 12.8 - __ cmpl(Address(rcx, JavaThread::is_method_handle_exception_offset()), 0); 12.9 + // Restore SP from BP if the exception PC is a MethodHandle call site. 12.10 + __ cmpl(Address(rcx, JavaThread::is_method_handle_return_offset()), 0); 12.11 __ cmovptr(Assembler::notEqual, rsp, rbp); 12.12 12.13 // We have a handler in rax, (could be deopt blob)
13.1 --- a/src/cpu/x86/vm/sharedRuntime_x86_64.cpp Fri Apr 09 15:01:49 2010 -0700 13.2 +++ b/src/cpu/x86/vm/sharedRuntime_x86_64.cpp Tue Apr 13 13:01:37 2010 -0700 13.3 @@ -3328,8 +3328,8 @@ 13.4 13.5 // rax: exception handler 13.6 13.7 - // Restore SP from BP if the exception PC is a MethodHandle call. 13.8 - __ cmpl(Address(r15_thread, JavaThread::is_method_handle_exception_offset()), 0); 13.9 + // Restore SP from BP if the exception PC is a MethodHandle call site. 13.10 + __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0); 13.11 __ cmovptr(Assembler::notEqual, rsp, rbp); 13.12 13.13 // We have a handler in rax (could be deopt blob).
14.1 --- a/src/cpu/x86/vm/stubGenerator_x86_32.cpp Fri Apr 09 15:01:49 2010 -0700 14.2 +++ b/src/cpu/x86/vm/stubGenerator_x86_32.cpp Tue Apr 13 13:01:37 2010 -0700 14.3 @@ -430,7 +430,7 @@ 14.4 __ verify_oop(exception_oop); 14.5 14.6 // Restore SP from BP if the exception PC is a MethodHandle call site. 14.7 - __ cmpl(Address(thread, JavaThread::is_method_handle_exception_offset()), 0); 14.8 + __ cmpl(Address(thread, JavaThread::is_method_handle_return_offset()), 0); 14.9 __ cmovptr(Assembler::notEqual, rsp, rbp); 14.10 14.11 // continue at exception handler (return address removed) 14.12 @@ -812,7 +812,7 @@ 14.13 Label L_copy_64_bytes_loop, L_copy_64_bytes, L_copy_8_bytes, L_exit; 14.14 // Copy 64-byte chunks 14.15 __ jmpb(L_copy_64_bytes); 14.16 - __ align(16); 14.17 + __ align(OptoLoopAlignment); 14.18 __ BIND(L_copy_64_bytes_loop); 14.19 14.20 if(UseUnalignedLoadStores) { 14.21 @@ -874,7 +874,7 @@ 14.22 Label L_copy_64_bytes_loop, L_copy_64_bytes, L_copy_8_bytes, L_exit; 14.23 // Copy 64-byte chunks 14.24 __ jmpb(L_copy_64_bytes); 14.25 - __ align(16); 14.26 + __ align(OptoLoopAlignment); 14.27 __ BIND(L_copy_64_bytes_loop); 14.28 __ movq(mmx0, Address(from, 0)); 14.29 __ movq(mmx1, Address(from, 8)); 14.30 @@ -1144,7 +1144,7 @@ 14.31 __ movl(Address(to, count, sf, 0), rdx); 14.32 __ jmpb(L_copy_8_bytes); 14.33 14.34 - __ align(16); 14.35 + __ align(OptoLoopAlignment); 14.36 // Move 8 bytes 14.37 __ BIND(L_copy_8_bytes_loop); 14.38 if (UseXMMForArrayCopy) { 14.39 @@ -1235,7 +1235,7 @@ 14.40 } 14.41 } else { 14.42 __ jmpb(L_copy_8_bytes); 14.43 - __ align(16); 14.44 + __ align(OptoLoopAlignment); 14.45 __ BIND(L_copy_8_bytes_loop); 14.46 __ fild_d(Address(from, 0)); 14.47 __ fistp_d(Address(from, to_from, Address::times_1)); 14.48 @@ -1282,7 +1282,7 @@ 14.49 14.50 __ jmpb(L_copy_8_bytes); 14.51 14.52 - __ align(16); 14.53 + __ align(OptoLoopAlignment); 14.54 __ BIND(L_copy_8_bytes_loop); 14.55 if (VM_Version::supports_mmx()) { 14.56 if (UseXMMForArrayCopy) { 14.57 @@ -1454,7 +1454,7 @@ 14.58 // Loop control: 14.59 // for (count = -count; count != 0; count++) 14.60 // Base pointers src, dst are biased by 8*count,to last element. 14.61 - __ align(16); 14.62 + __ align(OptoLoopAlignment); 14.63 14.64 __ BIND(L_store_element); 14.65 __ movptr(to_element_addr, elem); // store the oop
15.1 --- a/src/cpu/x86/vm/stubGenerator_x86_64.cpp Fri Apr 09 15:01:49 2010 -0700 15.2 +++ b/src/cpu/x86/vm/stubGenerator_x86_64.cpp Tue Apr 13 13:01:37 2010 -0700 15.3 @@ -871,9 +871,8 @@ 15.4 } 15.5 15.6 address generate_fp_mask(const char *stub_name, int64_t mask) { 15.7 + __ align(CodeEntryAlignment); 15.8 StubCodeMark mark(this, "StubRoutines", stub_name); 15.9 - 15.10 - __ align(16); 15.11 address start = __ pc(); 15.12 15.13 __ emit_data64( mask, relocInfo::none ); 15.14 @@ -1268,7 +1267,7 @@ 15.15 Label& L_copy_32_bytes, Label& L_copy_8_bytes) { 15.16 DEBUG_ONLY(__ stop("enter at entry label, not here")); 15.17 Label L_loop; 15.18 - __ align(16); 15.19 + __ align(OptoLoopAlignment); 15.20 __ BIND(L_loop); 15.21 if(UseUnalignedLoadStores) { 15.22 __ movdqu(xmm0, Address(end_from, qword_count, Address::times_8, -24)); 15.23 @@ -1309,7 +1308,7 @@ 15.24 Label& L_copy_32_bytes, Label& L_copy_8_bytes) { 15.25 DEBUG_ONLY(__ stop("enter at entry label, not here")); 15.26 Label L_loop; 15.27 - __ align(16); 15.28 + __ align(OptoLoopAlignment); 15.29 __ BIND(L_loop); 15.30 if(UseUnalignedLoadStores) { 15.31 __ movdqu(xmm0, Address(from, qword_count, Address::times_8, 16)); 15.32 @@ -2229,7 +2228,7 @@ 15.33 // Loop control: 15.34 // for (count = -count; count != 0; count++) 15.35 // Base pointers src, dst are biased by 8*(count-1),to last element. 15.36 - __ align(16); 15.37 + __ align(OptoLoopAlignment); 15.38 15.39 __ BIND(L_store_element); 15.40 __ store_heap_oop(to_element_addr, rax_oop); // store the oop
16.1 --- a/src/share/vm/c1/c1_LinearScan.cpp Fri Apr 09 15:01:49 2010 -0700 16.2 +++ b/src/share/vm/c1/c1_LinearScan.cpp Tue Apr 13 13:01:37 2010 -0700 16.3 @@ -2608,6 +2608,46 @@ 16.4 } else if (opr->is_double_xmm()) { 16.5 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation"); 16.6 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg(); 16.7 +# ifdef _LP64 16.8 + first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); 16.9 + second = &_int_0_scope_value; 16.10 +# else 16.11 + first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 16.12 + // %%% This is probably a waste but we'll keep things as they were for now 16.13 + if (true) { 16.14 + VMReg rname_second = rname_first->next(); 16.15 + second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 16.16 + } 16.17 +# endif 16.18 +#endif 16.19 + 16.20 + } else if (opr->is_double_fpu()) { 16.21 + // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of 16.22 + // the double as float registers in the native ordering. On X86, 16.23 + // fpu_regnrLo is a FPU stack slot whose VMReg represents 16.24 + // the low-order word of the double and fpu_regnrLo + 1 is the 16.25 + // name for the other half. *first and *second must represent the 16.26 + // least and most significant words, respectively. 16.27 + 16.28 +#ifdef X86 16.29 + // the exact location of fpu stack values is only known 16.30 + // during fpu stack allocation, so the stack allocator object 16.31 + // must be present 16.32 + assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); 16.33 + assert(_fpu_stack_allocator != NULL, "must be present"); 16.34 + opr = _fpu_stack_allocator->to_fpu_stack(opr); 16.35 + 16.36 + assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); 16.37 +#endif 16.38 +#ifdef SPARC 16.39 + assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); 16.40 +#endif 16.41 + 16.42 + VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi()); 16.43 +#ifdef _LP64 16.44 + first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); 16.45 + second = &_int_0_scope_value; 16.46 +#else 16.47 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 16.48 // %%% This is probably a waste but we'll keep things as they were for now 16.49 if (true) { 16.50 @@ -2616,37 +2656,6 @@ 16.51 } 16.52 #endif 16.53 16.54 - } else if (opr->is_double_fpu()) { 16.55 - // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of 16.56 - // the double as float registers in the native ordering. On X86, 16.57 - // fpu_regnrLo is a FPU stack slot whose VMReg represents 16.58 - // the low-order word of the double and fpu_regnrLo + 1 is the 16.59 - // name for the other half. *first and *second must represent the 16.60 - // least and most significant words, respectively. 16.61 - 16.62 -#ifdef X86 16.63 - // the exact location of fpu stack values is only known 16.64 - // during fpu stack allocation, so the stack allocator object 16.65 - // must be present 16.66 - assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); 16.67 - assert(_fpu_stack_allocator != NULL, "must be present"); 16.68 - opr = _fpu_stack_allocator->to_fpu_stack(opr); 16.69 - 16.70 - assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); 16.71 -#endif 16.72 -#ifdef SPARC 16.73 - assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); 16.74 -#endif 16.75 - 16.76 - VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi()); 16.77 - 16.78 - first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 16.79 - // %%% This is probably a waste but we'll keep things as they were for now 16.80 - if (true) { 16.81 - VMReg rname_second = rname_first->next(); 16.82 - second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 16.83 - } 16.84 - 16.85 } else { 16.86 ShouldNotReachHere(); 16.87 first = NULL;
17.1 --- a/src/share/vm/classfile/classFileParser.cpp Fri Apr 09 15:01:49 2010 -0700 17.2 +++ b/src/share/vm/classfile/classFileParser.cpp Tue Apr 13 13:01:37 2010 -0700 17.3 @@ -2956,8 +2956,8 @@ 17.4 #endif 17.5 bool compact_fields = CompactFields; 17.6 int allocation_style = FieldsAllocationStyle; 17.7 - if( allocation_style < 0 || allocation_style > 1 ) { // Out of range? 17.8 - assert(false, "0 <= FieldsAllocationStyle <= 1"); 17.9 + if( allocation_style < 0 || allocation_style > 2 ) { // Out of range? 17.10 + assert(false, "0 <= FieldsAllocationStyle <= 2"); 17.11 allocation_style = 1; // Optimistic 17.12 } 17.13 17.14 @@ -2993,6 +2993,25 @@ 17.15 } else if( allocation_style == 1 ) { 17.16 // Fields order: longs/doubles, ints, shorts/chars, bytes, oops 17.17 next_nonstatic_double_offset = next_nonstatic_field_offset; 17.18 + } else if( allocation_style == 2 ) { 17.19 + // Fields allocation: oops fields in super and sub classes are together. 17.20 + if( nonstatic_field_size > 0 && super_klass() != NULL && 17.21 + super_klass->nonstatic_oop_map_size() > 0 ) { 17.22 + int map_size = super_klass->nonstatic_oop_map_size(); 17.23 + OopMapBlock* first_map = super_klass->start_of_nonstatic_oop_maps(); 17.24 + OopMapBlock* last_map = first_map + map_size - 1; 17.25 + int next_offset = last_map->offset() + (last_map->count() * heapOopSize); 17.26 + if (next_offset == next_nonstatic_field_offset) { 17.27 + allocation_style = 0; // allocate oops first 17.28 + next_nonstatic_oop_offset = next_nonstatic_field_offset; 17.29 + next_nonstatic_double_offset = next_nonstatic_oop_offset + 17.30 + (nonstatic_oop_count * heapOopSize); 17.31 + } 17.32 + } 17.33 + if( allocation_style == 2 ) { 17.34 + allocation_style = 1; // allocate oops last 17.35 + next_nonstatic_double_offset = next_nonstatic_field_offset; 17.36 + } 17.37 } else { 17.38 ShouldNotReachHere(); 17.39 }
18.1 --- a/src/share/vm/code/codeCache.cpp Fri Apr 09 15:01:49 2010 -0700 18.2 +++ b/src/share/vm/code/codeCache.cpp Tue Apr 13 13:01:37 2010 -0700 18.3 @@ -1,5 +1,5 @@ 18.4 /* 18.5 - * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. 18.6 + * Copyright 1997-2010 Sun Microsystems, Inc. All Rights Reserved. 18.7 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 18.8 * 18.9 * This code is free software; you can redistribute it and/or modify it 18.10 @@ -284,9 +284,11 @@ 18.11 cur->print_on(tty, is_live ? "scavenge root" : "dead scavenge root"); tty->cr(); 18.12 } 18.13 #endif //PRODUCT 18.14 - if (is_live) 18.15 + if (is_live) { 18.16 // Perform cur->oops_do(f), maybe just once per nmethod. 18.17 f->do_code_blob(cur); 18.18 + cur->fix_oop_relocations(); 18.19 + } 18.20 } 18.21 18.22 // Check for stray marks.
19.1 --- a/src/share/vm/memory/threadLocalAllocBuffer.hpp Fri Apr 09 15:01:49 2010 -0700 19.2 +++ b/src/share/vm/memory/threadLocalAllocBuffer.hpp Tue Apr 13 13:01:37 2010 -0700 19.3 @@ -111,7 +111,22 @@ 19.4 19.5 // Allocate size HeapWords. The memory is NOT initialized to zero. 19.6 inline HeapWord* allocate(size_t size); 19.7 - static size_t alignment_reserve() { return align_object_size(typeArrayOopDesc::header_size(T_INT)); } 19.8 + 19.9 + // Reserve space at the end of TLAB 19.10 + static size_t end_reserve() { 19.11 + int reserve_size = typeArrayOopDesc::header_size(T_INT); 19.12 + if (AllocatePrefetchStyle == 3) { 19.13 + // BIS is used to prefetch - we need a space for it. 19.14 + // +1 for rounding up to next cache line +1 to be safe 19.15 + int lines = AllocatePrefetchLines + 2; 19.16 + int step_size = AllocatePrefetchStepSize; 19.17 + int distance = AllocatePrefetchDistance; 19.18 + int prefetch_end = (distance + step_size*lines)/(int)HeapWordSize; 19.19 + reserve_size = MAX2(reserve_size, prefetch_end); 19.20 + } 19.21 + return reserve_size; 19.22 + } 19.23 + static size_t alignment_reserve() { return align_object_size(end_reserve()); } 19.24 static size_t alignment_reserve_in_bytes() { return alignment_reserve() * HeapWordSize; } 19.25 19.26 // Return tlab size or remaining space in eden such that the
20.1 --- a/src/share/vm/opto/c2_globals.hpp Fri Apr 09 15:01:49 2010 -0700 20.2 +++ b/src/share/vm/opto/c2_globals.hpp Tue Apr 13 13:01:37 2010 -0700 20.3 @@ -52,9 +52,6 @@ 20.4 "Code alignment for interior entry points " \ 20.5 "in generated code (in bytes)") \ 20.6 \ 20.7 - product_pd(intx, OptoLoopAlignment, \ 20.8 - "Align inner loops to zero relative to this modulus") \ 20.9 - \ 20.10 product(intx, MaxLoopPad, (OptoLoopAlignment-1), \ 20.11 "Align a loop if padding size in bytes is less or equal to this value") \ 20.12 \
21.1 --- a/src/share/vm/opto/macro.cpp Fri Apr 09 15:01:49 2010 -0700 21.2 +++ b/src/share/vm/opto/macro.cpp Tue Apr 13 13:01:37 2010 -0700 21.3 @@ -1487,11 +1487,11 @@ 21.4 Node*& contended_phi_rawmem, 21.5 Node* old_eden_top, Node* new_eden_top, 21.6 Node* length) { 21.7 + enum { fall_in_path = 1, pf_path = 2 }; 21.8 if( UseTLAB && AllocatePrefetchStyle == 2 ) { 21.9 // Generate prefetch allocation with watermark check. 21.10 // As an allocation hits the watermark, we will prefetch starting 21.11 // at a "distance" away from watermark. 21.12 - enum { fall_in_path = 1, pf_path = 2 }; 21.13 21.14 Node *pf_region = new (C, 3) RegionNode(3); 21.15 Node *pf_phi_rawmem = new (C, 3) PhiNode( pf_region, Type::MEMORY, 21.16 @@ -1570,6 +1570,45 @@ 21.17 needgc_false = pf_region; 21.18 contended_phi_rawmem = pf_phi_rawmem; 21.19 i_o = pf_phi_abio; 21.20 + } else if( UseTLAB && AllocatePrefetchStyle == 3 ) { 21.21 + // Insert a prefetch for each allocation only on the fast-path 21.22 + Node *pf_region = new (C, 3) RegionNode(3); 21.23 + Node *pf_phi_rawmem = new (C, 3) PhiNode( pf_region, Type::MEMORY, 21.24 + TypeRawPtr::BOTTOM ); 21.25 + 21.26 + // Generate several prefetch instructions only for arrays. 21.27 + uint lines = (length != NULL) ? AllocatePrefetchLines : 1; 21.28 + uint step_size = AllocatePrefetchStepSize; 21.29 + uint distance = AllocatePrefetchDistance; 21.30 + 21.31 + // Next cache address. 21.32 + Node *cache_adr = new (C, 4) AddPNode(old_eden_top, old_eden_top, 21.33 + _igvn.MakeConX(distance)); 21.34 + transform_later(cache_adr); 21.35 + cache_adr = new (C, 2) CastP2XNode(needgc_false, cache_adr); 21.36 + transform_later(cache_adr); 21.37 + Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1)); 21.38 + cache_adr = new (C, 3) AndXNode(cache_adr, mask); 21.39 + transform_later(cache_adr); 21.40 + cache_adr = new (C, 2) CastX2PNode(cache_adr); 21.41 + transform_later(cache_adr); 21.42 + 21.43 + // Prefetch 21.44 + Node *prefetch = new (C, 3) PrefetchWriteNode( contended_phi_rawmem, cache_adr ); 21.45 + prefetch->set_req(0, needgc_false); 21.46 + transform_later(prefetch); 21.47 + contended_phi_rawmem = prefetch; 21.48 + Node *prefetch_adr; 21.49 + distance = step_size; 21.50 + for ( uint i = 1; i < lines; i++ ) { 21.51 + prefetch_adr = new (C, 4) AddPNode( cache_adr, cache_adr, 21.52 + _igvn.MakeConX(distance) ); 21.53 + transform_later(prefetch_adr); 21.54 + prefetch = new (C, 3) PrefetchWriteNode( contended_phi_rawmem, prefetch_adr ); 21.55 + transform_later(prefetch); 21.56 + distance += step_size; 21.57 + contended_phi_rawmem = prefetch; 21.58 + } 21.59 } else if( AllocatePrefetchStyle > 0 ) { 21.60 // Insert a prefetch for each allocation only on the fast-path 21.61 Node *prefetch_adr;
22.1 --- a/src/share/vm/opto/memnode.hpp Fri Apr 09 15:01:49 2010 -0700 22.2 +++ b/src/share/vm/opto/memnode.hpp Tue Apr 13 13:01:37 2010 -0700 22.3 @@ -1244,5 +1244,5 @@ 22.4 virtual int Opcode() const; 22.5 virtual uint ideal_reg() const { return NotAMachineReg; } 22.6 virtual uint match_edge(uint idx) const { return idx==2; } 22.7 - virtual const Type *bottom_type() const { return Type::ABIO; } 22.8 + virtual const Type *bottom_type() const { return ( AllocatePrefetchStyle == 3 ) ? Type::MEMORY : Type::ABIO; } 22.9 };
23.1 --- a/src/share/vm/opto/runtime.cpp Fri Apr 09 15:01:49 2010 -0700 23.2 +++ b/src/share/vm/opto/runtime.cpp Tue Apr 13 13:01:37 2010 -0700 23.3 @@ -865,7 +865,7 @@ 23.4 thread->set_exception_stack_size(0); 23.5 23.6 // Check if the exception PC is a MethodHandle call site. 23.7 - thread->set_is_method_handle_exception(nm->is_method_handle_return(pc)); 23.8 + thread->set_is_method_handle_return(nm->is_method_handle_return(pc)); 23.9 } 23.10 23.11 // Restore correct return pc. Was saved above.
24.1 --- a/src/share/vm/runtime/globals.hpp Fri Apr 09 15:01:49 2010 -0700 24.2 +++ b/src/share/vm/runtime/globals.hpp Tue Apr 13 13:01:37 2010 -0700 24.3 @@ -1052,7 +1052,8 @@ 24.4 "Use SSE2 MOVDQU instruction for Arraycopy") \ 24.5 \ 24.6 product(intx, FieldsAllocationStyle, 1, \ 24.7 - "0 - type based with oops first, 1 - with oops last") \ 24.8 + "0 - type based with oops first, 1 - with oops last, " \ 24.9 + "2 - oops in super and sub classes are together") \ 24.10 \ 24.11 product(bool, CompactFields, true, \ 24.12 "Allocate nonstatic fields in gaps between previous fields") \ 24.13 @@ -2707,7 +2708,8 @@ 24.14 product(intx, AllocatePrefetchStyle, 1, \ 24.15 "0 = no prefetch, " \ 24.16 "1 = prefetch instructions for each allocation, " \ 24.17 - "2 = use TLAB watermark to gate allocation prefetch") \ 24.18 + "2 = use TLAB watermark to gate allocation prefetch, " \ 24.19 + "3 = use BIS instruction on Sparc for allocation prefetch") \ 24.20 \ 24.21 product(intx, AllocatePrefetchDistance, -1, \ 24.22 "Distance to prefetch ahead of allocation pointer") \ 24.23 @@ -3110,6 +3112,9 @@ 24.24 develop_pd(intx, CodeEntryAlignment, \ 24.25 "Code entry alignment for generated code (in bytes)") \ 24.26 \ 24.27 + product_pd(intx, OptoLoopAlignment, \ 24.28 + "Align inner loops to zero relative to this modulus") \ 24.29 + \ 24.30 product_pd(uintx, InitialCodeCacheSize, \ 24.31 "Initial code cache size (in bytes)") \ 24.32 \
25.1 --- a/src/share/vm/runtime/sharedRuntime.cpp Fri Apr 09 15:01:49 2010 -0700 25.2 +++ b/src/share/vm/runtime/sharedRuntime.cpp Tue Apr 13 13:01:37 2010 -0700 25.3 @@ -259,13 +259,16 @@ 25.4 address SharedRuntime::raw_exception_handler_for_return_address(JavaThread* thread, address return_address) { 25.5 assert(frame::verify_return_pc(return_address), "must be a return pc"); 25.6 25.7 + // Reset MethodHandle flag. 25.8 + thread->set_is_method_handle_return(false); 25.9 + 25.10 // the fastest case first 25.11 CodeBlob* blob = CodeCache::find_blob(return_address); 25.12 if (blob != NULL && blob->is_nmethod()) { 25.13 nmethod* code = (nmethod*)blob; 25.14 assert(code != NULL, "nmethod must be present"); 25.15 // Check if the return address is a MethodHandle call site. 25.16 - thread->set_is_method_handle_exception(code->is_method_handle_return(return_address)); 25.17 + thread->set_is_method_handle_return(code->is_method_handle_return(return_address)); 25.18 // native nmethods don't have exception handlers 25.19 assert(!code->is_native_method(), "no exception handler"); 25.20 assert(code->header_begin() != code->exception_begin(), "no exception handler"); 25.21 @@ -292,7 +295,7 @@ 25.22 nmethod* code = (nmethod*)blob; 25.23 assert(code != NULL, "nmethod must be present"); 25.24 // Check if the return address is a MethodHandle call site. 25.25 - thread->set_is_method_handle_exception(code->is_method_handle_return(return_address)); 25.26 + thread->set_is_method_handle_return(code->is_method_handle_return(return_address)); 25.27 assert(code->header_begin() != code->exception_begin(), "no exception handler"); 25.28 return code->exception_begin(); 25.29 }
26.1 --- a/src/share/vm/runtime/thread.hpp Fri Apr 09 15:01:49 2010 -0700 26.2 +++ b/src/share/vm/runtime/thread.hpp Tue Apr 13 13:01:37 2010 -0700 26.3 @@ -772,7 +772,7 @@ 26.4 volatile address _exception_pc; // PC where exception happened 26.5 volatile address _exception_handler_pc; // PC for handler of exception 26.6 volatile int _exception_stack_size; // Size of frame where exception happened 26.7 - volatile int _is_method_handle_exception; // True if the current exception PC is at a MethodHandle call. 26.8 + volatile int _is_method_handle_return; // true (== 1) if the current exception PC is a MethodHandle call site. 26.9 26.10 // support for compilation 26.11 bool _is_compiling; // is true if a compilation is active inthis thread (one compilation per thread possible) 26.12 @@ -1108,13 +1108,13 @@ 26.13 int exception_stack_size() const { return _exception_stack_size; } 26.14 address exception_pc() const { return _exception_pc; } 26.15 address exception_handler_pc() const { return _exception_handler_pc; } 26.16 - int is_method_handle_exception() const { return _is_method_handle_exception; } 26.17 + bool is_method_handle_return() const { return _is_method_handle_return == 1; } 26.18 26.19 void set_exception_oop(oop o) { _exception_oop = o; } 26.20 void set_exception_pc(address a) { _exception_pc = a; } 26.21 void set_exception_handler_pc(address a) { _exception_handler_pc = a; } 26.22 void set_exception_stack_size(int size) { _exception_stack_size = size; } 26.23 - void set_is_method_handle_exception(int value) { _is_method_handle_exception = value; } 26.24 + void set_is_method_handle_return(bool value) { _is_method_handle_return = value ? 1 : 0; } 26.25 26.26 // Stack overflow support 26.27 inline size_t stack_available(address cur_sp); 26.28 @@ -1188,7 +1188,7 @@ 26.29 static ByteSize exception_pc_offset() { return byte_offset_of(JavaThread, _exception_pc ); } 26.30 static ByteSize exception_handler_pc_offset() { return byte_offset_of(JavaThread, _exception_handler_pc); } 26.31 static ByteSize exception_stack_size_offset() { return byte_offset_of(JavaThread, _exception_stack_size); } 26.32 - static ByteSize is_method_handle_exception_offset() { return byte_offset_of(JavaThread, _is_method_handle_exception); } 26.33 + static ByteSize is_method_handle_return_offset() { return byte_offset_of(JavaThread, _is_method_handle_return); } 26.34 static ByteSize stack_guard_state_offset() { return byte_offset_of(JavaThread, _stack_guard_state ); } 26.35 static ByteSize suspend_flags_offset() { return byte_offset_of(JavaThread, _suspend_flags ); } 26.36
