#9406 Backport of #9405 removed useless flag mips64el-jdk8u202-b10

Wed, 19 Jun 2019 10:29:37 +0800

author
aoqi
date
Wed, 19 Jun 2019 10:29:37 +0800
changeset 9580
f10841009d27
parent 9579
1938913e9ab2
child 9581
95fce20624fc

#9406 Backport of #9405 removed useless flag

src/cpu/mips/vm/globals_mips.hpp file | annotate | diff | comparison | revisions
src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/globals_mips.hpp	Thu May 30 09:56:25 2019 +0800
     1.2 +++ b/src/cpu/mips/vm/globals_mips.hpp	Wed Jun 19 10:29:37 2019 +0800
     1.3 @@ -110,46 +110,7 @@
     1.4            "999 means FS/FO/FN will not be changed"                          \
     1.5            "=XYZ, with X:FS, Y:FO, Z:FN, X, Y and Z in 0=off, 1=on")         \
     1.6                                                                              \
     1.7 -  product(intx, FenceInstruction, 0,                                        \
     1.8 -          "(Unsafe,Unstable) Experimental")                                 \
     1.9 -                                                                            \
    1.10 -  product(intx,  ReadPrefetchInstr, 0,                                      \
    1.11 -          "Prefetch instruction to prefetch ahead")                         \
    1.12 -                                                                            \
    1.13 -  product(bool, UseStoreImmI16, true,                                       \
    1.14 -          "Use store immediate 16-bits value instruction on x86")           \
    1.15 -                                                                            \
    1.16 -  product(intx, UseAVX, 99,                                                 \
    1.17 -          "Highest supported AVX instructions set on x86/x64")              \
    1.18 -                                                                            \
    1.19 -  diagnostic(bool, UseIncDec, true,                                         \
    1.20 -          "Use INC, DEC instructions on x86")                               \
    1.21 -                                                                            \
    1.22 -  product(bool, UseNewLongLShift, false,                                    \
    1.23 -          "Use optimized bitwise shift left")                               \
    1.24 -                                                                            \
    1.25 -  product(bool, UseAddressNop, false,                                       \
    1.26 -          "Use '0F 1F [addr]' NOP instructions on x86 cpus")                \
    1.27 -                                                                            \
    1.28 -  product(bool, UseXmmLoadAndClearUpper, true,                              \
    1.29 -          "Load low part of XMM register and clear upper part")             \
    1.30 -                                                                            \
    1.31 -  product(bool, UseXmmRegToRegMoveAll, false,                               \
    1.32 -          "Copy all XMM register bits when moving value between registers") \
    1.33 -                                                                            \
    1.34 -  product(bool, UseXmmI2D, false,                                           \
    1.35 -          "Use SSE2 CVTDQ2PD instruction to convert Integer to Double")     \
    1.36 -                                                                            \
    1.37 -  product(bool, UseXmmI2F, false,                                           \
    1.38 -          "Use SSE2 CVTDQ2PS instruction to convert Integer to Float")      \
    1.39 -                                                                            \
    1.40 -  product(bool, UseUnalignedLoadStores, false,                              \
    1.41 -          "Use SSE2 MOVDQU instruction for Arraycopy")                      \
    1.42 -                                                                            \
    1.43    /* assembler */                                                           \
    1.44 -  product(bool, Use486InstrsOnly, false,                                    \
    1.45 -          "Use 80486 Compliant instruction subset")                         \
    1.46 -                                                                            \
    1.47    product(bool, UseCountLeadingZerosInstructionMIPS64, true,                \
    1.48            "Use count leading zeros instruction")                            \
    1.49                                                                              \
     2.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu May 30 09:56:25 2019 +0800
     2.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Jun 19 10:29:37 2019 +0800
     2.3 @@ -12208,7 +12208,6 @@
     2.4  
     2.5  // Shift Left Long
     2.6  instruct salL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
     2.7 -  //predicate(UseNewLongLShift);
     2.8    match(Set dst (LShiftL src shift));
     2.9    ins_cost(100);
    2.10    format %{ "salL    $dst, $src, $shift @ salL_Reg_imm" %}
    2.11 @@ -12232,7 +12231,6 @@
    2.12  %}
    2.13  
    2.14  instruct salL_RegI2L_imm(mRegL dst, mRegI src, immI8 shift) %{
    2.15 -  //predicate(UseNewLongLShift);
    2.16    match(Set dst (LShiftL (ConvI2L src) shift));
    2.17    ins_cost(100);
    2.18    format %{ "salL    $dst, $src, $shift @ salL_RegI2L_imm" %}
    2.19 @@ -12257,7 +12255,6 @@
    2.20  
    2.21  // Shift Left Long
    2.22  instruct salL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
    2.23 -  //predicate(UseNewLongLShift);
    2.24    match(Set dst (LShiftL src shift));
    2.25    ins_cost(100);
    2.26    format %{ "salL    $dst, $src, $shift @ salL_Reg_Reg" %}
    2.27 @@ -12332,7 +12329,6 @@
    2.28  
    2.29  // Shift Right Long arithmetically
    2.30  instruct sarL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
    2.31 -  //predicate(UseNewLongLShift);
    2.32    match(Set dst (RShiftL src shift));
    2.33    ins_cost(100);
    2.34    format %{ "sarL    $dst, $src, $shift @ sarL_Reg_Reg" %}

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