7005241: C1: SEGV in java.util.concurrent.LinkedTransferQueue.xfer() with compressed oops

Wed, 08 Dec 2010 02:36:36 -0800

author
iveresov
date
Wed, 08 Dec 2010 02:36:36 -0800
changeset 2355
ec8c74742417
parent 2354
5fe0781a8560
child 2356
4de5f4101cfd

7005241: C1: SEGV in java.util.concurrent.LinkedTransferQueue.xfer() with compressed oops
Summary: Implementation of the CAS primitive for x64 compressed oops was incorrect. It kills rscratch2 register (r11), which is allocatable in C1. Also, we don't need to restore cmpval as it's never used after that, so we need only one temporary register, which can be scratch1.
Reviewed-by: kvn, never

src/cpu/x86/vm/c1_LIRAssembler_x86.cpp file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp	Tue Dec 07 11:00:02 2010 -0800
     1.2 +++ b/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp	Wed Dec 08 02:36:36 2010 -0800
     1.3 @@ -1993,15 +1993,14 @@
     1.4      if ( op->code() == lir_cas_obj) {
     1.5  #ifdef _LP64
     1.6        if (UseCompressedOops) {
     1.7 -        __ mov(rscratch1, cmpval);
     1.8          __ encode_heap_oop(cmpval);
     1.9 -        __ mov(rscratch2, newval);
    1.10 -        __ encode_heap_oop(rscratch2);
    1.11 +        __ mov(rscratch1, newval);
    1.12 +        __ encode_heap_oop(rscratch1);
    1.13          if (os::is_MP()) {
    1.14            __ lock();
    1.15          }
    1.16 -        __ cmpxchgl(rscratch2, Address(addr, 0));
    1.17 -        __ mov(cmpval, rscratch1);
    1.18 +        // cmpval (rax) is implicitly used by this instruction
    1.19 +        __ cmpxchgl(rscratch1, Address(addr, 0));
    1.20        } else
    1.21  #endif
    1.22        {

mercurial