Add madd in the C2 compiler and the pipeline should be adjusted before enabling it.

Tue, 02 Aug 2016 21:48:39 +0800

author
fujie
date
Tue, 02 Aug 2016 21:48:39 +0800
changeset 48
da67d05d2190
parent 47
bf40dae23a38
child 49
76cea9141c9d

Add madd in the C2 compiler and the pipeline should be adjusted before enabling it.

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Tue Aug 02 18:49:44 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Tue Aug 02 21:48:39 2016 +0800
     1.3 @@ -8384,6 +8384,24 @@
     1.4    ins_pipe( ialu_reg_reg_alu0 );
     1.5  %}
     1.6  
     1.7 +instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{
     1.8 +  match(Set dst (AddI (MulI src1 src2) src3));
     1.9 +
    1.10 +  ins_cost(999);
    1.11 +  format %{ "madd   $dst, $src1 * $src2 + $src3 #@maddI_Reg_Reg" %}
    1.12 +  ins_encode %{
    1.13 +     Register src1 = $src1$$Register;
    1.14 +     Register src2 = $src2$$Register;
    1.15 +     Register src3 = $src3$$Register;
    1.16 +     Register dst  = $dst$$Register;
    1.17 +         
    1.18 +     __ mtlo(src3);
    1.19 +     __ madd(src1, src2);
    1.20 +     __ mflo(dst);
    1.21 +  %}
    1.22 +  ins_pipe( ialu_reg_reg_alu0 );
    1.23 +%}
    1.24 +
    1.25  instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
    1.26    match(Set dst (DivI src1 src2));
    1.27  

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