jdk8-mips64-public/hotspot: changeset 4367:c52660592f37

     1.1 --- a/src/cpu/sparc/vm/c1_CodeStubs_sparc.cpp	Wed Dec 19 16:10:19 2012 -0800
     1.2 +++ b/src/cpu/sparc/vm/c1_CodeStubs_sparc.cpp	Fri Dec 21 01:39:34 2012 -0800
     1.3 @@ -298,7 +298,7 @@
     1.4      for (int i = 0; i < _bytes_to_copy; i++) {
     1.5        address ptr = (address)(_pc_start + i);
     1.6        int a_byte = (*ptr) & 0xFF;
     1.7 -      __ a_byte (a_byte);
     1.8 +      __ emit_int8 (a_byte);
     1.9      }
    1.10    }
    1.11  
    1.12 @@ -340,10 +340,10 @@
    1.13    int being_initialized_entry_offset = __ offset() - being_initialized_entry + sizeof_patch_record;
    1.14  
    1.15    // Emit the patch record.  We need to emit a full word, so emit an extra empty byte
    1.16 -  __ a_byte(0);
    1.17 -  __ a_byte(being_initialized_entry_offset);
    1.18 -  __ a_byte(bytes_to_skip);
    1.19 -  __ a_byte(_bytes_to_copy);
    1.20 +  __ emit_int8(0);
    1.21 +  __ emit_int8(being_initialized_entry_offset);
    1.22 +  __ emit_int8(bytes_to_skip);
    1.23 +  __ emit_int8(_bytes_to_copy);
    1.24    address patch_info_pc = __ pc();
    1.25    assert(patch_info_pc - end_of_patch == bytes_to_skip, "incorrect patch info");
    1.26

     2.1 --- a/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Wed Dec 19 16:10:19 2012 -0800
     2.2 +++ b/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Fri Dec 21 01:39:34 2012 -0800
     2.3 @@ -100,34 +100,6 @@
     2.4  bool AbstractAssembler::pd_check_instruction_mark() { return false; }
     2.5  #endif
     2.6  
     2.7 -
     2.8 -void MacroAssembler::print_instruction(int inst) {
     2.9 -  const char* s;
    2.10 -  switch (inv_op(inst)) {
    2.11 -  default:         s = "????"; break;
    2.12 -  case call_op:    s = "call"; break;
    2.13 -  case branch_op:
    2.14 -    switch (inv_op2(inst)) {
    2.15 -      case fb_op2:     s = "fb";   break;
    2.16 -      case fbp_op2:    s = "fbp";  break;
    2.17 -      case br_op2:     s = "br";   break;
    2.18 -      case bp_op2:     s = "bp";   break;
    2.19 -      case cb_op2:     s = "cb";   break;
    2.20 -      case bpr_op2: {
    2.21 -        if (is_cbcond(inst)) {
    2.22 -          s = is_cxb(inst) ? "cxb" : "cwb";
    2.23 -        } else {
    2.24 -          s = "bpr";
    2.25 -        }
    2.26 -        break;
    2.27 -      }
    2.28 -      default:         s = "????"; break;
    2.29 -    }
    2.30 -  }
    2.31 -  ::tty->print("%s", s);
    2.32 -}
    2.33 -
    2.34 -
    2.35  // Patch instruction inst at offset inst_pos to refer to dest_pos
    2.36  // and return the resulting instruction.
    2.37  // We should have pcs, not offsets, but since all is relative, it will work out

     3.1 --- a/src/cpu/sparc/vm/macroAssembler_sparc.hpp	Wed Dec 19 16:10:19 2012 -0800
     3.2 +++ b/src/cpu/sparc/vm/macroAssembler_sparc.hpp	Fri Dec 21 01:39:34 2012 -0800
     3.3 @@ -603,7 +603,6 @@
     3.4    friend class Label;
     3.5  
     3.6   protected:
     3.7 -  static void print_instruction(int inst);
     3.8    static int  patched_branch(int dest_pos, int inst, int inst_pos);
     3.9    static int  branch_destination(int inst, int pos);
    3.10  
    3.11 @@ -759,9 +758,6 @@
    3.12    // Required platform-specific helpers for Label::patch_instructions.
    3.13    // They _shadow_ the declarations in AbstractAssembler, which are undefined.
    3.14    void pd_patch_instruction(address branch, address target);
    3.15 -#ifndef PRODUCT
    3.16 -  static void pd_print_patched_instruction(address branch);
    3.17 -#endif
    3.18  
    3.19    // sethi Macro handles optimizations and relocations
    3.20  private:

     4.1 --- a/src/cpu/sparc/vm/macroAssembler_sparc.inline.hpp	Wed Dec 19 16:10:19 2012 -0800
     4.2 +++ b/src/cpu/sparc/vm/macroAssembler_sparc.inline.hpp	Fri Dec 21 01:39:34 2012 -0800
     4.3 @@ -43,14 +43,6 @@
     4.4    stub_inst = patched_branch(target - branch, stub_inst, 0);
     4.5  }
     4.6  
     4.7 -#ifndef PRODUCT
     4.8 -inline void MacroAssembler::pd_print_patched_instruction(address branch) {
     4.9 -  jint stub_inst = *(jint*) branch;
    4.10 -  print_instruction(stub_inst);
    4.11 -  ::tty->print("%s", " (unresolved)");
    4.12 -}
    4.13 -#endif // PRODUCT
    4.14 -
    4.15  // Use the right loads/stores for the platform
    4.16  inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
    4.17  #ifdef _LP64

     5.1 --- a/src/cpu/sparc/vm/sparc.ad	Wed Dec 19 16:10:19 2012 -0800
     5.2 +++ b/src/cpu/sparc/vm/sparc.ad	Fri Dec 21 01:39:34 2012 -0800
     5.3 @@ -10224,7 +10224,7 @@
     5.4  
     5.5  //---------- Zeros Count Instructions ------------------------------------------
     5.6  
     5.7 -instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
     5.8 +instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
     5.9    predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
    5.10    match(Set dst (CountLeadingZerosI src));
    5.11    effect(TEMP dst, TEMP tmp, KILL cr);
    5.12 @@ -10321,7 +10321,7 @@
    5.13    ins_pipe(ialu_reg);
    5.14  %}
    5.15  
    5.16 -instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
    5.17 +instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
    5.18    predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
    5.19    match(Set dst (CountTrailingZerosI src));
    5.20    effect(TEMP dst, KILL cr);
    5.21 @@ -10364,19 +10364,21 @@
    5.22  
    5.23  //---------- Population Count Instructions -------------------------------------
    5.24  
    5.25 -instruct popCountI(iRegI dst, iRegI src) %{
    5.26 +instruct popCountI(iRegIsafe dst, iRegI src) %{
    5.27    predicate(UsePopCountInstruction);
    5.28    match(Set dst (PopCountI src));
    5.29  
    5.30 -  format %{ "POPC   $src, $dst" %}
    5.31 -  ins_encode %{
    5.32 -    __ popc($src$$Register, $dst$$Register);
    5.33 +  format %{ "SRL    $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
    5.34 +            "POPC   $dst, $dst" %}
    5.35 +  ins_encode %{
    5.36 +    __ srl($src$$Register, G0, $dst$$Register);
    5.37 +    __ popc($dst$$Register, $dst$$Register);
    5.38    %}
    5.39    ins_pipe(ialu_reg);
    5.40  %}
    5.41  
    5.42  // Note: Long.bitCount(long) returns an int.
    5.43 -instruct popCountL(iRegI dst, iRegL src) %{
    5.44 +instruct popCountL(iRegIsafe dst, iRegL src) %{
    5.45    predicate(UsePopCountInstruction);
    5.46    match(Set dst (PopCountL src));
    5.47

     6.1 --- a/src/cpu/sparc/vm/templateInterpreter_sparc.cpp	Wed Dec 19 16:10:19 2012 -0800
     6.2 +++ b/src/cpu/sparc/vm/templateInterpreter_sparc.cpp	Fri Dec 21 01:39:34 2012 -0800
     6.3 @@ -434,7 +434,7 @@
     6.4  
     6.5    // the frame is greater than one page in size, so check against
     6.6    // the bottom of the stack
     6.7 -  __ cmp_and_brx_short(SP, Rscratch, Assembler::greater, Assembler::pt, after_frame_check);
     6.8 +  __ cmp_and_brx_short(SP, Rscratch, Assembler::greaterUnsigned, Assembler::pt, after_frame_check);
     6.9  
    6.10    // the stack will overflow, throw an exception
    6.11

     7.1 --- a/src/cpu/x86/vm/assembler_x86.cpp	Wed Dec 19 16:10:19 2012 -0800
     7.2 +++ b/src/cpu/x86/vm/assembler_x86.cpp	Fri Dec 21 01:39:34 2012 -0800
     7.3 @@ -226,9 +226,9 @@
     7.4    assert(isByte(op1) && isByte(op2), "wrong opcode");
     7.5    assert(isByte(imm8), "not a byte");
     7.6    assert((op1 & 0x01) == 0, "should be 8bit operation");
     7.7 -  emit_byte(op1);
     7.8 -  emit_byte(op2 | encode(dst));
     7.9 -  emit_byte(imm8);
    7.10 +  emit_int8(op1);
    7.11 +  emit_int8(op2 | encode(dst));
    7.12 +  emit_int8(imm8);
    7.13  }
    7.14  
    7.15  
    7.16 @@ -237,12 +237,12 @@
    7.17    assert((op1 & 0x01) == 1, "should be 32bit operation");
    7.18    assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
    7.19    if (is8bit(imm32)) {
    7.20 -    emit_byte(op1 | 0x02); // set sign bit
    7.21 -    emit_byte(op2 | encode(dst));
    7.22 -    emit_byte(imm32 & 0xFF);
    7.23 +    emit_int8(op1 | 0x02); // set sign bit
    7.24 +    emit_int8(op2 | encode(dst));
    7.25 +    emit_int8(imm32 & 0xFF);
    7.26    } else {
    7.27 -    emit_byte(op1);
    7.28 -    emit_byte(op2 | encode(dst));
    7.29 +    emit_int8(op1);
    7.30 +    emit_int8(op2 | encode(dst));
    7.31      emit_long(imm32);
    7.32    }
    7.33  }
    7.34 @@ -252,8 +252,8 @@
    7.35    assert(isByte(op1) && isByte(op2), "wrong opcode");
    7.36    assert((op1 & 0x01) == 1, "should be 32bit operation");
    7.37    assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
    7.38 -  emit_byte(op1);
    7.39 -  emit_byte(op2 | encode(dst));
    7.40 +  emit_int8(op1);
    7.41 +  emit_int8(op2 | encode(dst));
    7.42    emit_long(imm32);
    7.43  }
    7.44  
    7.45 @@ -262,11 +262,11 @@
    7.46    assert((op1 & 0x01) == 1, "should be 32bit operation");
    7.47    assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
    7.48    if (is8bit(imm32)) {
    7.49 -    emit_byte(op1 | 0x02); // set sign bit
    7.50 +    emit_int8(op1 | 0x02); // set sign bit
    7.51      emit_operand(rm, adr, 1);
    7.52 -    emit_byte(imm32 & 0xFF);
    7.53 +    emit_int8(imm32 & 0xFF);
    7.54    } else {
    7.55 -    emit_byte(op1);
    7.56 +    emit_int8(op1);
    7.57      emit_operand(rm, adr, 4);
    7.58      emit_long(imm32);
    7.59    }
    7.60 @@ -275,8 +275,8 @@
    7.61  
    7.62  void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
    7.63    assert(isByte(op1) && isByte(op2), "wrong opcode");
    7.64 -  emit_byte(op1);
    7.65 -  emit_byte(op2 | encode(dst) << 3 | encode(src));
    7.66 +  emit_int8(op1);
    7.67 +  emit_int8(op2 | encode(dst) << 3 | encode(src));
    7.68  }
    7.69  
    7.70  
    7.71 @@ -301,21 +301,21 @@
    7.72          // [base + index*scale]
    7.73          // [00 reg 100][ss index base]
    7.74          assert(index != rsp, "illegal addressing mode");
    7.75 -        emit_byte(0x04 | regenc);
    7.76 -        emit_byte(scale << 6 | indexenc | baseenc);
    7.77 +        emit_int8(0x04 | regenc);
    7.78 +        emit_int8(scale << 6 | indexenc | baseenc);
    7.79        } else if (is8bit(disp) && rtype == relocInfo::none) {
    7.80          // [base + index*scale + imm8]
    7.81          // [01 reg 100][ss index base] imm8
    7.82          assert(index != rsp, "illegal addressing mode");
    7.83 -        emit_byte(0x44 | regenc);
    7.84 -        emit_byte(scale << 6 | indexenc | baseenc);
    7.85 -        emit_byte(disp & 0xFF);
    7.86 +        emit_int8(0x44 | regenc);
    7.87 +        emit_int8(scale << 6 | indexenc | baseenc);
    7.88 +        emit_int8(disp & 0xFF);
    7.89        } else {
    7.90          // [base + index*scale + disp32]
    7.91          // [10 reg 100][ss index base] disp32
    7.92          assert(index != rsp, "illegal addressing mode");
    7.93 -        emit_byte(0x84 | regenc);
    7.94 -        emit_byte(scale << 6 | indexenc | baseenc);
    7.95 +        emit_int8(0x84 | regenc);
    7.96 +        emit_int8(scale << 6 | indexenc | baseenc);
    7.97          emit_data(disp, rspec, disp32_operand);
    7.98        }
    7.99      } else if (base == rsp LP64_ONLY(|| base == r12)) {
   7.100 @@ -323,19 +323,19 @@
   7.101        if (disp == 0 && rtype == relocInfo::none) {
   7.102          // [rsp]
   7.103          // [00 reg 100][00 100 100]
   7.104 -        emit_byte(0x04 | regenc);
   7.105 -        emit_byte(0x24);
   7.106 +        emit_int8(0x04 | regenc);
   7.107 +        emit_int8(0x24);
   7.108        } else if (is8bit(disp) && rtype == relocInfo::none) {
   7.109          // [rsp + imm8]
   7.110          // [01 reg 100][00 100 100] disp8
   7.111 -        emit_byte(0x44 | regenc);
   7.112 -        emit_byte(0x24);
   7.113 -        emit_byte(disp & 0xFF);
   7.114 +        emit_int8(0x44 | regenc);
   7.115 +        emit_int8(0x24);
   7.116 +        emit_int8(disp & 0xFF);
   7.117        } else {
   7.118          // [rsp + imm32]
   7.119          // [10 reg 100][00 100 100] disp32
   7.120 -        emit_byte(0x84 | regenc);
   7.121 -        emit_byte(0x24);
   7.122 +        emit_int8(0x84 | regenc);
   7.123 +        emit_int8(0x24);
   7.124          emit_data(disp, rspec, disp32_operand);
   7.125        }
   7.126      } else {
   7.127 @@ -345,16 +345,16 @@
   7.128            base != rbp LP64_ONLY(&& base != r13)) {
   7.129          // [base]
   7.130          // [00 reg base]
   7.131 -        emit_byte(0x00 | regenc | baseenc);
   7.132 +        emit_int8(0x00 | regenc | baseenc);
   7.133        } else if (is8bit(disp) && rtype == relocInfo::none) {
   7.134          // [base + disp8]
   7.135          // [01 reg base] disp8
   7.136 -        emit_byte(0x40 | regenc | baseenc);
   7.137 -        emit_byte(disp & 0xFF);
   7.138 +        emit_int8(0x40 | regenc | baseenc);
   7.139 +        emit_int8(disp & 0xFF);
   7.140        } else {
   7.141          // [base + disp32]
   7.142          // [10 reg base] disp32
   7.143 -        emit_byte(0x80 | regenc | baseenc);
   7.144 +        emit_int8(0x80 | regenc | baseenc);
   7.145          emit_data(disp, rspec, disp32_operand);
   7.146        }
   7.147      }
   7.148 @@ -364,14 +364,14 @@
   7.149        // [index*scale + disp]
   7.150        // [00 reg 100][ss index 101] disp32
   7.151        assert(index != rsp, "illegal addressing mode");
   7.152 -      emit_byte(0x04 | regenc);
   7.153 -      emit_byte(scale << 6 | indexenc | 0x05);
   7.154 +      emit_int8(0x04 | regenc);
   7.155 +      emit_int8(scale << 6 | indexenc | 0x05);
   7.156        emit_data(disp, rspec, disp32_operand);
   7.157      } else if (rtype != relocInfo::none ) {
   7.158        // [disp] (64bit) RIP-RELATIVE (32bit) abs
   7.159        // [00 000 101] disp32
   7.160  
   7.161 -      emit_byte(0x05 | regenc);
   7.162 +      emit_int8(0x05 | regenc);
   7.163        // Note that the RIP-rel. correction applies to the generated
   7.164        // disp field, but _not_ to the target address in the rspec.
   7.165  
   7.166 @@ -391,8 +391,8 @@
   7.167        // 32bit never did this, did everything as the rip-rel/disp code above
   7.168        // [disp] ABSOLUTE
   7.169        // [00 reg 100][00 100 101] disp32
   7.170 -      emit_byte(0x04 | regenc);
   7.171 -      emit_byte(0x25);
   7.172 +      emit_int8(0x04 | regenc);
   7.173 +      emit_int8(0x25);
   7.174        emit_data(disp, rspec, disp32_operand);
   7.175      }
   7.176    }
   7.177 @@ -883,8 +883,8 @@
   7.178  void Assembler::emit_farith(int b1, int b2, int i) {
   7.179    assert(isByte(b1) && isByte(b2), "wrong opcode");
   7.180    assert(0 <= i &&  i < 8, "illegal stack offset");
   7.181 -  emit_byte(b1);
   7.182 -  emit_byte(b2 + i);
   7.183 +  emit_int8(b1);
   7.184 +  emit_int8(b2 + i);
   7.185  }
   7.186  
   7.187  
   7.188 @@ -899,7 +899,7 @@
   7.189  void Assembler::adcl(Address dst, Register src) {
   7.190    InstructionMark im(this);
   7.191    prefix(dst, src);
   7.192 -  emit_byte(0x11);
   7.193 +  emit_int8(0x11);
   7.194    emit_operand(src, dst);
   7.195  }
   7.196  
   7.197 @@ -911,7 +911,7 @@
   7.198  void Assembler::adcl(Register dst, Address src) {
   7.199    InstructionMark im(this);
   7.200    prefix(src, dst);
   7.201 -  emit_byte(0x13);
   7.202 +  emit_int8(0x13);
   7.203    emit_operand(dst, src);
   7.204  }
   7.205  
   7.206 @@ -929,7 +929,7 @@
   7.207  void Assembler::addl(Address dst, Register src) {
   7.208    InstructionMark im(this);
   7.209    prefix(dst, src);
   7.210 -  emit_byte(0x01);
   7.211 +  emit_int8(0x01);
   7.212    emit_operand(src, dst);
   7.213  }
   7.214  
   7.215 @@ -941,7 +941,7 @@
   7.216  void Assembler::addl(Register dst, Address src) {
   7.217    InstructionMark im(this);
   7.218    prefix(src, dst);
   7.219 -  emit_byte(0x03);
   7.220 +  emit_int8(0x03);
   7.221    emit_operand(dst, src);
   7.222  }
   7.223  
   7.224 @@ -953,38 +953,40 @@
   7.225  void Assembler::addr_nop_4() {
   7.226    assert(UseAddressNop, "no CPU support");
   7.227    // 4 bytes: NOP DWORD PTR [EAX+0]
   7.228 -  emit_byte(0x0F);
   7.229 -  emit_byte(0x1F);
   7.230 -  emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
   7.231 -  emit_byte(0);    // 8-bits offset (1 byte)
   7.232 +  emit_int8(0x0F);
   7.233 +  emit_int8(0x1F);
   7.234 +  emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
   7.235 +  emit_int8(0);    // 8-bits offset (1 byte)
   7.236  }
   7.237  
   7.238  void Assembler::addr_nop_5() {
   7.239    assert(UseAddressNop, "no CPU support");
   7.240    // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
   7.241 -  emit_byte(0x0F);
   7.242 -  emit_byte(0x1F);
   7.243 -  emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
   7.244 -  emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
   7.245 -  emit_byte(0);    // 8-bits offset (1 byte)
   7.246 +  emit_int8(0x0F);
   7.247 +  emit_int8(0x1F);
   7.248 +  emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
   7.249 +  emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
   7.250 +  emit_int8(0);    // 8-bits offset (1 byte)
   7.251  }
   7.252  
   7.253  void Assembler::addr_nop_7() {
   7.254    assert(UseAddressNop, "no CPU support");
   7.255    // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
   7.256 -  emit_byte(0x0F);
   7.257 -  emit_byte(0x1F);
   7.258 -  emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
   7.259 +  emit_int8(0x0F);
   7.260 +  emit_int8(0x1F);
   7.261 +  emit_int8((unsigned char)0x80);
   7.262 +                   // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
   7.263    emit_long(0);    // 32-bits offset (4 bytes)
   7.264  }
   7.265  
   7.266  void Assembler::addr_nop_8() {
   7.267    assert(UseAddressNop, "no CPU support");
   7.268    // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
   7.269 -  emit_byte(0x0F);
   7.270 -  emit_byte(0x1F);
   7.271 -  emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
   7.272 -  emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
   7.273 +  emit_int8(0x0F);
   7.274 +  emit_int8(0x1F);
   7.275 +  emit_int8((unsigned char)0x84);
   7.276 +                   // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
   7.277 +  emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
   7.278    emit_long(0);    // 32-bits offset (4 bytes)
   7.279  }
   7.280  
   7.281 @@ -1012,67 +1014,67 @@
   7.282    assert(VM_Version::supports_aes(), "");
   7.283    InstructionMark im(this);
   7.284    simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
   7.285 -  emit_byte(0xde);
   7.286 +  emit_int8((unsigned char)0xDE);
   7.287    emit_operand(dst, src);
   7.288  }
   7.289  
   7.290  void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
   7.291    assert(VM_Version::supports_aes(), "");
   7.292    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
   7.293 -  emit_byte(0xde);
   7.294 -  emit_byte(0xC0 | encode);
   7.295 +  emit_int8((unsigned char)0xDE);
   7.296 +  emit_int8(0xC0 | encode);
   7.297  }
   7.298  
   7.299  void Assembler::aesdeclast(XMMRegister dst, Address src) {
   7.300    assert(VM_Version::supports_aes(), "");
   7.301    InstructionMark im(this);
   7.302    simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
   7.303 -  emit_byte(0xdf);
   7.304 +  emit_int8((unsigned char)0xDF);
   7.305    emit_operand(dst, src);
   7.306  }
   7.307  
   7.308  void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
   7.309    assert(VM_Version::supports_aes(), "");
   7.310    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
   7.311 -  emit_byte(0xdf);
   7.312 -  emit_byte(0xC0 | encode);
   7.313 +  emit_int8((unsigned char)0xDF);
   7.314 +  emit_int8((unsigned char)(0xC0 | encode));
   7.315  }
   7.316  
   7.317  void Assembler::aesenc(XMMRegister dst, Address src) {
   7.318    assert(VM_Version::supports_aes(), "");
   7.319    InstructionMark im(this);
   7.320    simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
   7.321 -  emit_byte(0xdc);
   7.322 +  emit_int8((unsigned char)0xDC);
   7.323    emit_operand(dst, src);
   7.324  }
   7.325  
   7.326  void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
   7.327    assert(VM_Version::supports_aes(), "");
   7.328    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
   7.329 -  emit_byte(0xdc);
   7.330 -  emit_byte(0xC0 | encode);
   7.331 +  emit_int8((unsigned char)0xDC);
   7.332 +  emit_int8(0xC0 | encode);
   7.333  }
   7.334  
   7.335  void Assembler::aesenclast(XMMRegister dst, Address src) {
   7.336    assert(VM_Version::supports_aes(), "");
   7.337    InstructionMark im(this);
   7.338    simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
   7.339 -  emit_byte(0xdd);
   7.340 +  emit_int8((unsigned char)0xDD);
   7.341    emit_operand(dst, src);
   7.342  }
   7.343  
   7.344  void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
   7.345    assert(VM_Version::supports_aes(), "");
   7.346    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
   7.347 -  emit_byte(0xdd);
   7.348 -  emit_byte(0xC0 | encode);
   7.349 +  emit_int8((unsigned char)0xDD);
   7.350 +  emit_int8((unsigned char)(0xC0 | encode));
   7.351  }
   7.352  
   7.353  
   7.354  void Assembler::andl(Address dst, int32_t imm32) {
   7.355    InstructionMark im(this);
   7.356    prefix(dst);
   7.357 -  emit_byte(0x81);
   7.358 +  emit_int8((unsigned char)0x81);
   7.359    emit_operand(rsp, dst, 4);
   7.360    emit_long(imm32);
   7.361  }
   7.362 @@ -1085,7 +1087,7 @@
   7.363  void Assembler::andl(Register dst, Address src) {
   7.364    InstructionMark im(this);
   7.365    prefix(src, dst);
   7.366 -  emit_byte(0x23);
   7.367 +  emit_int8(0x23);
   7.368    emit_operand(dst, src);
   7.369  }
   7.370  
   7.371 @@ -1096,23 +1098,23 @@
   7.372  
   7.373  void Assembler::bsfl(Register dst, Register src) {
   7.374    int encode = prefix_and_encode(dst->encoding(), src->encoding());
   7.375 -  emit_byte(0x0F);
   7.376 -  emit_byte(0xBC);
   7.377 -  emit_byte(0xC0 | encode);
   7.378 +  emit_int8(0x0F);
   7.379 +  emit_int8((unsigned char)0xBC);
   7.380 +  emit_int8((unsigned char)(0xC0 | encode));
   7.381  }
   7.382  
   7.383  void Assembler::bsrl(Register dst, Register src) {
   7.384    assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
   7.385    int encode = prefix_and_encode(dst->encoding(), src->encoding());
   7.386 -  emit_byte(0x0F);
   7.387 -  emit_byte(0xBD);
   7.388 -  emit_byte(0xC0 | encode);
   7.389 +  emit_int8(0x0F);
   7.390 +  emit_int8((unsigned char)0xBD);
   7.391 +  emit_int8((unsigned char)(0xC0 | encode));
   7.392  }
   7.393  
   7.394  void Assembler::bswapl(Register reg) { // bswap
   7.395    int encode = prefix_and_encode(reg->encoding());
   7.396 -  emit_byte(0x0F);
   7.397 -  emit_byte(0xC8 | encode);
   7.398 +  emit_int8(0x0F);
   7.399 +  emit_int8((unsigned char)(0xC8 | encode));
   7.400  }
   7.401  
   7.402  void Assembler::call(Label& L, relocInfo::relocType rtype) {
   7.403 @@ -1125,36 +1127,36 @@
   7.404      assert(offs <= 0, "assembler error");
   7.405      InstructionMark im(this);
   7.406      // 1110 1000 #32-bit disp
   7.407 -    emit_byte(0xE8);
   7.408 +    emit_int8((unsigned char)0xE8);
   7.409      emit_data(offs - long_size, rtype, operand);
   7.410    } else {
   7.411      InstructionMark im(this);
   7.412      // 1110 1000 #32-bit disp
   7.413      L.add_patch_at(code(), locator());
   7.414  
   7.415 -    emit_byte(0xE8);
   7.416 +    emit_int8((unsigned char)0xE8);
   7.417      emit_data(int(0), rtype, operand);
   7.418    }
   7.419  }
   7.420  
   7.421  void Assembler::call(Register dst) {
   7.422    int encode = prefix_and_encode(dst->encoding());
   7.423 -  emit_byte(0xFF);
   7.424 -  emit_byte(0xD0 | encode);
   7.425 +  emit_int8((unsigned char)0xFF);
   7.426 +  emit_int8((unsigned char)(0xD0 | encode));
   7.427  }
   7.428  
   7.429  
   7.430  void Assembler::call(Address adr) {
   7.431    InstructionMark im(this);
   7.432    prefix(adr);
   7.433 -  emit_byte(0xFF);
   7.434 +  emit_int8((unsigned char)0xFF);
   7.435    emit_operand(rdx, adr);
   7.436  }
   7.437  
   7.438  void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
   7.439    assert(entry != NULL, "call most probably wrong");
   7.440    InstructionMark im(this);
   7.441 -  emit_byte(0xE8);
   7.442 +  emit_int8((unsigned char)0xE8);
   7.443    intptr_t disp = entry - (pc() + sizeof(int32_t));
   7.444    assert(is_simm32(disp), "must be 32bit offset (call2)");
   7.445    // Technically, should use call32_operand, but this format is
   7.446 @@ -1165,42 +1167,42 @@
   7.447  }
   7.448  
   7.449  void Assembler::cdql() {
   7.450 -  emit_byte(0x99);
   7.451 +  emit_int8((unsigned char)0x99);
   7.452  }
   7.453  
   7.454  void Assembler::cld() {
   7.455 -  emit_byte(0xfc);
   7.456 +  emit_int8((unsigned char)0xFC);
   7.457  }
   7.458  
   7.459  void Assembler::cmovl(Condition cc, Register dst, Register src) {
   7.460    NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
   7.461    int encode = prefix_and_encode(dst->encoding(), src->encoding());
   7.462 -  emit_byte(0x0F);
   7.463 -  emit_byte(0x40 | cc);
   7.464 -  emit_byte(0xC0 | encode);
   7.465 +  emit_int8(0x0F);
   7.466 +  emit_int8(0x40 | cc);
   7.467 +  emit_int8((unsigned char)(0xC0 | encode));
   7.468  }
   7.469  
   7.470  
   7.471  void Assembler::cmovl(Condition cc, Register dst, Address src) {
   7.472    NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
   7.473    prefix(src, dst);
   7.474 -  emit_byte(0x0F);
   7.475 -  emit_byte(0x40 | cc);
   7.476 +  emit_int8(0x0F);
   7.477 +  emit_int8(0x40 | cc);
   7.478    emit_operand(dst, src);
   7.479  }
   7.480  
   7.481  void Assembler::cmpb(Address dst, int imm8) {
   7.482    InstructionMark im(this);
   7.483    prefix(dst);
   7.484 -  emit_byte(0x80);
   7.485 +  emit_int8((unsigned char)0x80);
   7.486    emit_operand(rdi, dst, 1);
   7.487 -  emit_byte(imm8);
   7.488 +  emit_int8(imm8);
   7.489  }
   7.490  
   7.491  void Assembler::cmpl(Address dst, int32_t imm32) {
   7.492    InstructionMark im(this);
   7.493    prefix(dst);
   7.494 -  emit_byte(0x81);
   7.495 +  emit_int8((unsigned char)0x81);
   7.496    emit_operand(rdi, dst, 4);
   7.497    emit_long(imm32);
   7.498  }
   7.499 @@ -1219,17 +1221,17 @@
   7.500  void Assembler::cmpl(Register dst, Address  src) {
   7.501    InstructionMark im(this);
   7.502    prefix(src, dst);
   7.503 -  emit_byte(0x3B);
   7.504 +  emit_int8((unsigned char)0x3B);
   7.505    emit_operand(dst, src);
   7.506  }
   7.507  
   7.508  void Assembler::cmpw(Address dst, int imm16) {
   7.509    InstructionMark im(this);
   7.510    assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
   7.511 -  emit_byte(0x66);
   7.512 -  emit_byte(0x81);
   7.513 +  emit_int8(0x66);
   7.514 +  emit_int8((unsigned char)0x81);
   7.515    emit_operand(rdi, dst, 2);
   7.516 -  emit_word(imm16);
   7.517 +  emit_int16(imm16);
   7.518  }
   7.519  
   7.520  // The 32-bit cmpxchg compares the value at adr with the contents of rax,
   7.521 @@ -1238,8 +1240,8 @@
   7.522  void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
   7.523    InstructionMark im(this);
   7.524    prefix(adr, reg);
   7.525 -  emit_byte(0x0F);
   7.526 -  emit_byte(0xB1);
   7.527 +  emit_int8(0x0F);
   7.528 +  emit_int8((unsigned char)0xB1);
   7.529    emit_operand(reg, adr);
   7.530  }
   7.531  
   7.532 @@ -1266,8 +1268,8 @@
   7.533  }
   7.534  
   7.535  void Assembler::cpuid() {
   7.536 -  emit_byte(0x0F);
   7.537 -  emit_byte(0xA2);
   7.538 +  emit_int8(0x0F);
   7.539 +  emit_int8((unsigned char)0xA2);
   7.540  }
   7.541  
   7.542  void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
   7.543 @@ -1293,8 +1295,8 @@
   7.544  void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
   7.545    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   7.546    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
   7.547 -  emit_byte(0x2A);
   7.548 -  emit_byte(0xC0 | encode);
   7.549 +  emit_int8(0x2A);
   7.550 +  emit_int8((unsigned char)(0xC0 | encode));
   7.551  }
   7.552  
   7.553  void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
   7.554 @@ -1305,8 +1307,8 @@
   7.555  void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
   7.556    NOT_LP64(assert(VM_Version::supports_sse(), ""));
   7.557    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
   7.558 -  emit_byte(0x2A);
   7.559 -  emit_byte(0xC0 | encode);
   7.560 +  emit_int8(0x2A);
   7.561 +  emit_int8((unsigned char)(0xC0 | encode));
   7.562  }
   7.563  
   7.564  void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
   7.565 @@ -1328,22 +1330,22 @@
   7.566  void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
   7.567    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   7.568    int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
   7.569 -  emit_byte(0x2C);
   7.570 -  emit_byte(0xC0 | encode);
   7.571 +  emit_int8(0x2C);
   7.572 +  emit_int8((unsigned char)(0xC0 | encode));
   7.573  }
   7.574  
   7.575  void Assembler::cvttss2sil(Register dst, XMMRegister src) {
   7.576    NOT_LP64(assert(VM_Version::supports_sse(), ""));
   7.577    int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
   7.578 -  emit_byte(0x2C);
   7.579 -  emit_byte(0xC0 | encode);
   7.580 +  emit_int8(0x2C);
   7.581 +  emit_int8((unsigned char)(0xC0 | encode));
   7.582  }
   7.583  
   7.584  void Assembler::decl(Address dst) {
   7.585    // Don't use it directly. Use MacroAssembler::decrement() instead.
   7.586    InstructionMark im(this);
   7.587    prefix(dst);
   7.588 -  emit_byte(0xFF);
   7.589 +  emit_int8((unsigned char)0xFF);
   7.590    emit_operand(rcx, dst);
   7.591  }
   7.592  
   7.593 @@ -1369,43 +1371,43 @@
   7.594  
   7.595  void Assembler::emms() {
   7.596    NOT_LP64(assert(VM_Version::supports_mmx(), ""));
   7.597 -  emit_byte(0x0F);
   7.598 -  emit_byte(0x77);
   7.599 +  emit_int8(0x0F);
   7.600 +  emit_int8(0x77);
   7.601  }
   7.602  
   7.603  void Assembler::hlt() {
   7.604 -  emit_byte(0xF4);
   7.605 +  emit_int8((unsigned char)0xF4);
   7.606  }
   7.607  
   7.608  void Assembler::idivl(Register src) {
   7.609    int encode = prefix_and_encode(src->encoding());
   7.610 -  emit_byte(0xF7);
   7.611 -  emit_byte(0xF8 | encode);
   7.612 +  emit_int8((unsigned char)0xF7);
   7.613 +  emit_int8((unsigned char)(0xF8 | encode));
   7.614  }
   7.615  
   7.616  void Assembler::divl(Register src) { // Unsigned
   7.617    int encode = prefix_and_encode(src->encoding());
   7.618 -  emit_byte(0xF7);
   7.619 -  emit_byte(0xF0 | encode);
   7.620 +  emit_int8((unsigned char)0xF7);
   7.621 +  emit_int8((unsigned char)(0xF0 | encode));
   7.622  }
   7.623  
   7.624  void Assembler::imull(Register dst, Register src) {
   7.625    int encode = prefix_and_encode(dst->encoding(), src->encoding());
   7.626 -  emit_byte(0x0F);
   7.627 -  emit_byte(0xAF);
   7.628 -  emit_byte(0xC0 | encode);
   7.629 +  emit_int8(0x0F);
   7.630 +  emit_int8((unsigned char)0xAF);
   7.631 +  emit_int8((unsigned char)(0xC0 | encode));
   7.632  }
   7.633  
   7.634  
   7.635  void Assembler::imull(Register dst, Register src, int value) {
   7.636    int encode = prefix_and_encode(dst->encoding(), src->encoding());
   7.637    if (is8bit(value)) {
   7.638 -    emit_byte(0x6B);
   7.639 -    emit_byte(0xC0 | encode);
   7.640 -    emit_byte(value & 0xFF);
   7.641 +    emit_int8(0x6B);
   7.642 +    emit_int8((unsigned char)(0xC0 | encode));
   7.643 +    emit_int8(value & 0xFF);
   7.644    } else {
   7.645 -    emit_byte(0x69);
   7.646 -    emit_byte(0xC0 | encode);
   7.647 +    emit_int8(0x69);
   7.648 +    emit_int8((unsigned char)(0xC0 | encode));
   7.649      emit_long(value);
   7.650    }
   7.651  }
   7.652 @@ -1414,7 +1416,7 @@
   7.653    // Don't use it directly. Use MacroAssembler::increment() instead.
   7.654    InstructionMark im(this);
   7.655    prefix(dst);
   7.656 -  emit_byte(0xFF);
   7.657 +  emit_int8((unsigned char)0xFF);
   7.658    emit_operand(rax, dst);
   7.659  }
   7.660  
   7.661 @@ -1430,14 +1432,14 @@
   7.662      intptr_t offs = (intptr_t)dst - (intptr_t)pc();
   7.663      if (maybe_short && is8bit(offs - short_size)) {
   7.664        // 0111 tttn #8-bit disp
   7.665 -      emit_byte(0x70 | cc);
   7.666 -      emit_byte((offs - short_size) & 0xFF);
   7.667 +      emit_int8(0x70 | cc);
   7.668 +      emit_int8((offs - short_size) & 0xFF);
   7.669      } else {
   7.670        // 0000 1111 1000 tttn #32-bit disp
   7.671        assert(is_simm32(offs - long_size),
   7.672               "must be 32bit offset (call4)");
   7.673 -      emit_byte(0x0F);
   7.674 -      emit_byte(0x80 | cc);
   7.675 +      emit_int8(0x0F);
   7.676 +      emit_int8((unsigned char)(0x80 | cc));
   7.677        emit_long(offs - long_size);
   7.678      }
   7.679    } else {
   7.680 @@ -1446,8 +1448,8 @@
   7.681      // Note: use jccb() if label to be bound is very close to get
   7.682      //       an 8-bit displacement
   7.683      L.add_patch_at(code(), locator());
   7.684 -    emit_byte(0x0F);
   7.685 -    emit_byte(0x80 | cc);
   7.686 +    emit_int8(0x0F);
   7.687 +    emit_int8((unsigned char)(0x80 | cc));
   7.688      emit_long(0);
   7.689    }
   7.690  }
   7.691 @@ -1466,20 +1468,20 @@
   7.692  #endif
   7.693      intptr_t offs = (intptr_t)entry - (intptr_t)pc();
   7.694      // 0111 tttn #8-bit disp
   7.695 -    emit_byte(0x70 | cc);
   7.696 -    emit_byte((offs - short_size) & 0xFF);
   7.697 +    emit_int8(0x70 | cc);
   7.698 +    emit_int8((offs - short_size) & 0xFF);
   7.699    } else {
   7.700      InstructionMark im(this);
   7.701      L.add_patch_at(code(), locator());
   7.702 -    emit_byte(0x70 | cc);
   7.703 -    emit_byte(0);
   7.704 +    emit_int8(0x70 | cc);
   7.705 +    emit_int8(0);
   7.706    }
   7.707  }
   7.708  
   7.709  void Assembler::jmp(Address adr) {
   7.710    InstructionMark im(this);
   7.711    prefix(adr);
   7.712 -  emit_byte(0xFF);
   7.713 +  emit_int8((unsigned char)0xFF);
   7.714    emit_operand(rsp, adr);
   7.715  }
   7.716  
   7.717 @@ -1492,10 +1494,10 @@
   7.718      const int long_size = 5;
   7.719      intptr_t offs = entry - pc();
   7.720      if (maybe_short && is8bit(offs - short_size)) {
   7.721 -      emit_byte(0xEB);
   7.722 -      emit_byte((offs - short_size) & 0xFF);
   7.723 +      emit_int8((unsigned char)0xEB);
   7.724 +      emit_int8((offs - short_size) & 0xFF);
   7.725      } else {
   7.726 -      emit_byte(0xE9);
   7.727 +      emit_int8((unsigned char)0xE9);
   7.728        emit_long(offs - long_size);
   7.729      }
   7.730    } else {
   7.731 @@ -1505,20 +1507,20 @@
   7.732      // force an 8-bit displacement.
   7.733      InstructionMark im(this);
   7.734      L.add_patch_at(code(), locator());
   7.735 -    emit_byte(0xE9);
   7.736 +    emit_int8((unsigned char)0xE9);
   7.737      emit_long(0);
   7.738    }
   7.739  }
   7.740  
   7.741  void Assembler::jmp(Register entry) {
   7.742    int encode = prefix_and_encode(entry->encoding());
   7.743 -  emit_byte(0xFF);
   7.744 -  emit_byte(0xE0 | encode);
   7.745 +  emit_int8((unsigned char)0xFF);
   7.746 +  emit_int8((unsigned char)(0xE0 | encode));
   7.747  }
   7.748  
   7.749  void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
   7.750    InstructionMark im(this);
   7.751 -  emit_byte(0xE9);
   7.752 +  emit_int8((unsigned char)0xE9);
   7.753    assert(dest != NULL, "must have a target");
   7.754    intptr_t disp = dest - (pc() + sizeof(int32_t));
   7.755    assert(is_simm32(disp), "must be 32bit offset (jmp)");
   7.756 @@ -1539,13 +1541,13 @@
   7.757      assert(is8bit(dist), "Dispacement too large for a short jmp");
   7.758  #endif
   7.759      intptr_t offs = entry - pc();
   7.760 -    emit_byte(0xEB);
   7.761 -    emit_byte((offs - short_size) & 0xFF);
   7.762 +    emit_int8((unsigned char)0xEB);
   7.763 +    emit_int8((offs - short_size) & 0xFF);
   7.764    } else {
   7.765      InstructionMark im(this);
   7.766      L.add_patch_at(code(), locator());
   7.767 -    emit_byte(0xEB);
   7.768 -    emit_byte(0);
   7.769 +    emit_int8((unsigned char)0xEB);
   7.770 +    emit_int8(0);
   7.771    }
   7.772  }
   7.773  
   7.774 @@ -1553,46 +1555,46 @@
   7.775    NOT_LP64(assert(VM_Version::supports_sse(), ""));
   7.776    InstructionMark im(this);
   7.777    prefix(src);
   7.778 -  emit_byte(0x0F);
   7.779 -  emit_byte(0xAE);
   7.780 +  emit_int8(0x0F);
   7.781 +  emit_int8((unsigned char)0xAE);
   7.782    emit_operand(as_Register(2), src);
   7.783  }
   7.784  
   7.785  void Assembler::leal(Register dst, Address src) {
   7.786    InstructionMark im(this);
   7.787  #ifdef _LP64
   7.788 -  emit_byte(0x67); // addr32
   7.789 +  emit_int8(0x67); // addr32
   7.790    prefix(src, dst);
   7.791  #endif // LP64
   7.792 -  emit_byte(0x8D);
   7.793 +  emit_int8((unsigned char)0x8D);
   7.794    emit_operand(dst, src);
   7.795  }
   7.796  
   7.797  void Assembler::lfence() {
   7.798 -  emit_byte(0x0F);
   7.799 -  emit_byte(0xAE);
   7.800 -  emit_byte(0xE8);
   7.801 +  emit_int8(0x0F);
   7.802 +  emit_int8((unsigned char)0xAE);
   7.803 +  emit_int8((unsigned char)0xE8);
   7.804  }
   7.805  
   7.806  void Assembler::lock() {
   7.807 -  emit_byte(0xF0);
   7.808 +  emit_int8((unsigned char)0xF0);
   7.809  }
   7.810  
   7.811  void Assembler::lzcntl(Register dst, Register src) {
   7.812    assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
   7.813 -  emit_byte(0xF3);
   7.814 +  emit_int8((unsigned char)0xF3);
   7.815    int encode = prefix_and_encode(dst->encoding(), src->encoding());
   7.816 -  emit_byte(0x0F);
   7.817 -  emit_byte(0xBD);
   7.818 -  emit_byte(0xC0 | encode);
   7.819 +  emit_int8(0x0F);
   7.820 +  emit_int8((unsigned char)0xBD);
   7.821 +  emit_int8((unsigned char)(0xC0 | encode));
   7.822  }
   7.823  
   7.824  // Emit mfence instruction
   7.825  void Assembler::mfence() {
   7.826    NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
   7.827 -  emit_byte( 0x0F );
   7.828 -  emit_byte( 0xAE );
   7.829 -  emit_byte( 0xF0 );
   7.830 +  emit_int8(0x0F);
   7.831 +  emit_int8((unsigned char)0xAE);
   7.832 +  emit_int8((unsigned char)0xF0);
   7.833  }
   7.834  
   7.835  void Assembler::mov(Register dst, Register src) {
   7.836 @@ -1612,15 +1614,15 @@
   7.837  void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
   7.838    NOT_LP64(assert(VM_Version::supports_sse(), ""));
   7.839    int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
   7.840 -  emit_byte(0x16);
   7.841 -  emit_byte(0xC0 | encode);
   7.842 +  emit_int8(0x16);
   7.843 +  emit_int8((unsigned char)(0xC0 | encode));
   7.844  }
   7.845  
   7.846  void Assembler::movb(Register dst, Address src) {
   7.847    NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
   7.848    InstructionMark im(this);
   7.849    prefix(src, dst, true);
   7.850 -  emit_byte(0x8A);
   7.851 +  emit_int8((unsigned char)0x8A);
   7.852    emit_operand(dst, src);
   7.853  }
   7.854  
   7.855 @@ -1628,9 +1630,9 @@
   7.856  void Assembler::movb(Address dst, int imm8) {
   7.857    InstructionMark im(this);
   7.858     prefix(dst);
   7.859 -  emit_byte(0xC6);
   7.860 +  emit_int8((unsigned char)0xC6);
   7.861    emit_operand(rax, dst, 1);
   7.862 -  emit_byte(imm8);
   7.863 +  emit_int8(imm8);
   7.864  }
   7.865  
   7.866  
   7.867 @@ -1638,30 +1640,30 @@
   7.868    assert(src->has_byte_register(), "must have byte register");
   7.869    InstructionMark im(this);
   7.870    prefix(dst, src, true);
   7.871 -  emit_byte(0x88);
   7.872 +  emit_int8((unsigned char)0x88);
   7.873    emit_operand(src, dst);
   7.874  }
   7.875  
   7.876  void Assembler::movdl(XMMRegister dst, Register src) {
   7.877    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   7.878    int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
   7.879 -  emit_byte(0x6E);
   7.880 -  emit_byte(0xC0 | encode);
   7.881 +  emit_int8(0x6E);
   7.882 +  emit_int8((unsigned char)(0xC0 | encode));
   7.883  }
   7.884  
   7.885  void Assembler::movdl(Register dst, XMMRegister src) {
   7.886    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   7.887    // swap src/dst to get correct prefix
   7.888    int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
   7.889 -  emit_byte(0x7E);
   7.890 -  emit_byte(0xC0 | encode);
   7.891 +  emit_int8(0x7E);
   7.892 +  emit_int8((unsigned char)(0xC0 | encode));
   7.893  }
   7.894  
   7.895  void Assembler::movdl(XMMRegister dst, Address src) {
   7.896    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   7.897    InstructionMark im(this);
   7.898    simd_prefix(dst, src, VEX_SIMD_66);
   7.899 -  emit_byte(0x6E);
   7.900 +  emit_int8(0x6E);
   7.901    emit_operand(dst, src);
   7.902  }
   7.903  
   7.904 @@ -1669,7 +1671,7 @@
   7.905    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   7.906    InstructionMark im(this);
   7.907    simd_prefix(dst, src, VEX_SIMD_66);
   7.908 -  emit_byte(0x7E);
   7.909 +  emit_int8(0x7E);
   7.910    emit_operand(src, dst);
   7.911  }
   7.912  
   7.913 @@ -1692,7 +1694,7 @@
   7.914    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
   7.915    InstructionMark im(this);
   7.916    simd_prefix(dst, src, VEX_SIMD_F3);
   7.917 -  emit_byte(0x7F);
   7.918 +  emit_int8(0x7F);
   7.919    emit_operand(src, dst);
   7.920  }
   7.921  
   7.922 @@ -1701,8 +1703,8 @@
   7.923    assert(UseAVX, "");
   7.924    bool vector256 = true;
   7.925    int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
   7.926 -  emit_byte(0x6F);
   7.927 -  emit_byte(0xC0 | encode);
   7.928 +  emit_int8(0x6F);
   7.929 +  emit_int8((unsigned char)(0xC0 | encode));
   7.930  }
   7.931  
   7.932  void Assembler::vmovdqu(XMMRegister dst, Address src) {
   7.933 @@ -1710,7 +1712,7 @@
   7.934    InstructionMark im(this);
   7.935    bool vector256 = true;
   7.936    vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
   7.937 -  emit_byte(0x6F);
   7.938 +  emit_int8(0x6F);
   7.939    emit_operand(dst, src);
   7.940  }
   7.941  
   7.942 @@ -1721,7 +1723,7 @@
   7.943    // swap src<->dst for encoding
   7.944    assert(src != xnoreg, "sanity");
   7.945    vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
   7.946 -  emit_byte(0x7F);
   7.947 +  emit_int8(0x7F);
   7.948    emit_operand(src, dst);
   7.949  }
   7.950  
   7.951 @@ -1729,27 +1731,27 @@
   7.952  
   7.953  void Assembler::movl(Register dst, int32_t imm32) {
   7.954    int encode = prefix_and_encode(dst->encoding());
   7.955 -  emit_byte(0xB8 | encode);
   7.956 +  emit_int8((unsigned char)(0xB8 | encode));
   7.957    emit_long(imm32);
   7.958  }
   7.959  
   7.960  void Assembler::movl(Register dst, Register src) {
   7.961    int encode = prefix_and_encode(dst->encoding(), src->encoding());
   7.962 -  emit_byte(0x8B);
   7.963 -  emit_byte(0xC0 | encode);
   7.964 +  emit_int8((unsigned char)0x8B);
   7.965 +  emit_int8((unsigned char)(0xC0 | encode));
   7.966  }
   7.967  
   7.968  void Assembler::movl(Register dst, Address src) {
   7.969    InstructionMark im(this);
   7.970    prefix(src, dst);
   7.971 -  emit_byte(0x8B);
   7.972 +  emit_int8((unsigned char)0x8B);
   7.973    emit_operand(dst, src);
   7.974  }
   7.975  
   7.976  void Assembler::movl(Address dst, int32_t imm32) {
   7.977    InstructionMark im(this);
   7.978    prefix(dst);
   7.979 -  emit_byte(0xC7);
   7.980 +  emit_int8((unsigned char)0xC7);
   7.981    emit_operand(rax, dst, 4);
   7.982    emit_long(imm32);
   7.983  }
   7.984 @@ -1757,7 +1759,7 @@
   7.985  void Assembler::movl(Address dst, Register src) {
   7.986    InstructionMark im(this);
   7.987    prefix(dst, src);
   7.988 -  emit_byte(0x89);
   7.989 +  emit_int8((unsigned char)0x89);
   7.990    emit_operand(src, dst);
   7.991  }
   7.992  
   7.993 @@ -1771,15 +1773,15 @@
   7.994  
   7.995  void Assembler::movq( MMXRegister dst, Address src ) {
   7.996    assert( VM_Version::supports_mmx(), "" );
   7.997 -  emit_byte(0x0F);
   7.998 -  emit_byte(0x6F);
   7.999 +  emit_int8(0x0F);
  7.1000 +  emit_int8(0x6F);
  7.1001    emit_operand(dst, src);
  7.1002  }
  7.1003  
  7.1004  void Assembler::movq( Address dst, MMXRegister src ) {
  7.1005    assert( VM_Version::supports_mmx(), "" );
  7.1006 -  emit_byte(0x0F);
  7.1007 -  emit_byte(0x7F);
  7.1008 +  emit_int8(0x0F);
  7.1009 +  emit_int8(0x7F);
  7.1010    // workaround gcc (3.2.1-7a) bug
  7.1011    // In that version of gcc with only an emit_operand(MMX, Address)
  7.1012    // gcc will tail jump and try and reverse the parameters completely
  7.1013 @@ -1793,7 +1795,7 @@
  7.1014    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.1015    InstructionMark im(this);
  7.1016    simd_prefix(dst, src, VEX_SIMD_F3);
  7.1017 -  emit_byte(0x7E);
  7.1018 +  emit_int8(0x7E);
  7.1019    emit_operand(dst, src);
  7.1020  }
  7.1021  
  7.1022 @@ -1801,24 +1803,24 @@
  7.1023    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.1024    InstructionMark im(this);
  7.1025    simd_prefix(dst, src, VEX_SIMD_66);
  7.1026 -  emit_byte(0xD6);
  7.1027 +  emit_int8((unsigned char)0xD6);
  7.1028    emit_operand(src, dst);
  7.1029  }
  7.1030  
  7.1031  void Assembler::movsbl(Register dst, Address src) { // movsxb
  7.1032    InstructionMark im(this);
  7.1033    prefix(src, dst);
  7.1034 -  emit_byte(0x0F);
  7.1035 -  emit_byte(0xBE);
  7.1036 +  emit_int8(0x0F);
  7.1037 +  emit_int8((unsigned char)0xBE);
  7.1038    emit_operand(dst, src);
  7.1039  }
  7.1040  
  7.1041  void Assembler::movsbl(Register dst, Register src) { // movsxb
  7.1042    NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
  7.1043    int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
  7.1044 -  emit_byte(0x0F);
  7.1045 -  emit_byte(0xBE);
  7.1046 -  emit_byte(0xC0 | encode);
  7.1047 +  emit_int8(0x0F);
  7.1048 +  emit_int8((unsigned char)0xBE);
  7.1049 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1050  }
  7.1051  
  7.1052  void Assembler::movsd(XMMRegister dst, XMMRegister src) {
  7.1053 @@ -1835,7 +1837,7 @@
  7.1054    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.1055    InstructionMark im(this);
  7.1056    simd_prefix(dst, src, VEX_SIMD_F2);
  7.1057 -  emit_byte(0x11);
  7.1058 +  emit_int8(0x11);
  7.1059    emit_operand(src, dst);
  7.1060  }
  7.1061  
  7.1062 @@ -1853,93 +1855,93 @@
  7.1063    NOT_LP64(assert(VM_Version::supports_sse(), ""));
  7.1064    InstructionMark im(this);
  7.1065    simd_prefix(dst, src, VEX_SIMD_F3);
  7.1066 -  emit_byte(0x11);
  7.1067 +  emit_int8(0x11);
  7.1068    emit_operand(src, dst);
  7.1069  }
  7.1070  
  7.1071  void Assembler::movswl(Register dst, Address src) { // movsxw
  7.1072    InstructionMark im(this);
  7.1073    prefix(src, dst);
  7.1074 -  emit_byte(0x0F);
  7.1075 -  emit_byte(0xBF);
  7.1076 +  emit_int8(0x0F);
  7.1077 +  emit_int8((unsigned char)0xBF);
  7.1078    emit_operand(dst, src);
  7.1079  }
  7.1080  
  7.1081  void Assembler::movswl(Register dst, Register src) { // movsxw
  7.1082    int encode = prefix_and_encode(dst->encoding(), src->encoding());
  7.1083 -  emit_byte(0x0F);
  7.1084 -  emit_byte(0xBF);
  7.1085 -  emit_byte(0xC0 | encode);
  7.1086 +  emit_int8(0x0F);
  7.1087 +  emit_int8((unsigned char)0xBF);
  7.1088 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1089  }
  7.1090  
  7.1091  void Assembler::movw(Address dst, int imm16) {
  7.1092    InstructionMark im(this);
  7.1093  
  7.1094 -  emit_byte(0x66); // switch to 16-bit mode
  7.1095 +  emit_int8(0x66); // switch to 16-bit mode
  7.1096    prefix(dst);
  7.1097 -  emit_byte(0xC7);
  7.1098 +  emit_int8((unsigned char)0xC7);
  7.1099    emit_operand(rax, dst, 2);
  7.1100 -  emit_word(imm16);
  7.1101 +  emit_int16(imm16);
  7.1102  }
  7.1103  
  7.1104  void Assembler::movw(Register dst, Address src) {
  7.1105    InstructionMark im(this);
  7.1106 -  emit_byte(0x66);
  7.1107 +  emit_int8(0x66);
  7.1108    prefix(src, dst);
  7.1109 -  emit_byte(0x8B);
  7.1110 +  emit_int8((unsigned char)0x8B);
  7.1111    emit_operand(dst, src);
  7.1112  }
  7.1113  
  7.1114  void Assembler::movw(Address dst, Register src) {
  7.1115    InstructionMark im(this);
  7.1116 -  emit_byte(0x66);
  7.1117 +  emit_int8(0x66);
  7.1118    prefix(dst, src);
  7.1119 -  emit_byte(0x89);
  7.1120 +  emit_int8((unsigned char)0x89);
  7.1121    emit_operand(src, dst);
  7.1122  }
  7.1123  
  7.1124  void Assembler::movzbl(Register dst, Address src) { // movzxb
  7.1125    InstructionMark im(this);
  7.1126    prefix(src, dst);
  7.1127 -  emit_byte(0x0F);
  7.1128 -  emit_byte(0xB6);
  7.1129 +  emit_int8(0x0F);
  7.1130 +  emit_int8((unsigned char)0xB6);
  7.1131    emit_operand(dst, src);
  7.1132  }
  7.1133  
  7.1134  void Assembler::movzbl(Register dst, Register src) { // movzxb
  7.1135    NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
  7.1136    int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
  7.1137 -  emit_byte(0x0F);
  7.1138 -  emit_byte(0xB6);
  7.1139 -  emit_byte(0xC0 | encode);
  7.1140 +  emit_int8(0x0F);
  7.1141 +  emit_int8((unsigned char)0xB6);
  7.1142 +  emit_int8(0xC0 | encode);
  7.1143  }
  7.1144  
  7.1145  void Assembler::movzwl(Register dst, Address src) { // movzxw
  7.1146    InstructionMark im(this);
  7.1147    prefix(src, dst);
  7.1148 -  emit_byte(0x0F);
  7.1149 -  emit_byte(0xB7);
  7.1150 +  emit_int8(0x0F);
  7.1151 +  emit_int8((unsigned char)0xB7);
  7.1152    emit_operand(dst, src);
  7.1153  }
  7.1154  
  7.1155  void Assembler::movzwl(Register dst, Register src) { // movzxw
  7.1156    int encode = prefix_and_encode(dst->encoding(), src->encoding());
  7.1157 -  emit_byte(0x0F);
  7.1158 -  emit_byte(0xB7);
  7.1159 -  emit_byte(0xC0 | encode);
  7.1160 +  emit_int8(0x0F);
  7.1161 +  emit_int8((unsigned char)0xB7);
  7.1162 +  emit_int8(0xC0 | encode);
  7.1163  }
  7.1164  
  7.1165  void Assembler::mull(Address src) {
  7.1166    InstructionMark im(this);
  7.1167    prefix(src);
  7.1168 -  emit_byte(0xF7);
  7.1169 +  emit_int8((unsigned char)0xF7);
  7.1170    emit_operand(rsp, src);
  7.1171  }
  7.1172  
  7.1173  void Assembler::mull(Register src) {
  7.1174    int encode = prefix_and_encode(src->encoding());
  7.1175 -  emit_byte(0xF7);
  7.1176 -  emit_byte(0xE0 | encode);
  7.1177 +  emit_int8((unsigned char)0xF7);
  7.1178 +  emit_int8((unsigned char)(0xE0 | encode));
  7.1179  }
  7.1180  
  7.1181  void Assembler::mulsd(XMMRegister dst, Address src) {
  7.1182 @@ -1964,8 +1966,8 @@
  7.1183  
  7.1184  void Assembler::negl(Register dst) {
  7.1185    int encode = prefix_and_encode(dst->encoding());
  7.1186 -  emit_byte(0xF7);
  7.1187 -  emit_byte(0xD8 | encode);
  7.1188 +  emit_int8((unsigned char)0xF7);
  7.1189 +  emit_int8((unsigned char)(0xD8 | encode));
  7.1190  }
  7.1191  
  7.1192  void Assembler::nop(int i) {
  7.1193 @@ -1976,7 +1978,7 @@
  7.1194    // speed is not an issue so simply use the single byte traditional nop
  7.1195    // to do alignment.
  7.1196  
  7.1197 -  for (; i > 0 ; i--) emit_byte(0x90);
  7.1198 +  for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
  7.1199    return;
  7.1200  
  7.1201  #endif // ASSERT
  7.1202 @@ -2006,33 +2008,35 @@
  7.1203      while(i >= 15) {
  7.1204        // For Intel don't generate consecutive addess nops (mix with regular nops)
  7.1205        i -= 15;
  7.1206 -      emit_byte(0x66);   // size prefix
  7.1207 -      emit_byte(0x66);   // size prefix
  7.1208 -      emit_byte(0x66);   // size prefix
  7.1209 +      emit_int8(0x66);   // size prefix
  7.1210 +      emit_int8(0x66);   // size prefix
  7.1211 +      emit_int8(0x66);   // size prefix
  7.1212        addr_nop_8();
  7.1213 -      emit_byte(0x66);   // size prefix
  7.1214 -      emit_byte(0x66);   // size prefix
  7.1215 -      emit_byte(0x66);   // size prefix
  7.1216 -      emit_byte(0x90);   // nop
  7.1217 +      emit_int8(0x66);   // size prefix
  7.1218 +      emit_int8(0x66);   // size prefix
  7.1219 +      emit_int8(0x66);   // size prefix
  7.1220 +      emit_int8((unsigned char)0x90);
  7.1221 +                         // nop
  7.1222      }
  7.1223      switch (i) {
  7.1224        case 14:
  7.1225 -        emit_byte(0x66); // size prefix
  7.1226 +        emit_int8(0x66); // size prefix
  7.1227        case 13:
  7.1228 -        emit_byte(0x66); // size prefix
  7.1229 +        emit_int8(0x66); // size prefix
  7.1230        case 12:
  7.1231          addr_nop_8();
  7.1232 -        emit_byte(0x66); // size prefix
  7.1233 -        emit_byte(0x66); // size prefix
  7.1234 -        emit_byte(0x66); // size prefix
  7.1235 -        emit_byte(0x90); // nop
  7.1236 +        emit_int8(0x66); // size prefix
  7.1237 +        emit_int8(0x66); // size prefix
  7.1238 +        emit_int8(0x66); // size prefix
  7.1239 +        emit_int8((unsigned char)0x90);
  7.1240 +                         // nop
  7.1241          break;
  7.1242        case 11:
  7.1243 -        emit_byte(0x66); // size prefix
  7.1244 +        emit_int8(0x66); // size prefix
  7.1245        case 10:
  7.1246 -        emit_byte(0x66); // size prefix
  7.1247 +        emit_int8(0x66); // size prefix
  7.1248        case 9:
  7.1249 -        emit_byte(0x66); // size prefix
  7.1250 +        emit_int8(0x66); // size prefix
  7.1251        case 8:
  7.1252          addr_nop_8();
  7.1253          break;
  7.1254 @@ -2040,7 +2044,7 @@
  7.1255          addr_nop_7();
  7.1256          break;
  7.1257        case 6:
  7.1258 -        emit_byte(0x66); // size prefix
  7.1259 +        emit_int8(0x66); // size prefix
  7.1260        case 5:
  7.1261          addr_nop_5();
  7.1262          break;
  7.1263 @@ -2049,11 +2053,12 @@
  7.1264          break;
  7.1265        case 3:
  7.1266          // Don't use "0x0F 0x1F 0x00" - need patching safe padding
  7.1267 -        emit_byte(0x66); // size prefix
  7.1268 +        emit_int8(0x66); // size prefix
  7.1269        case 2:
  7.1270 -        emit_byte(0x66); // size prefix
  7.1271 +        emit_int8(0x66); // size prefix
  7.1272        case 1:
  7.1273 -        emit_byte(0x90); // nop
  7.1274 +        emit_int8((unsigned char)0x90);
  7.1275 +                         // nop
  7.1276          break;
  7.1277        default:
  7.1278          assert(i == 0, " ");
  7.1279 @@ -2086,24 +2091,24 @@
  7.1280  
  7.1281      while(i >= 22) {
  7.1282        i -= 11;
  7.1283 -      emit_byte(0x66); // size prefix
  7.1284 -      emit_byte(0x66); // size prefix
  7.1285 -      emit_byte(0x66); // size prefix
  7.1286 +      emit_int8(0x66); // size prefix
  7.1287 +      emit_int8(0x66); // size prefix
  7.1288 +      emit_int8(0x66); // size prefix
  7.1289        addr_nop_8();
  7.1290      }
  7.1291      // Generate first nop for size between 21-12
  7.1292      switch (i) {
  7.1293        case 21:
  7.1294          i -= 1;
  7.1295 -        emit_byte(0x66); // size prefix
  7.1296 +        emit_int8(0x66); // size prefix
  7.1297        case 20:
  7.1298        case 19:
  7.1299          i -= 1;
  7.1300 -        emit_byte(0x66); // size prefix
  7.1301 +        emit_int8(0x66); // size prefix
  7.1302        case 18:
  7.1303        case 17:
  7.1304          i -= 1;
  7.1305 -        emit_byte(0x66); // size prefix
  7.1306 +        emit_int8(0x66); // size prefix
  7.1307        case 16:
  7.1308        case 15:
  7.1309          i -= 8;
  7.1310 @@ -2116,7 +2121,7 @@
  7.1311          break;
  7.1312        case 12:
  7.1313          i -= 6;
  7.1314 -        emit_byte(0x66); // size prefix
  7.1315 +        emit_int8(0x66); // size prefix
  7.1316          addr_nop_5();
  7.1317          break;
  7.1318        default:
  7.1319 @@ -2126,11 +2131,11 @@
  7.1320      // Generate second nop for size between 11-1
  7.1321      switch (i) {
  7.1322        case 11:
  7.1323 -        emit_byte(0x66); // size prefix
  7.1324 +        emit_int8(0x66); // size prefix
  7.1325        case 10:
  7.1326 -        emit_byte(0x66); // size prefix
  7.1327 +        emit_int8(0x66); // size prefix
  7.1328        case 9:
  7.1329 -        emit_byte(0x66); // size prefix
  7.1330 +        emit_int8(0x66); // size prefix
  7.1331        case 8:
  7.1332          addr_nop_8();
  7.1333          break;
  7.1334 @@ -2138,7 +2143,7 @@
  7.1335          addr_nop_7();
  7.1336          break;
  7.1337        case 6:
  7.1338 -        emit_byte(0x66); // size prefix
  7.1339 +        emit_int8(0x66); // size prefix
  7.1340        case 5:
  7.1341          addr_nop_5();
  7.1342          break;
  7.1343 @@ -2147,11 +2152,12 @@
  7.1344          break;
  7.1345        case 3:
  7.1346          // Don't use "0x0F 0x1F 0x00" - need patching safe padding
  7.1347 -        emit_byte(0x66); // size prefix
  7.1348 +        emit_int8(0x66); // size prefix
  7.1349        case 2:
  7.1350 -        emit_byte(0x66); // size prefix
  7.1351 +        emit_int8(0x66); // size prefix
  7.1352        case 1:
  7.1353 -        emit_byte(0x90); // nop
  7.1354 +        emit_int8((unsigned char)0x90);
  7.1355 +                         // nop
  7.1356          break;
  7.1357        default:
  7.1358          assert(i == 0, " ");
  7.1359 @@ -2174,42 +2180,43 @@
  7.1360    //
  7.1361    while(i > 12) {
  7.1362      i -= 4;
  7.1363 -    emit_byte(0x66); // size prefix
  7.1364 -    emit_byte(0x66);
  7.1365 -    emit_byte(0x66);
  7.1366 -    emit_byte(0x90); // nop
  7.1367 +    emit_int8(0x66); // size prefix
  7.1368 +    emit_int8(0x66);
  7.1369 +    emit_int8(0x66);
  7.1370 +    emit_int8((unsigned char)0x90);
  7.1371 +                     // nop
  7.1372    }
  7.1373    // 1 - 12 nops
  7.1374    if(i > 8) {
  7.1375      if(i > 9) {
  7.1376        i -= 1;
  7.1377 -      emit_byte(0x66);
  7.1378 +      emit_int8(0x66);
  7.1379      }
  7.1380      i -= 3;
  7.1381 -    emit_byte(0x66);
  7.1382 -    emit_byte(0x66);
  7.1383 -    emit_byte(0x90);
  7.1384 +    emit_int8(0x66);
  7.1385 +    emit_int8(0x66);
  7.1386 +    emit_int8((unsigned char)0x90);
  7.1387    }
  7.1388    // 1 - 8 nops
  7.1389    if(i > 4) {
  7.1390      if(i > 6) {
  7.1391        i -= 1;
  7.1392 -      emit_byte(0x66);
  7.1393 +      emit_int8(0x66);
  7.1394      }
  7.1395      i -= 3;
  7.1396 -    emit_byte(0x66);
  7.1397 -    emit_byte(0x66);
  7.1398 -    emit_byte(0x90);
  7.1399 +    emit_int8(0x66);
  7.1400 +    emit_int8(0x66);
  7.1401 +    emit_int8((unsigned char)0x90);
  7.1402    }
  7.1403    switch (i) {
  7.1404      case 4:
  7.1405 -      emit_byte(0x66);
  7.1406 +      emit_int8(0x66);
  7.1407      case 3:
  7.1408 -      emit_byte(0x66);
  7.1409 +      emit_int8(0x66);
  7.1410      case 2:
  7.1411 -      emit_byte(0x66);
  7.1412 +      emit_int8(0x66);
  7.1413      case 1:
  7.1414 -      emit_byte(0x90);
  7.1415 +      emit_int8((unsigned char)0x90);
  7.1416        break;
  7.1417      default:
  7.1418        assert(i == 0, " ");
  7.1419 @@ -2218,8 +2225,8 @@
  7.1420  
  7.1421  void Assembler::notl(Register dst) {
  7.1422    int encode = prefix_and_encode(dst->encoding());
  7.1423 -  emit_byte(0xF7);
  7.1424 -  emit_byte(0xD0 | encode );
  7.1425 +  emit_int8((unsigned char)0xF7);
  7.1426 +  emit_int8((unsigned char)(0xD0 | encode));
  7.1427  }
  7.1428  
  7.1429  void Assembler::orl(Address dst, int32_t imm32) {
  7.1430 @@ -2236,7 +2243,7 @@
  7.1431  void Assembler::orl(Register dst, Address src) {
  7.1432    InstructionMark im(this);
  7.1433    prefix(src, dst);
  7.1434 -  emit_byte(0x0B);
  7.1435 +  emit_int8(0x0B);
  7.1436    emit_operand(dst, src);
  7.1437  }
  7.1438  
  7.1439 @@ -2260,61 +2267,61 @@
  7.1440    assert(VM_Version::supports_sse4_2(), "");
  7.1441    InstructionMark im(this);
  7.1442    simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
  7.1443 -  emit_byte(0x61);
  7.1444 +  emit_int8(0x61);
  7.1445    emit_operand(dst, src);
  7.1446 -  emit_byte(imm8);
  7.1447 +  emit_int8(imm8);
  7.1448  }
  7.1449  
  7.1450  void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
  7.1451    assert(VM_Version::supports_sse4_2(), "");
  7.1452    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
  7.1453 -  emit_byte(0x61);
  7.1454 -  emit_byte(0xC0 | encode);
  7.1455 -  emit_byte(imm8);
  7.1456 +  emit_int8(0x61);
  7.1457 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1458 +  emit_int8(imm8);
  7.1459  }
  7.1460  
  7.1461  void Assembler::pmovzxbw(XMMRegister dst, Address src) {
  7.1462    assert(VM_Version::supports_sse4_1(), "");
  7.1463    InstructionMark im(this);
  7.1464    simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
  7.1465 -  emit_byte(0x30);
  7.1466 +  emit_int8(0x30);
  7.1467    emit_operand(dst, src);
  7.1468  }
  7.1469  
  7.1470  void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
  7.1471    assert(VM_Version::supports_sse4_1(), "");
  7.1472    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
  7.1473 -  emit_byte(0x30);
  7.1474 -  emit_byte(0xC0 | encode);
  7.1475 +  emit_int8(0x30);
  7.1476 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1477  }
  7.1478  
  7.1479  // generic
  7.1480  void Assembler::pop(Register dst) {
  7.1481    int encode = prefix_and_encode(dst->encoding());
  7.1482 -  emit_byte(0x58 | encode);
  7.1483 +  emit_int8(0x58 | encode);
  7.1484  }
  7.1485  
  7.1486  void Assembler::popcntl(Register dst, Address src) {
  7.1487    assert(VM_Version::supports_popcnt(), "must support");
  7.1488    InstructionMark im(this);
  7.1489 -  emit_byte(0xF3);
  7.1490 +  emit_int8((unsigned char)0xF3);
  7.1491    prefix(src, dst);
  7.1492 -  emit_byte(0x0F);
  7.1493 -  emit_byte(0xB8);
  7.1494 +  emit_int8(0x0F);
  7.1495 +  emit_int8((unsigned char)0xB8);
  7.1496    emit_operand(dst, src);
  7.1497  }
  7.1498  
  7.1499  void Assembler::popcntl(Register dst, Register src) {
  7.1500    assert(VM_Version::supports_popcnt(), "must support");
  7.1501 -  emit_byte(0xF3);
  7.1502 +  emit_int8((unsigned char)0xF3);
  7.1503    int encode = prefix_and_encode(dst->encoding(), src->encoding());
  7.1504 -  emit_byte(0x0F);
  7.1505 -  emit_byte(0xB8);
  7.1506 -  emit_byte(0xC0 | encode);
  7.1507 +  emit_int8(0x0F);
  7.1508 +  emit_int8((unsigned char)0xB8);
  7.1509 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1510  }
  7.1511  
  7.1512  void Assembler::popf() {
  7.1513 -  emit_byte(0x9D);
  7.1514 +  emit_int8((unsigned char)0x9D);
  7.1515  }
  7.1516  
  7.1517  #ifndef _LP64 // no 32bit push/pop on amd64
  7.1518 @@ -2322,21 +2329,21 @@
  7.1519    // NOTE: this will adjust stack by 8byte on 64bits
  7.1520    InstructionMark im(this);
  7.1521    prefix(dst);
  7.1522 -  emit_byte(0x8F);
  7.1523 +  emit_int8((unsigned char)0x8F);
  7.1524    emit_operand(rax, dst);
  7.1525  }
  7.1526  #endif
  7.1527  
  7.1528  void Assembler::prefetch_prefix(Address src) {
  7.1529    prefix(src);
  7.1530 -  emit_byte(0x0F);
  7.1531 +  emit_int8(0x0F);
  7.1532  }
  7.1533  
  7.1534  void Assembler::prefetchnta(Address src) {
  7.1535    NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
  7.1536    InstructionMark im(this);
  7.1537    prefetch_prefix(src);
  7.1538 -  emit_byte(0x18);
  7.1539 +  emit_int8(0x18);
  7.1540    emit_operand(rax, src); // 0, src
  7.1541  }
  7.1542  
  7.1543 @@ -2344,7 +2351,7 @@
  7.1544    assert(VM_Version::supports_3dnow_prefetch(), "must support");
  7.1545    InstructionMark im(this);
  7.1546    prefetch_prefix(src);
  7.1547 -  emit_byte(0x0D);
  7.1548 +  emit_int8(0x0D);
  7.1549    emit_operand(rax, src); // 0, src
  7.1550  }
  7.1551  
  7.1552 @@ -2352,7 +2359,7 @@
  7.1553    NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
  7.1554    InstructionMark im(this);
  7.1555    prefetch_prefix(src);
  7.1556 -  emit_byte(0x18);
  7.1557 +  emit_int8(0x18);
  7.1558    emit_operand(rcx, src); // 1, src
  7.1559  }
  7.1560  
  7.1561 @@ -2360,7 +2367,7 @@
  7.1562    NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
  7.1563    InstructionMark im(this);
  7.1564    prefetch_prefix(src);
  7.1565 -  emit_byte(0x18);
  7.1566 +  emit_int8(0x18);
  7.1567    emit_operand(rdx, src); // 2, src
  7.1568  }
  7.1569  
  7.1570 @@ -2368,7 +2375,7 @@
  7.1571    NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
  7.1572    InstructionMark im(this);
  7.1573    prefetch_prefix(src);
  7.1574 -  emit_byte(0x18);
  7.1575 +  emit_int8(0x18);
  7.1576    emit_operand(rbx, src); // 3, src
  7.1577  }
  7.1578  
  7.1579 @@ -2376,27 +2383,26 @@
  7.1580    assert(VM_Version::supports_3dnow_prefetch(), "must support");
  7.1581    InstructionMark im(this);
  7.1582    prefetch_prefix(src);
  7.1583 -  emit_byte(0x0D);
  7.1584 +  emit_int8(0x0D);
  7.1585    emit_operand(rcx, src); // 1, src
  7.1586  }
  7.1587  
  7.1588  void Assembler::prefix(Prefix p) {
  7.1589 -  a_byte(p);
  7.1590 +  emit_int8(p);
  7.1591  }
  7.1592  
  7.1593  void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
  7.1594    assert(VM_Version::supports_ssse3(), "");
  7.1595    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
  7.1596 -  emit_byte(0x00);
  7.1597 -  emit_byte(0xC0 | encode);
  7.1598 +  emit_int8(0x00);
  7.1599 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1600  }
  7.1601  
  7.1602  void Assembler::pshufb(XMMRegister dst, Address src) {
  7.1603    assert(VM_Version::supports_ssse3(), "");
  7.1604 -  assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
  7.1605    InstructionMark im(this);
  7.1606    simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
  7.1607 -  emit_byte(0x00);
  7.1608 +  emit_int8(0x00);
  7.1609    emit_operand(dst, src);
  7.1610  }
  7.1611  
  7.1612 @@ -2404,7 +2410,7 @@
  7.1613    assert(isByte(mode), "invalid value");
  7.1614    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.1615    emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
  7.1616 -  emit_byte(mode & 0xFF);
  7.1617 +  emit_int8(mode & 0xFF);
  7.1618  
  7.1619  }
  7.1620  
  7.1621 @@ -2414,16 +2420,16 @@
  7.1622    assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
  7.1623    InstructionMark im(this);
  7.1624    simd_prefix(dst, src, VEX_SIMD_66);
  7.1625 -  emit_byte(0x70);
  7.1626 +  emit_int8(0x70);
  7.1627    emit_operand(dst, src);
  7.1628 -  emit_byte(mode & 0xFF);
  7.1629 +  emit_int8(mode & 0xFF);
  7.1630  }
  7.1631  
  7.1632  void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
  7.1633    assert(isByte(mode), "invalid value");
  7.1634    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.1635    emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
  7.1636 -  emit_byte(mode & 0xFF);
  7.1637 +  emit_int8(mode & 0xFF);
  7.1638  }
  7.1639  
  7.1640  void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
  7.1641 @@ -2432,18 +2438,18 @@
  7.1642    assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
  7.1643    InstructionMark im(this);
  7.1644    simd_prefix(dst, src, VEX_SIMD_F2);
  7.1645 -  emit_byte(0x70);
  7.1646 +  emit_int8(0x70);
  7.1647    emit_operand(dst, src);
  7.1648 -  emit_byte(mode & 0xFF);
  7.1649 +  emit_int8(mode & 0xFF);
  7.1650  }
  7.1651  
  7.1652  void Assembler::psrldq(XMMRegister dst, int shift) {
  7.1653    // Shift 128 bit value in xmm register by number of bytes.
  7.1654    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.1655    int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
  7.1656 -  emit_byte(0x73);
  7.1657 -  emit_byte(0xC0 | encode);
  7.1658 -  emit_byte(shift);
  7.1659 +  emit_int8(0x73);
  7.1660 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1661 +  emit_int8(shift);
  7.1662  }
  7.1663  
  7.1664  void Assembler::ptest(XMMRegister dst, Address src) {
  7.1665 @@ -2451,15 +2457,15 @@
  7.1666    assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
  7.1667    InstructionMark im(this);
  7.1668    simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
  7.1669 -  emit_byte(0x17);
  7.1670 +  emit_int8(0x17);
  7.1671    emit_operand(dst, src);
  7.1672  }
  7.1673  
  7.1674  void Assembler::ptest(XMMRegister dst, XMMRegister src) {
  7.1675    assert(VM_Version::supports_sse4_1(), "");
  7.1676    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
  7.1677 -  emit_byte(0x17);
  7.1678 -  emit_byte(0xC0 | encode);
  7.1679 +  emit_int8(0x17);
  7.1680 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1681  }
  7.1682  
  7.1683  void Assembler::punpcklbw(XMMRegister dst, Address src) {
  7.1684 @@ -2492,18 +2498,18 @@
  7.1685  void Assembler::push(int32_t imm32) {
  7.1686    // in 64bits we push 64bits onto the stack but only
  7.1687    // take a 32bit immediate
  7.1688 -  emit_byte(0x68);
  7.1689 +  emit_int8(0x68);
  7.1690    emit_long(imm32);
  7.1691  }
  7.1692  
  7.1693  void Assembler::push(Register src) {
  7.1694    int encode = prefix_and_encode(src->encoding());
  7.1695  
  7.1696 -  emit_byte(0x50 | encode);
  7.1697 +  emit_int8(0x50 | encode);
  7.1698  }
  7.1699  
  7.1700  void Assembler::pushf() {
  7.1701 -  emit_byte(0x9C);
  7.1702 +  emit_int8((unsigned char)0x9C);
  7.1703  }
  7.1704  
  7.1705  #ifndef _LP64 // no 32bit push/pop on amd64
  7.1706 @@ -2511,7 +2517,7 @@
  7.1707    // Note this will push 64bit on 64bit
  7.1708    InstructionMark im(this);
  7.1709    prefix(src);
  7.1710 -  emit_byte(0xFF);
  7.1711 +  emit_int8((unsigned char)0xFF);
  7.1712    emit_operand(rsi, src);
  7.1713  }
  7.1714  #endif
  7.1715 @@ -2520,58 +2526,58 @@
  7.1716    assert(isShiftCount(imm8), "illegal shift count");
  7.1717    int encode = prefix_and_encode(dst->encoding());
  7.1718    if (imm8 == 1) {
  7.1719 -    emit_byte(0xD1);
  7.1720 -    emit_byte(0xD0 | encode);
  7.1721 +    emit_int8((unsigned char)0xD1);
  7.1722 +    emit_int8((unsigned char)(0xD0 | encode));
  7.1723    } else {
  7.1724 -    emit_byte(0xC1);
  7.1725 -    emit_byte(0xD0 | encode);
  7.1726 -    emit_byte(imm8);
  7.1727 +    emit_int8((unsigned char)0xC1);
  7.1728 +    emit_int8((unsigned char)0xD0 | encode);
  7.1729 +    emit_int8(imm8);
  7.1730    }
  7.1731  }
  7.1732  
  7.1733  // copies data from [esi] to [edi] using rcx pointer sized words
  7.1734  // generic
  7.1735  void Assembler::rep_mov() {
  7.1736 -  emit_byte(0xF3);
  7.1737 +  emit_int8((unsigned char)0xF3);
  7.1738    // MOVSQ
  7.1739    LP64_ONLY(prefix(REX_W));
  7.1740 -  emit_byte(0xA5);
  7.1741 +  emit_int8((unsigned char)0xA5);
  7.1742  }
  7.1743  
  7.1744  // sets rcx pointer sized words with rax, value at [edi]
  7.1745  // generic
  7.1746  void Assembler::rep_set() { // rep_set
  7.1747 -  emit_byte(0xF3);
  7.1748 +  emit_int8((unsigned char)0xF3);
  7.1749    // STOSQ
  7.1750    LP64_ONLY(prefix(REX_W));
  7.1751 -  emit_byte(0xAB);
  7.1752 +  emit_int8((unsigned char)0xAB);
  7.1753  }
  7.1754  
  7.1755  // scans rcx pointer sized words at [edi] for occurance of rax,
  7.1756  // generic
  7.1757  void Assembler::repne_scan() { // repne_scan
  7.1758 -  emit_byte(0xF2);
  7.1759 +  emit_int8((unsigned char)0xF2);
  7.1760    // SCASQ
  7.1761    LP64_ONLY(prefix(REX_W));
  7.1762 -  emit_byte(0xAF);
  7.1763 +  emit_int8((unsigned char)0xAF);
  7.1764  }
  7.1765  
  7.1766  #ifdef _LP64
  7.1767  // scans rcx 4 byte words at [edi] for occurance of rax,
  7.1768  // generic
  7.1769  void Assembler::repne_scanl() { // repne_scan
  7.1770 -  emit_byte(0xF2);
  7.1771 +  emit_int8((unsigned char)0xF2);
  7.1772    // SCASL
  7.1773 -  emit_byte(0xAF);
  7.1774 +  emit_int8((unsigned char)0xAF);
  7.1775  }
  7.1776  #endif
  7.1777  
  7.1778  void Assembler::ret(int imm16) {
  7.1779    if (imm16 == 0) {
  7.1780 -    emit_byte(0xC3);
  7.1781 +    emit_int8((unsigned char)0xC3);
  7.1782    } else {
  7.1783 -    emit_byte(0xC2);
  7.1784 -    emit_word(imm16);
  7.1785 +    emit_int8((unsigned char)0xC2);
  7.1786 +    emit_int16(imm16);
  7.1787    }
  7.1788  }
  7.1789  
  7.1790 @@ -2580,26 +2586,26 @@
  7.1791    // Not supported in 64bit mode
  7.1792    ShouldNotReachHere();
  7.1793  #endif
  7.1794 -  emit_byte(0x9E);
  7.1795 +  emit_int8((unsigned char)0x9E);
  7.1796  }
  7.1797  
  7.1798  void Assembler::sarl(Register dst, int imm8) {
  7.1799    int encode = prefix_and_encode(dst->encoding());
  7.1800    assert(isShiftCount(imm8), "illegal shift count");
  7.1801    if (imm8 == 1) {
  7.1802 -    emit_byte(0xD1);
  7.1803 -    emit_byte(0xF8 | encode);
  7.1804 +    emit_int8((unsigned char)0xD1);
  7.1805 +    emit_int8((unsigned char)(0xF8 | encode));
  7.1806    } else {
  7.1807 -    emit_byte(0xC1);
  7.1808 -    emit_byte(0xF8 | encode);
  7.1809 -    emit_byte(imm8);
  7.1810 +    emit_int8((unsigned char)0xC1);
  7.1811 +    emit_int8((unsigned char)(0xF8 | encode));
  7.1812 +    emit_int8(imm8);
  7.1813    }
  7.1814  }
  7.1815  
  7.1816  void Assembler::sarl(Register dst) {
  7.1817    int encode = prefix_and_encode(dst->encoding());
  7.1818 -  emit_byte(0xD3);
  7.1819 -  emit_byte(0xF8 | encode);
  7.1820 +  emit_int8((unsigned char)0xD3);
  7.1821 +  emit_int8((unsigned char)(0xF8 | encode));
  7.1822  }
  7.1823  
  7.1824  void Assembler::sbbl(Address dst, int32_t imm32) {
  7.1825 @@ -2617,7 +2623,7 @@
  7.1826  void Assembler::sbbl(Register dst, Address src) {
  7.1827    InstructionMark im(this);
  7.1828    prefix(src, dst);
  7.1829 -  emit_byte(0x1B);
  7.1830 +  emit_int8(0x1B);
  7.1831    emit_operand(dst, src);
  7.1832  }
  7.1833  
  7.1834 @@ -2629,47 +2635,47 @@
  7.1835  void Assembler::setb(Condition cc, Register dst) {
  7.1836    assert(0 <= cc && cc < 16, "illegal cc");
  7.1837    int encode = prefix_and_encode(dst->encoding(), true);
  7.1838 -  emit_byte(0x0F);
  7.1839 -  emit_byte(0x90 | cc);
  7.1840 -  emit_byte(0xC0 | encode);
  7.1841 +  emit_int8(0x0F);
  7.1842 +  emit_int8((unsigned char)0x90 | cc);
  7.1843 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1844  }
  7.1845  
  7.1846  void Assembler::shll(Register dst, int imm8) {
  7.1847    assert(isShiftCount(imm8), "illegal shift count");
  7.1848    int encode = prefix_and_encode(dst->encoding());
  7.1849    if (imm8 == 1 ) {
  7.1850 -    emit_byte(0xD1);
  7.1851 -    emit_byte(0xE0 | encode);
  7.1852 +    emit_int8((unsigned char)0xD1);
  7.1853 +    emit_int8((unsigned char)(0xE0 | encode));
  7.1854    } else {
  7.1855 -    emit_byte(0xC1);
  7.1856 -    emit_byte(0xE0 | encode);
  7.1857 -    emit_byte(imm8);
  7.1858 +    emit_int8((unsigned char)0xC1);
  7.1859 +    emit_int8((unsigned char)(0xE0 | encode));
  7.1860 +    emit_int8(imm8);
  7.1861    }
  7.1862  }
  7.1863  
  7.1864  void Assembler::shll(Register dst) {
  7.1865    int encode = prefix_and_encode(dst->encoding());
  7.1866 -  emit_byte(0xD3);
  7.1867 -  emit_byte(0xE0 | encode);
  7.1868 +  emit_int8((unsigned char)0xD3);
  7.1869 +  emit_int8((unsigned char)(0xE0 | encode));
  7.1870  }
  7.1871  
  7.1872  void Assembler::shrl(Register dst, int imm8) {
  7.1873    assert(isShiftCount(imm8), "illegal shift count");
  7.1874    int encode = prefix_and_encode(dst->encoding());
  7.1875 -  emit_byte(0xC1);
  7.1876 -  emit_byte(0xE8 | encode);
  7.1877 -  emit_byte(imm8);
  7.1878 +  emit_int8((unsigned char)0xC1);
  7.1879 +  emit_int8((unsigned char)(0xE8 | encode));
  7.1880 +  emit_int8(imm8);
  7.1881  }
  7.1882  
  7.1883  void Assembler::shrl(Register dst) {
  7.1884    int encode = prefix_and_encode(dst->encoding());
  7.1885 -  emit_byte(0xD3);
  7.1886 -  emit_byte(0xE8 | encode);
  7.1887 +  emit_int8((unsigned char)0xD3);
  7.1888 +  emit_int8((unsigned char)(0xE8 | encode));
  7.1889  }
  7.1890  
  7.1891  // copies a single word from [esi] to [edi]
  7.1892  void Assembler::smovl() {
  7.1893 -  emit_byte(0xA5);
  7.1894 +  emit_int8((unsigned char)0xA5);
  7.1895  }
  7.1896  
  7.1897  void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
  7.1898 @@ -2688,7 +2694,7 @@
  7.1899  }
  7.1900  
  7.1901  void Assembler::std() {
  7.1902 -  emit_byte(0xfd);
  7.1903 +  emit_int8((unsigned char)0xFD);
  7.1904  }
  7.1905  
  7.1906  void Assembler::sqrtss(XMMRegister dst, Address src) {
  7.1907 @@ -2700,8 +2706,8 @@
  7.1908    NOT_LP64(assert(VM_Version::supports_sse(), ""));
  7.1909    InstructionMark im(this);
  7.1910    prefix(dst);
  7.1911 -  emit_byte(0x0F);
  7.1912 -  emit_byte(0xAE);
  7.1913 +  emit_int8(0x0F);
  7.1914 +  emit_int8((unsigned char)0xAE);
  7.1915    emit_operand(as_Register(3), dst);
  7.1916  }
  7.1917  
  7.1918 @@ -2714,7 +2720,7 @@
  7.1919  void Assembler::subl(Address dst, Register src) {
  7.1920    InstructionMark im(this);
  7.1921    prefix(dst, src);
  7.1922 -  emit_byte(0x29);
  7.1923 +  emit_int8(0x29);
  7.1924    emit_operand(src, dst);
  7.1925  }
  7.1926  
  7.1927 @@ -2732,7 +2738,7 @@
  7.1928  void Assembler::subl(Register dst, Address src) {
  7.1929    InstructionMark im(this);
  7.1930    prefix(src, dst);
  7.1931 -  emit_byte(0x2B);
  7.1932 +  emit_int8(0x2B);
  7.1933    emit_operand(dst, src);
  7.1934  }
  7.1935  
  7.1936 @@ -2773,11 +2779,11 @@
  7.1937    // 8bit operands
  7.1938    int encode = dst->encoding();
  7.1939    if (encode == 0) {
  7.1940 -    emit_byte(0xA9);
  7.1941 +    emit_int8((unsigned char)0xA9);
  7.1942    } else {
  7.1943      encode = prefix_and_encode(encode);
  7.1944 -    emit_byte(0xF7);
  7.1945 -    emit_byte(0xC0 | encode);
  7.1946 +    emit_int8((unsigned char)0xF7);
  7.1947 +    emit_int8((unsigned char)(0xC0 | encode));
  7.1948    }
  7.1949    emit_long(imm32);
  7.1950  }
  7.1951 @@ -2790,7 +2796,7 @@
  7.1952  void Assembler::testl(Register dst, Address  src) {
  7.1953    InstructionMark im(this);
  7.1954    prefix(src, dst);
  7.1955 -  emit_byte(0x85);
  7.1956 +  emit_int8((unsigned char)0x85);
  7.1957    emit_operand(dst, src);
  7.1958  }
  7.1959  
  7.1960 @@ -2818,28 +2824,28 @@
  7.1961  void Assembler::xaddl(Address dst, Register src) {
  7.1962    InstructionMark im(this);
  7.1963    prefix(dst, src);
  7.1964 -  emit_byte(0x0F);
  7.1965 -  emit_byte(0xC1);
  7.1966 +  emit_int8(0x0F);
  7.1967 +  emit_int8((unsigned char)0xC1);
  7.1968    emit_operand(src, dst);
  7.1969  }
  7.1970  
  7.1971  void Assembler::xchgl(Register dst, Address src) { // xchg
  7.1972    InstructionMark im(this);
  7.1973    prefix(src, dst);
  7.1974 -  emit_byte(0x87);
  7.1975 +  emit_int8((unsigned char)0x87);
  7.1976    emit_operand(dst, src);
  7.1977  }
  7.1978  
  7.1979  void Assembler::xchgl(Register dst, Register src) {
  7.1980    int encode = prefix_and_encode(dst->encoding(), src->encoding());
  7.1981 -  emit_byte(0x87);
  7.1982 -  emit_byte(0xc0 | encode);
  7.1983 +  emit_int8((unsigned char)0x87);
  7.1984 +  emit_int8((unsigned char)(0xC0 | encode));
  7.1985  }
  7.1986  
  7.1987  void Assembler::xgetbv() {
  7.1988 -  emit_byte(0x0F);
  7.1989 -  emit_byte(0x01);
  7.1990 -  emit_byte(0xD0);
  7.1991 +  emit_int8(0x0F);
  7.1992 +  emit_int8(0x01);
  7.1993 +  emit_int8((unsigned char)0xD0);
  7.1994  }
  7.1995  
  7.1996  void Assembler::xorl(Register dst, int32_t imm32) {
  7.1997 @@ -2850,7 +2856,7 @@
  7.1998  void Assembler::xorl(Register dst, Address src) {
  7.1999    InstructionMark im(this);
  7.2000    prefix(src, dst);
  7.2001 -  emit_byte(0x33);
  7.2002 +  emit_int8(0x33);
  7.2003    emit_operand(dst, src);
  7.2004  }
  7.2005  
  7.2006 @@ -3276,8 +3282,8 @@
  7.2007  void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
  7.2008    assert(VM_Version::supports_sse4_1(), "");
  7.2009    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
  7.2010 -  emit_byte(0x40);
  7.2011 -  emit_byte(0xC0 | encode);
  7.2012 +  emit_int8(0x40);
  7.2013 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2014  }
  7.2015  
  7.2016  void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
  7.2017 @@ -3288,8 +3294,8 @@
  7.2018  void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
  7.2019    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2020    int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
  7.2021 -  emit_byte(0x40);
  7.2022 -  emit_byte(0xC0 | encode);
  7.2023 +  emit_int8(0x40);
  7.2024 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2025  }
  7.2026  
  7.2027  void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
  7.2028 @@ -3303,7 +3309,7 @@
  7.2029    int dst_enc = dst->encoding();
  7.2030    int nds_enc = nds->is_valid() ? nds->encoding() : 0;
  7.2031    vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
  7.2032 -  emit_byte(0x40);
  7.2033 +  emit_int8(0x40);
  7.2034    emit_operand(dst, src);
  7.2035  }
  7.2036  
  7.2037 @@ -3312,27 +3318,27 @@
  7.2038    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.2039    // XMM6 is for /6 encoding: 66 0F 71 /6 ib
  7.2040    int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
  7.2041 -  emit_byte(0x71);
  7.2042 -  emit_byte(0xC0 | encode);
  7.2043 -  emit_byte(shift & 0xFF);
  7.2044 +  emit_int8(0x71);
  7.2045 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2046 +  emit_int8(shift & 0xFF);
  7.2047  }
  7.2048  
  7.2049  void Assembler::pslld(XMMRegister dst, int shift) {
  7.2050    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.2051    // XMM6 is for /6 encoding: 66 0F 72 /6 ib
  7.2052    int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
  7.2053 -  emit_byte(0x72);
  7.2054 -  emit_byte(0xC0 | encode);
  7.2055 -  emit_byte(shift & 0xFF);
  7.2056 +  emit_int8(0x72);
  7.2057 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2058 +  emit_int8(shift & 0xFF);
  7.2059  }
  7.2060  
  7.2061  void Assembler::psllq(XMMRegister dst, int shift) {
  7.2062    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.2063    // XMM6 is for /6 encoding: 66 0F 73 /6 ib
  7.2064    int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
  7.2065 -  emit_byte(0x73);
  7.2066 -  emit_byte(0xC0 | encode);
  7.2067 -  emit_byte(shift & 0xFF);
  7.2068 +  emit_int8(0x73);
  7.2069 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2070 +  emit_int8(shift & 0xFF);
  7.2071  }
  7.2072  
  7.2073  void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
  7.2074 @@ -3354,21 +3360,21 @@
  7.2075    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2076    // XMM6 is for /6 encoding: 66 0F 71 /6 ib
  7.2077    emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
  7.2078 -  emit_byte(shift & 0xFF);
  7.2079 +  emit_int8(shift & 0xFF);
  7.2080  }
  7.2081  
  7.2082  void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
  7.2083    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2084    // XMM6 is for /6 encoding: 66 0F 72 /6 ib
  7.2085    emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
  7.2086 -  emit_byte(shift & 0xFF);
  7.2087 +  emit_int8(shift & 0xFF);
  7.2088  }
  7.2089  
  7.2090  void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
  7.2091    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2092    // XMM6 is for /6 encoding: 66 0F 73 /6 ib
  7.2093    emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
  7.2094 -  emit_byte(shift & 0xFF);
  7.2095 +  emit_int8(shift & 0xFF);
  7.2096  }
  7.2097  
  7.2098  void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
  7.2099 @@ -3391,18 +3397,18 @@
  7.2100    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.2101    // XMM2 is for /2 encoding: 66 0F 71 /2 ib
  7.2102    int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
  7.2103 -  emit_byte(0x71);
  7.2104 -  emit_byte(0xC0 | encode);
  7.2105 -  emit_byte(shift & 0xFF);
  7.2106 +  emit_int8(0x71);
  7.2107 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2108 +  emit_int8(shift & 0xFF);
  7.2109  }
  7.2110  
  7.2111  void Assembler::psrld(XMMRegister dst, int shift) {
  7.2112    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.2113    // XMM2 is for /2 encoding: 66 0F 72 /2 ib
  7.2114    int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
  7.2115 -  emit_byte(0x72);
  7.2116 -  emit_byte(0xC0 | encode);
  7.2117 -  emit_byte(shift & 0xFF);
  7.2118 +  emit_int8(0x72);
  7.2119 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2120 +  emit_int8(shift & 0xFF);
  7.2121  }
  7.2122  
  7.2123  void Assembler::psrlq(XMMRegister dst, int shift) {
  7.2124 @@ -3411,9 +3417,9 @@
  7.2125    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.2126    // XMM2 is for /2 encoding: 66 0F 73 /2 ib
  7.2127    int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
  7.2128 -  emit_byte(0x73);
  7.2129 -  emit_byte(0xC0 | encode);
  7.2130 -  emit_byte(shift & 0xFF);
  7.2131 +  emit_int8(0x73);
  7.2132 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2133 +  emit_int8(shift & 0xFF);
  7.2134  }
  7.2135  
  7.2136  void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
  7.2137 @@ -3435,21 +3441,21 @@
  7.2138    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2139    // XMM2 is for /2 encoding: 66 0F 73 /2 ib
  7.2140    emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
  7.2141 -  emit_byte(shift & 0xFF);
  7.2142 +  emit_int8(shift & 0xFF);
  7.2143  }
  7.2144  
  7.2145  void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
  7.2146    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2147    // XMM2 is for /2 encoding: 66 0F 73 /2 ib
  7.2148    emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
  7.2149 -  emit_byte(shift & 0xFF);
  7.2150 +  emit_int8(shift & 0xFF);
  7.2151  }
  7.2152  
  7.2153  void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
  7.2154    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2155    // XMM2 is for /2 encoding: 66 0F 73 /2 ib
  7.2156    emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
  7.2157 -  emit_byte(shift & 0xFF);
  7.2158 +  emit_int8(shift & 0xFF);
  7.2159  }
  7.2160  
  7.2161  void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
  7.2162 @@ -3472,18 +3478,18 @@
  7.2163    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.2164    // XMM4 is for /4 encoding: 66 0F 71 /4 ib
  7.2165    int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
  7.2166 -  emit_byte(0x71);
  7.2167 -  emit_byte(0xC0 | encode);
  7.2168 -  emit_byte(shift & 0xFF);
  7.2169 +  emit_int8(0x71);
  7.2170 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2171 +  emit_int8(shift & 0xFF);
  7.2172  }
  7.2173  
  7.2174  void Assembler::psrad(XMMRegister dst, int shift) {
  7.2175    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.2176    // XMM4 is for /4 encoding: 66 0F 72 /4 ib
  7.2177    int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
  7.2178 -  emit_byte(0x72);
  7.2179 -  emit_byte(0xC0 | encode);
  7.2180 -  emit_byte(shift & 0xFF);
  7.2181 +  emit_int8(0x72);
  7.2182 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2183 +  emit_int8(shift & 0xFF);
  7.2184  }
  7.2185  
  7.2186  void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
  7.2187 @@ -3500,14 +3506,14 @@
  7.2188    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2189    // XMM4 is for /4 encoding: 66 0F 71 /4 ib
  7.2190    emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
  7.2191 -  emit_byte(shift & 0xFF);
  7.2192 +  emit_int8(shift & 0xFF);
  7.2193  }
  7.2194  
  7.2195  void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
  7.2196    assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
  7.2197    // XMM4 is for /4 encoding: 66 0F 71 /4 ib
  7.2198    emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
  7.2199 -  emit_byte(shift & 0xFF);
  7.2200 +  emit_int8(shift & 0xFF);
  7.2201  }
  7.2202  
  7.2203  void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
  7.2204 @@ -3572,11 +3578,11 @@
  7.2205    assert(VM_Version::supports_avx(), "");
  7.2206    bool vector256 = true;
  7.2207    int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
  7.2208 -  emit_byte(0x18);
  7.2209 -  emit_byte(0xC0 | encode);
  7.2210 +  emit_int8(0x18);
  7.2211 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2212    // 0x00 - insert into lower 128 bits
  7.2213    // 0x01 - insert into upper 128 bits
  7.2214 -  emit_byte(0x01);
  7.2215 +  emit_int8(0x01);
  7.2216  }
  7.2217  
  7.2218  void Assembler::vinsertf128h(XMMRegister dst, Address src) {
  7.2219 @@ -3587,10 +3593,10 @@
  7.2220    int dst_enc = dst->encoding();
  7.2221    // swap src<->dst for encoding
  7.2222    vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
  7.2223 -  emit_byte(0x18);
  7.2224 +  emit_int8(0x18);
  7.2225    emit_operand(dst, src);
  7.2226    // 0x01 - insert into upper 128 bits
  7.2227 -  emit_byte(0x01);
  7.2228 +  emit_int8(0x01);
  7.2229  }
  7.2230  
  7.2231  void Assembler::vextractf128h(Address dst, XMMRegister src) {
  7.2232 @@ -3600,21 +3606,21 @@
  7.2233    assert(src != xnoreg, "sanity");
  7.2234    int src_enc = src->encoding();
  7.2235    vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
  7.2236 -  emit_byte(0x19);
  7.2237 +  emit_int8(0x19);
  7.2238    emit_operand(src, dst);
  7.2239    // 0x01 - extract from upper 128 bits
  7.2240 -  emit_byte(0x01);
  7.2241 +  emit_int8(0x01);
  7.2242  }
  7.2243  
  7.2244  void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
  7.2245    assert(VM_Version::supports_avx2(), "");
  7.2246    bool vector256 = true;
  7.2247    int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
  7.2248 -  emit_byte(0x38);
  7.2249 -  emit_byte(0xC0 | encode);
  7.2250 +  emit_int8(0x38);
  7.2251 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2252    // 0x00 - insert into lower 128 bits
  7.2253    // 0x01 - insert into upper 128 bits
  7.2254 -  emit_byte(0x01);
  7.2255 +  emit_int8(0x01);
  7.2256  }
  7.2257  
  7.2258  void Assembler::vinserti128h(XMMRegister dst, Address src) {
  7.2259 @@ -3625,10 +3631,10 @@
  7.2260    int dst_enc = dst->encoding();
  7.2261    // swap src<->dst for encoding
  7.2262    vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
  7.2263 -  emit_byte(0x38);
  7.2264 +  emit_int8(0x38);
  7.2265    emit_operand(dst, src);
  7.2266    // 0x01 - insert into upper 128 bits
  7.2267 -  emit_byte(0x01);
  7.2268 +  emit_int8(0x01);
  7.2269  }
  7.2270  
  7.2271  void Assembler::vextracti128h(Address dst, XMMRegister src) {
  7.2272 @@ -3638,16 +3644,16 @@
  7.2273    assert(src != xnoreg, "sanity");
  7.2274    int src_enc = src->encoding();
  7.2275    vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
  7.2276 -  emit_byte(0x39);
  7.2277 +  emit_int8(0x39);
  7.2278    emit_operand(src, dst);
  7.2279    // 0x01 - extract from upper 128 bits
  7.2280 -  emit_byte(0x01);
  7.2281 +  emit_int8(0x01);
  7.2282  }
  7.2283  
  7.2284  void Assembler::vzeroupper() {
  7.2285    assert(VM_Version::supports_avx(), "");
  7.2286    (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
  7.2287 -  emit_byte(0x77);
  7.2288 +  emit_int8(0x77);
  7.2289  }
  7.2290  
  7.2291  
  7.2292 @@ -3657,15 +3663,15 @@
  7.2293  void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
  7.2294    // NO PREFIX AS NEVER 64BIT
  7.2295    InstructionMark im(this);
  7.2296 -  emit_byte(0x81);
  7.2297 -  emit_byte(0xF8 | src1->encoding());
  7.2298 +  emit_int8((unsigned char)0x81);
  7.2299 +  emit_int8((unsigned char)(0xF8 | src1->encoding()));
  7.2300    emit_data(imm32, rspec, 0);
  7.2301  }
  7.2302  
  7.2303  void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
  7.2304    // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
  7.2305    InstructionMark im(this);
  7.2306 -  emit_byte(0x81);
  7.2307 +  emit_int8((unsigned char)0x81);
  7.2308    emit_operand(rdi, src1);
  7.2309    emit_data(imm32, rspec, 0);
  7.2310  }
  7.2311 @@ -3675,14 +3681,14 @@
  7.2312  // into rdx:rax.  The ZF is set if the compared values were equal, and cleared otherwise.
  7.2313  void Assembler::cmpxchg8(Address adr) {
  7.2314    InstructionMark im(this);
  7.2315 -  emit_byte(0x0F);
  7.2316 -  emit_byte(0xc7);
  7.2317 +  emit_int8(0x0F);
  7.2318 +  emit_int8((unsigned char)0xC7);
  7.2319    emit_operand(rcx, adr);
  7.2320  }
  7.2321  
  7.2322  void Assembler::decl(Register dst) {
  7.2323    // Don't use it directly. Use MacroAssembler::decrementl() instead.
  7.2324 - emit_byte(0x48 | dst->encoding());
  7.2325 + emit_int8(0x48 | dst->encoding());
  7.2326  }
  7.2327  
  7.2328  #endif // _LP64
  7.2329 @@ -3690,8 +3696,8 @@
  7.2330  // 64bit typically doesn't use the x87 but needs to for the trig funcs
  7.2331  
  7.2332  void Assembler::fabs() {
  7.2333 -  emit_byte(0xD9);
  7.2334 -  emit_byte(0xE1);
  7.2335 +  emit_int8((unsigned char)0xD9);
  7.2336 +  emit_int8((unsigned char)0xE1);
  7.2337  }
  7.2338  
  7.2339  void Assembler::fadd(int i) {
  7.2340 @@ -3700,13 +3706,13 @@
  7.2341  
  7.2342  void Assembler::fadd_d(Address src) {
  7.2343    InstructionMark im(this);
  7.2344 -  emit_byte(0xDC);
  7.2345 +  emit_int8((unsigned char)0xDC);
  7.2346    emit_operand32(rax, src);
  7.2347  }
  7.2348  
  7.2349  void Assembler::fadd_s(Address src) {
  7.2350    InstructionMark im(this);
  7.2351 -  emit_byte(0xD8);
  7.2352 +  emit_int8((unsigned char)0xD8);
  7.2353    emit_operand32(rax, src);
  7.2354  }
  7.2355  
  7.2356 @@ -3719,8 +3725,8 @@
  7.2357  }
  7.2358  
  7.2359  void Assembler::fchs() {
  7.2360 -  emit_byte(0xD9);
  7.2361 -  emit_byte(0xE0);
  7.2362 +  emit_int8((unsigned char)0xD9);
  7.2363 +  emit_int8((unsigned char)0xE0);
  7.2364  }
  7.2365  
  7.2366  void Assembler::fcom(int i) {
  7.2367 @@ -3733,29 +3739,29 @@
  7.2368  
  7.2369  void Assembler::fcomp_d(Address src) {
  7.2370    InstructionMark im(this);
  7.2371 -  emit_byte(0xDC);
  7.2372 +  emit_int8((unsigned char)0xDC);
  7.2373    emit_operand32(rbx, src);
  7.2374  }
  7.2375  
  7.2376  void Assembler::fcomp_s(Address src) {
  7.2377    InstructionMark im(this);
  7.2378 -  emit_byte(0xD8);
  7.2379 +  emit_int8((unsigned char)0xD8);
  7.2380    emit_operand32(rbx, src);
  7.2381  }
  7.2382  
  7.2383  void Assembler::fcompp() {
  7.2384 -  emit_byte(0xDE);
  7.2385 -  emit_byte(0xD9);
  7.2386 +  emit_int8((unsigned char)0xDE);
  7.2387 +  emit_int8((unsigned char)0xD9);
  7.2388  }
  7.2389  
  7.2390  void Assembler::fcos() {
  7.2391 -  emit_byte(0xD9);
  7.2392 -  emit_byte(0xFF);
  7.2393 +  emit_int8((unsigned char)0xD9);
  7.2394 +  emit_int8((unsigned char)0xFF);
  7.2395  }
  7.2396  
  7.2397  void Assembler::fdecstp() {
  7.2398 -  emit_byte(0xD9);
  7.2399 -  emit_byte(0xF6);
  7.2400 +  emit_int8((unsigned char)0xD9);
  7.2401 +  emit_int8((unsigned char)0xF6);
  7.2402  }
  7.2403  
  7.2404  void Assembler::fdiv(int i) {
  7.2405 @@ -3764,13 +3770,13 @@
  7.2406  
  7.2407  void Assembler::fdiv_d(Address src) {
  7.2408    InstructionMark im(this);
  7.2409 -  emit_byte(0xDC);
  7.2410 +  emit_int8((unsigned char)0xDC);
  7.2411    emit_operand32(rsi, src);
  7.2412  }
  7.2413  
  7.2414  void Assembler::fdiv_s(Address src) {
  7.2415    InstructionMark im(this);
  7.2416 -  emit_byte(0xD8);
  7.2417 +  emit_int8((unsigned char)0xD8);
  7.2418    emit_operand32(rsi, src);
  7.2419  }
  7.2420  
  7.2421 @@ -3791,13 +3797,13 @@
  7.2422  
  7.2423  void Assembler::fdivr_d(Address src) {
  7.2424    InstructionMark im(this);
  7.2425 -  emit_byte(0xDC);
  7.2426 +  emit_int8((unsigned char)0xDC);
  7.2427    emit_operand32(rdi, src);
  7.2428  }
  7.2429  
  7.2430  void Assembler::fdivr_s(Address src) {
  7.2431    InstructionMark im(this);
  7.2432 -  emit_byte(0xD8);
  7.2433 +  emit_int8((unsigned char)0xD8);
  7.2434    emit_operand32(rdi, src);
  7.2435  }
  7.2436  
  7.2437 @@ -3815,59 +3821,59 @@
  7.2438  
  7.2439  void Assembler::fild_d(Address adr) {
  7.2440    InstructionMark im(this);
  7.2441 -  emit_byte(0xDF);
  7.2442 +  emit_int8((unsigned char)0xDF);
  7.2443    emit_operand32(rbp, adr);
  7.2444  }
  7.2445  
  7.2446  void Assembler::fild_s(Address adr) {
  7.2447    InstructionMark im(this);
  7.2448 -  emit_byte(0xDB);
  7.2449 +  emit_int8((unsigned char)0xDB);
  7.2450    emit_operand32(rax, adr);
  7.2451  }
  7.2452  
  7.2453  void Assembler::fincstp() {
  7.2454 -  emit_byte(0xD9);
  7.2455 -  emit_byte(0xF7);
  7.2456 +  emit_int8((unsigned char)0xD9);
  7.2457 +  emit_int8((unsigned char)0xF7);
  7.2458  }
  7.2459  
  7.2460  void Assembler::finit() {
  7.2461 -  emit_byte(0x9B);
  7.2462 -  emit_byte(0xDB);
  7.2463 -  emit_byte(0xE3);
  7.2464 +  emit_int8((unsigned char)0x9B);
  7.2465 +  emit_int8((unsigned char)0xDB);
  7.2466 +  emit_int8((unsigned char)0xE3);
  7.2467  }
  7.2468  
  7.2469  void Assembler::fist_s(Address adr) {
  7.2470    InstructionMark im(this);
  7.2471 -  emit_byte(0xDB);
  7.2472 +  emit_int8((unsigned char)0xDB);
  7.2473    emit_operand32(rdx, adr);
  7.2474  }
  7.2475  
  7.2476  void Assembler::fistp_d(Address adr) {
  7.2477    InstructionMark im(this);
  7.2478 -  emit_byte(0xDF);
  7.2479 +  emit_int8((unsigned char)0xDF);
  7.2480    emit_operand32(rdi, adr);
  7.2481  }
  7.2482  
  7.2483  void Assembler::fistp_s(Address adr) {
  7.2484    InstructionMark im(this);
  7.2485 -  emit_byte(0xDB);
  7.2486 +  emit_int8((unsigned char)0xDB);
  7.2487    emit_operand32(rbx, adr);
  7.2488  }
  7.2489  
  7.2490  void Assembler::fld1() {
  7.2491 -  emit_byte(0xD9);
  7.2492 -  emit_byte(0xE8);
  7.2493 +  emit_int8((unsigned char)0xD9);
  7.2494 +  emit_int8((unsigned char)0xE8);
  7.2495  }
  7.2496  
  7.2497  void Assembler::fld_d(Address adr) {
  7.2498    InstructionMark im(this);
  7.2499 -  emit_byte(0xDD);
  7.2500 +  emit_int8((unsigned char)0xDD);
  7.2501    emit_operand32(rax, adr);
  7.2502  }
  7.2503  
  7.2504  void Assembler::fld_s(Address adr) {
  7.2505    InstructionMark im(this);
  7.2506 -  emit_byte(0xD9);
  7.2507 +  emit_int8((unsigned char)0xD9);
  7.2508    emit_operand32(rax, adr);
  7.2509  }
  7.2510  
  7.2511 @@ -3878,35 +3884,35 @@
  7.2512  
  7.2513  void Assembler::fld_x(Address adr) {
  7.2514    InstructionMark im(this);
  7.2515 -  emit_byte(0xDB);
  7.2516 +  emit_int8((unsigned char)0xDB);
  7.2517    emit_operand32(rbp, adr);
  7.2518  }
  7.2519  
  7.2520  void Assembler::fldcw(Address src) {
  7.2521    InstructionMark im(this);
  7.2522 -  emit_byte(0xd9);
  7.2523 +  emit_int8((unsigned char)0xD9);
  7.2524    emit_operand32(rbp, src);
  7.2525  }
  7.2526  
  7.2527  void Assembler::fldenv(Address src) {
  7.2528    InstructionMark im(this);
  7.2529 -  emit_byte(0xD9);
  7.2530 +  emit_int8((unsigned char)0xD9);
  7.2531    emit_operand32(rsp, src);
  7.2532  }
  7.2533  
  7.2534  void Assembler::fldlg2() {
  7.2535 -  emit_byte(0xD9);
  7.2536 -  emit_byte(0xEC);
  7.2537 +  emit_int8((unsigned char)0xD9);
  7.2538 +  emit_int8((unsigned char)0xEC);
  7.2539  }
  7.2540  
  7.2541  void Assembler::fldln2() {
  7.2542 -  emit_byte(0xD9);
  7.2543 -  emit_byte(0xED);
  7.2544 +  emit_int8((unsigned char)0xD9);
  7.2545 +  emit_int8((unsigned char)0xED);
  7.2546  }
  7.2547  
  7.2548  void Assembler::fldz() {
  7.2549 -  emit_byte(0xD9);
  7.2550 -  emit_byte(0xEE);
  7.2551 +  emit_int8((unsigned char)0xD9);
  7.2552 +  emit_int8((unsigned char)0xEE);
  7.2553  }
  7.2554  
  7.2555  void Assembler::flog() {
  7.2556 @@ -3927,13 +3933,13 @@
  7.2557  
  7.2558  void Assembler::fmul_d(Address src) {
  7.2559    InstructionMark im(this);
  7.2560 -  emit_byte(0xDC);
  7.2561 +  emit_int8((unsigned char)0xDC);
  7.2562    emit_operand32(rcx, src);
  7.2563  }
  7.2564  
  7.2565  void Assembler::fmul_s(Address src) {
  7.2566    InstructionMark im(this);
  7.2567 -  emit_byte(0xD8);
  7.2568 +  emit_int8((unsigned char)0xD8);
  7.2569    emit_operand32(rcx, src);
  7.2570  }
  7.2571  
  7.2572 @@ -3947,63 +3953,63 @@
  7.2573  
  7.2574  void Assembler::fnsave(Address dst) {
  7.2575    InstructionMark im(this);
  7.2576 -  emit_byte(0xDD);
  7.2577 +  emit_int8((unsigned char)0xDD);
  7.2578    emit_operand32(rsi, dst);
  7.2579  }
  7.2580  
  7.2581  void Assembler::fnstcw(Address src) {
  7.2582    InstructionMark im(this);
  7.2583 -  emit_byte(0x9B);
  7.2584 -  emit_byte(0xD9);
  7.2585 +  emit_int8((unsigned char)0x9B);
  7.2586 +  emit_int8((unsigned char)0xD9);
  7.2587    emit_operand32(rdi, src);
  7.2588  }
  7.2589  
  7.2590  void Assembler::fnstsw_ax() {
  7.2591 -  emit_byte(0xdF);
  7.2592 -  emit_byte(0xE0);
  7.2593 +  emit_int8((unsigned char)0xDF);
  7.2594 +  emit_int8((unsigned char)0xE0);
  7.2595  }
  7.2596  
  7.2597  void Assembler::fprem() {
  7.2598 -  emit_byte(0xD9);
  7.2599 -  emit_byte(0xF8);
  7.2600 +  emit_int8((unsigned char)0xD9);
  7.2601 +  emit_int8((unsigned char)0xF8);
  7.2602  }
  7.2603  
  7.2604  void Assembler::fprem1() {
  7.2605 -  emit_byte(0xD9);
  7.2606 -  emit_byte(0xF5);
  7.2607 +  emit_int8((unsigned char)0xD9);
  7.2608 +  emit_int8((unsigned char)0xF5);
  7.2609  }
  7.2610  
  7.2611  void Assembler::frstor(Address src) {
  7.2612    InstructionMark im(this);
  7.2613 -  emit_byte(0xDD);
  7.2614 +  emit_int8((unsigned char)0xDD);
  7.2615    emit_operand32(rsp, src);
  7.2616  }
  7.2617  
  7.2618  void Assembler::fsin() {
  7.2619 -  emit_byte(0xD9);
  7.2620 -  emit_byte(0xFE);
  7.2621 +  emit_int8((unsigned char)0xD9);
  7.2622 +  emit_int8((unsigned char)0xFE);
  7.2623  }
  7.2624  
  7.2625  void Assembler::fsqrt() {
  7.2626 -  emit_byte(0xD9);
  7.2627 -  emit_byte(0xFA);
  7.2628 +  emit_int8((unsigned char)0xD9);
  7.2629 +  emit_int8((unsigned char)0xFA);
  7.2630  }
  7.2631  
  7.2632  void Assembler::fst_d(Address adr) {
  7.2633    InstructionMark im(this);
  7.2634 -  emit_byte(0xDD);
  7.2635 +  emit_int8((unsigned char)0xDD);
  7.2636    emit_operand32(rdx, adr);
  7.2637  }
  7.2638  
  7.2639  void Assembler::fst_s(Address adr) {
  7.2640    InstructionMark im(this);
  7.2641 -  emit_byte(0xD9);
  7.2642 +  emit_int8((unsigned char)0xD9);
  7.2643    emit_operand32(rdx, adr);
  7.2644  }
  7.2645  
  7.2646  void Assembler::fstp_d(Address adr) {
  7.2647    InstructionMark im(this);
  7.2648 -  emit_byte(0xDD);
  7.2649 +  emit_int8((unsigned char)0xDD);
  7.2650    emit_operand32(rbx, adr);
  7.2651  }
  7.2652  
  7.2653 @@ -4013,13 +4019,13 @@
  7.2654  
  7.2655  void Assembler::fstp_s(Address adr) {
  7.2656    InstructionMark im(this);
  7.2657 -  emit_byte(0xD9);
  7.2658 +  emit_int8((unsigned char)0xD9);
  7.2659    emit_operand32(rbx, adr);
  7.2660  }
  7.2661  
  7.2662  void Assembler::fstp_x(Address adr) {
  7.2663    InstructionMark im(this);
  7.2664 -  emit_byte(0xDB);
  7.2665 +  emit_int8((unsigned char)0xDB);
  7.2666    emit_operand32(rdi, adr);
  7.2667  }
  7.2668  
  7.2669 @@ -4029,13 +4035,13 @@
  7.2670  
  7.2671  void Assembler::fsub_d(Address src) {
  7.2672    InstructionMark im(this);
  7.2673 -  emit_byte(0xDC);
  7.2674 +  emit_int8((unsigned char)0xDC);
  7.2675    emit_operand32(rsp, src);
  7.2676  }
  7.2677  
  7.2678  void Assembler::fsub_s(Address src) {
  7.2679    InstructionMark im(this);
  7.2680 -  emit_byte(0xD8);
  7.2681 +  emit_int8((unsigned char)0xD8);
  7.2682    emit_operand32(rsp, src);
  7.2683  }
  7.2684  
  7.2685 @@ -4053,13 +4059,13 @@
  7.2686  
  7.2687  void Assembler::fsubr_d(Address src) {
  7.2688    InstructionMark im(this);
  7.2689 -  emit_byte(0xDC);
  7.2690 +  emit_int8((unsigned char)0xDC);
  7.2691    emit_operand32(rbp, src);
  7.2692  }
  7.2693  
  7.2694  void Assembler::fsubr_s(Address src) {
  7.2695    InstructionMark im(this);
  7.2696 -  emit_byte(0xD8);
  7.2697 +  emit_int8((unsigned char)0xD8);
  7.2698    emit_operand32(rbp, src);
  7.2699  }
  7.2700  
  7.2701 @@ -4072,15 +4078,15 @@
  7.2702  }
  7.2703  
  7.2704  void Assembler::ftan() {
  7.2705 -  emit_byte(0xD9);
  7.2706 -  emit_byte(0xF2);
  7.2707 -  emit_byte(0xDD);
  7.2708 -  emit_byte(0xD8);
  7.2709 +  emit_int8((unsigned char)0xD9);
  7.2710 +  emit_int8((unsigned char)0xF2);
  7.2711 +  emit_int8((unsigned char)0xDD);
  7.2712 +  emit_int8((unsigned char)0xD8);
  7.2713  }
  7.2714  
  7.2715  void Assembler::ftst() {
  7.2716 -  emit_byte(0xD9);
  7.2717 -  emit_byte(0xE4);
  7.2718 +  emit_int8((unsigned char)0xD9);
  7.2719 +  emit_int8((unsigned char)0xE4);
  7.2720  }
  7.2721  
  7.2722  void Assembler::fucomi(int i) {
  7.2723 @@ -4096,7 +4102,7 @@
  7.2724  }
  7.2725  
  7.2726  void Assembler::fwait() {
  7.2727 -  emit_byte(0x9B);
  7.2728 +  emit_int8((unsigned char)0x9B);
  7.2729  }
  7.2730  
  7.2731  void Assembler::fxch(int i) {
  7.2732 @@ -4104,23 +4110,23 @@
  7.2733  }
  7.2734  
  7.2735  void Assembler::fyl2x() {
  7.2736 -  emit_byte(0xD9);
  7.2737 -  emit_byte(0xF1);
  7.2738 +  emit_int8((unsigned char)0xD9);
  7.2739 +  emit_int8((unsigned char)0xF1);
  7.2740  }
  7.2741  
  7.2742  void Assembler::frndint() {
  7.2743 -  emit_byte(0xD9);
  7.2744 -  emit_byte(0xFC);
  7.2745 +  emit_int8((unsigned char)0xD9);
  7.2746 +  emit_int8((unsigned char)0xFC);
  7.2747  }
  7.2748  
  7.2749  void Assembler::f2xm1() {
  7.2750 -  emit_byte(0xD9);
  7.2751 -  emit_byte(0xF0);
  7.2752 +  emit_int8((unsigned char)0xD9);
  7.2753 +  emit_int8((unsigned char)0xF0);
  7.2754  }
  7.2755  
  7.2756  void Assembler::fldl2e() {
  7.2757 -  emit_byte(0xD9);
  7.2758 -  emit_byte(0xEA);
  7.2759 +  emit_int8((unsigned char)0xD9);
  7.2760 +  emit_int8((unsigned char)0xEA);
  7.2761  }
  7.2762  
  7.2763  // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
  7.2764 @@ -4131,7 +4137,7 @@
  7.2765  // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
  7.2766  void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
  7.2767    if (pre > 0) {
  7.2768 -    emit_byte(simd_pre[pre]);
  7.2769 +    emit_int8(simd_pre[pre]);
  7.2770    }
  7.2771    if (rex_w) {
  7.2772      prefixq(adr, xreg);
  7.2773 @@ -4139,25 +4145,25 @@
  7.2774      prefix(adr, xreg);
  7.2775    }
  7.2776    if (opc > 0) {
  7.2777 -    emit_byte(0x0F);
  7.2778 +    emit_int8(0x0F);
  7.2779      int opc2 = simd_opc[opc];
  7.2780      if (opc2 > 0) {
  7.2781 -      emit_byte(opc2);
  7.2782 +      emit_int8(opc2);
  7.2783      }
  7.2784    }
  7.2785  }
  7.2786  
  7.2787  int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
  7.2788    if (pre > 0) {
  7.2789 -    emit_byte(simd_pre[pre]);
  7.2790 +    emit_int8(simd_pre[pre]);
  7.2791    }
  7.2792    int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
  7.2793                            prefix_and_encode(dst_enc, src_enc);
  7.2794    if (opc > 0) {
  7.2795 -    emit_byte(0x0F);
  7.2796 +    emit_int8(0x0F);
  7.2797      int opc2 = simd_opc[opc];
  7.2798      if (opc2 > 0) {
  7.2799 -      emit_byte(opc2);
  7.2800 +      emit_int8(opc2);
  7.2801      }
  7.2802    }
  7.2803    return encode;
  7.2804 @@ -4171,11 +4177,11 @@
  7.2805      int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
  7.2806      byte1 = (~byte1) & 0xE0;
  7.2807      byte1 |= opc;
  7.2808 -    a_byte(byte1);
  7.2809 +    emit_int8(byte1);
  7.2810  
  7.2811      int byte2 = ((~nds_enc) & 0xf) << 3;
  7.2812      byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
  7.2813 -    emit_byte(byte2);
  7.2814 +    emit_int8(byte2);
  7.2815    } else {
  7.2816      prefix(VEX_2bytes);
  7.2817  
  7.2818 @@ -4183,7 +4189,7 @@
  7.2819      byte1 = (~byte1) & 0x80;
  7.2820      byte1 |= ((~nds_enc) & 0xf) << 3;
  7.2821      byte1 |= (vector256 ? 4 : 0) | pre;
  7.2822 -    emit_byte(byte1);
  7.2823 +    emit_int8(byte1);
  7.2824    }
  7.2825  }
  7.2826  
  7.2827 @@ -4229,28 +4235,28 @@
  7.2828  void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
  7.2829    InstructionMark im(this);
  7.2830    simd_prefix(dst, dst, src, pre);
  7.2831 -  emit_byte(opcode);
  7.2832 +  emit_int8(opcode);
  7.2833    emit_operand(dst, src);
  7.2834  }
  7.2835  
  7.2836  void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
  7.2837    int encode = simd_prefix_and_encode(dst, dst, src, pre);
  7.2838 -  emit_byte(opcode);
  7.2839 -  emit_byte(0xC0 | encode);
  7.2840 +  emit_int8(opcode);
  7.2841 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2842  }
  7.2843  
  7.2844  // Versions with no second source register (non-destructive source).
  7.2845  void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
  7.2846    InstructionMark im(this);
  7.2847    simd_prefix(dst, xnoreg, src, pre);
  7.2848 -  emit_byte(opcode);
  7.2849 +  emit_int8(opcode);
  7.2850    emit_operand(dst, src);
  7.2851  }
  7.2852  
  7.2853  void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
  7.2854    int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
  7.2855 -  emit_byte(opcode);
  7.2856 -  emit_byte(0xC0 | encode);
  7.2857 +  emit_int8(opcode);
  7.2858 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2859  }
  7.2860  
  7.2861  // 3-operands AVX instructions
  7.2862 @@ -4258,22 +4264,22 @@
  7.2863                                 Address src, VexSimdPrefix pre, bool vector256) {
  7.2864    InstructionMark im(this);
  7.2865    vex_prefix(dst, nds, src, pre, vector256);
  7.2866 -  emit_byte(opcode);
  7.2867 +  emit_int8(opcode);
  7.2868    emit_operand(dst, src);
  7.2869  }
  7.2870  
  7.2871  void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
  7.2872                                 XMMRegister src, VexSimdPrefix pre, bool vector256) {
  7.2873    int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
  7.2874 -  emit_byte(opcode);
  7.2875 -  emit_byte(0xC0 | encode);
  7.2876 +  emit_int8(opcode);
  7.2877 +  emit_int8((unsigned char)(0xC0 | encode));
  7.2878  }
  7.2879  
  7.2880  #ifndef _LP64
  7.2881  
  7.2882  void Assembler::incl(Register dst) {
  7.2883    // Don't use it directly. Use MacroAssembler::incrementl() instead.
  7.2884 -  emit_byte(0x40 | dst->encoding());
  7.2885 +  emit_int8(0x40 | dst->encoding());
  7.2886  }
  7.2887  
  7.2888  void Assembler::lea(Register dst, Address src) {
  7.2889 @@ -4282,7 +4288,7 @@
  7.2890  
  7.2891  void Assembler::mov_literal32(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
  7.2892    InstructionMark im(this);
  7.2893 -  emit_byte(0xC7);
  7.2894 +  emit_int8((unsigned char)0xC7);
  7.2895    emit_operand(rax, dst);
  7.2896    emit_data((int)imm32, rspec, 0);
  7.2897  }
  7.2898 @@ -4290,49 +4296,49 @@
  7.2899  void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
  7.2900    InstructionMark im(this);
  7.2901    int encode = prefix_and_encode(dst->encoding());
  7.2902 -  emit_byte(0xB8 | encode);
  7.2903 +  emit_int8((unsigned char)(0xB8 | encode));
  7.2904    emit_data((int)imm32, rspec, 0);
  7.2905  }
  7.2906  
  7.2907  void Assembler::popa() { // 32bit
  7.2908 -  emit_byte(0x61);
  7.2909 +  emit_int8(0x61);
  7.2910  }
  7.2911  
  7.2912  void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
  7.2913    InstructionMark im(this);
  7.2914 -  emit_byte(0x68);
  7.2915 +  emit_int8(0x68);
  7.2916    emit_data(imm32, rspec, 0);
  7.2917  }
  7.2918  
  7.2919  void Assembler::pusha() { // 32bit
  7.2920 -  emit_byte(0x60);
  7.2921 +  emit_int8(0x60);
  7.2922  }
  7.2923  
  7.2924  void Assembler::set_byte_if_not_zero(Register dst) {
  7.2925 -  emit_byte(0x0F);
  7.2926 -  emit_byte(0x95);
  7.2927 -  emit_byte(0xE0 | dst->encoding());
  7.2928 +  emit_int8(0x0F);
  7.2929 +  emit_int8((unsigned char)0x95);
  7.2930 +  emit_int8((unsigned char)(0xE0 | dst->encoding()));
  7.2931  }
  7.2932  
  7.2933  void Assembler::shldl(Register dst, Register src) {
  7.2934 -  emit_byte(0x0F);
  7.2935 -  emit_byte(0xA5);
  7.2936 -  emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
  7.2937 +  emit_int8(0x0F);
  7.2938 +  emit_int8((unsigned char)0xA5);
  7.2939 +  emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
  7.2940  }
  7.2941  
  7.2942  void Assembler::shrdl(Register dst, Register src) {
  7.2943 -  emit_byte(0x0F);
  7.2944 -  emit_byte(0xAD);
  7.2945 -  emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
  7.2946 +  emit_int8(0x0F);
  7.2947 +  emit_int8((unsigned char)0xAD);
  7.2948 +  emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
  7.2949  }
  7.2950  
  7.2951  #else // LP64
  7.2952  
  7.2953  void Assembler::set_byte_if_not_zero(Register dst) {
  7.2954    int enc = prefix_and_encode(dst->encoding(), true);
  7.2955 -  emit_byte(0x0F);
  7.2956 -  emit_byte(0x95);
  7.2957 -  emit_byte(0xE0 | enc);
  7.2958 +  emit_int8(0x0F);
  7.2959 +  emit_int8((unsigned char)0x95);
  7.2960 +  emit_int8((unsigned char)(0xE0 | enc));
  7.2961  }
  7.2962  
  7.2963  // 64bit only pieces of the assembler
  7.2964 @@ -4670,7 +4676,7 @@
  7.2965  void Assembler::adcq(Register dst, Address src) {
  7.2966    InstructionMark im(this);
  7.2967    prefixq(src, dst);
  7.2968 -  emit_byte(0x13);
  7.2969 +  emit_int8(0x13);
  7.2970    emit_operand(dst, src);
  7.2971  }
  7.2972  
  7.2973 @@ -4688,7 +4694,7 @@
  7.2974  void Assembler::addq(Address dst, Register src) {
  7.2975    InstructionMark im(this);
  7.2976    prefixq(dst, src);
  7.2977 -  emit_byte(0x01);
  7.2978 +  emit_int8(0x01);
  7.2979    emit_operand(src, dst);
  7.2980  }
  7.2981  
  7.2982 @@ -4700,7 +4706,7 @@
  7.2983  void Assembler::addq(Register dst, Address src) {
  7.2984    InstructionMark im(this);
  7.2985    prefixq(src, dst);
  7.2986 -  emit_byte(0x03);
  7.2987 +  emit_int8(0x03);
  7.2988    emit_operand(dst, src);
  7.2989  }
  7.2990  
  7.2991 @@ -4712,7 +4718,7 @@
  7.2992  void Assembler::andq(Address dst, int32_t imm32) {
  7.2993    InstructionMark im(this);
  7.2994    prefixq(dst);
  7.2995 -  emit_byte(0x81);
  7.2996 +  emit_int8((unsigned char)0x81);
  7.2997    emit_operand(rsp, dst, 4);
  7.2998    emit_long(imm32);
  7.2999  }
  7.3000 @@ -4725,7 +4731,7 @@
  7.3001  void Assembler::andq(Register dst, Address src) {
  7.3002    InstructionMark im(this);
  7.3003    prefixq(src, dst);
  7.3004 -  emit_byte(0x23);
  7.3005 +  emit_int8(0x23);
  7.3006    emit_operand(dst, src);
  7.3007  }
  7.3008  
  7.3009 @@ -4736,56 +4742,56 @@
  7.3010  
  7.3011  void Assembler::bsfq(Register dst, Register src) {
  7.3012    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3013 -  emit_byte(0x0F);
  7.3014 -  emit_byte(0xBC);
  7.3015 -  emit_byte(0xC0 | encode);
  7.3016 +  emit_int8(0x0F);
  7.3017 +  emit_int8((unsigned char)0xBC);
  7.3018 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3019  }
  7.3020  
  7.3021  void Assembler::bsrq(Register dst, Register src) {
  7.3022    assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
  7.3023    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3024 -  emit_byte(0x0F);
  7.3025 -  emit_byte(0xBD);
  7.3026 -  emit_byte(0xC0 | encode);
  7.3027 +  emit_int8(0x0F);
  7.3028 +  emit_int8((unsigned char)0xBD);
  7.3029 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3030  }
  7.3031  
  7.3032  void Assembler::bswapq(Register reg) {
  7.3033    int encode = prefixq_and_encode(reg->encoding());
  7.3034 -  emit_byte(0x0F);
  7.3035 -  emit_byte(0xC8 | encode);
  7.3036 +  emit_int8(0x0F);
  7.3037 +  emit_int8((unsigned char)(0xC8 | encode));
  7.3038  }
  7.3039  
  7.3040  void Assembler::cdqq() {
  7.3041    prefix(REX_W);
  7.3042 -  emit_byte(0x99);
  7.3043 +  emit_int8((unsigned char)0x99);
  7.3044  }
  7.3045  
  7.3046  void Assembler::clflush(Address adr) {
  7.3047    prefix(adr);
  7.3048 -  emit_byte(0x0F);
  7.3049 -  emit_byte(0xAE);
  7.3050 +  emit_int8(0x0F);
  7.3051 +  emit_int8((unsigned char)0xAE);
  7.3052    emit_operand(rdi, adr);
  7.3053  }
  7.3054  
  7.3055  void Assembler::cmovq(Condition cc, Register dst, Register src) {
  7.3056    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3057 -  emit_byte(0x0F);
  7.3058 -  emit_byte(0x40 | cc);
  7.3059 -  emit_byte(0xC0 | encode);
  7.3060 +  emit_int8(0x0F);
  7.3061 +  emit_int8(0x40 | cc);
  7.3062 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3063  }
  7.3064  
  7.3065  void Assembler::cmovq(Condition cc, Register dst, Address src) {
  7.3066    InstructionMark im(this);
  7.3067    prefixq(src, dst);
  7.3068 -  emit_byte(0x0F);
  7.3069 -  emit_byte(0x40 | cc);
  7.3070 +  emit_int8(0x0F);
  7.3071 +  emit_int8(0x40 | cc);
  7.3072    emit_operand(dst, src);
  7.3073  }
  7.3074  
  7.3075  void Assembler::cmpq(Address dst, int32_t imm32) {
  7.3076    InstructionMark im(this);
  7.3077    prefixq(dst);
  7.3078 -  emit_byte(0x81);
  7.3079 +  emit_int8((unsigned char)0x81);
  7.3080    emit_operand(rdi, dst, 4);
  7.3081    emit_long(imm32);
  7.3082  }
  7.3083 @@ -4798,7 +4804,7 @@
  7.3084  void Assembler::cmpq(Address dst, Register src) {
  7.3085    InstructionMark im(this);
  7.3086    prefixq(dst, src);
  7.3087 -  emit_byte(0x3B);
  7.3088 +  emit_int8(0x3B);
  7.3089    emit_operand(src, dst);
  7.3090  }
  7.3091  
  7.3092 @@ -4810,122 +4816,122 @@
  7.3093  void Assembler::cmpq(Register dst, Address  src) {
  7.3094    InstructionMark im(this);
  7.3095    prefixq(src, dst);
  7.3096 -  emit_byte(0x3B);
  7.3097 +  emit_int8(0x3B);
  7.3098    emit_operand(dst, src);
  7.3099  }
  7.3100  
  7.3101  void Assembler::cmpxchgq(Register reg, Address adr) {
  7.3102    InstructionMark im(this);
  7.3103    prefixq(adr, reg);
  7.3104 -  emit_byte(0x0F);
  7.3105 -  emit_byte(0xB1);
  7.3106 +  emit_int8(0x0F);
  7.3107 +  emit_int8((unsigned char)0xB1);
  7.3108    emit_operand(reg, adr);
  7.3109  }
  7.3110  
  7.3111  void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
  7.3112    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.3113    int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
  7.3114 -  emit_byte(0x2A);
  7.3115 -  emit_byte(0xC0 | encode);
  7.3116 +  emit_int8(0x2A);
  7.3117 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3118  }
  7.3119  
  7.3120  void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
  7.3121    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.3122    InstructionMark im(this);
  7.3123    simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
  7.3124 -  emit_byte(0x2A);
  7.3125 +  emit_int8(0x2A);
  7.3126    emit_operand(dst, src);
  7.3127  }
  7.3128  
  7.3129  void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
  7.3130    NOT_LP64(assert(VM_Version::supports_sse(), ""));
  7.3131    int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
  7.3132 -  emit_byte(0x2A);
  7.3133 -  emit_byte(0xC0 | encode);
  7.3134 +  emit_int8(0x2A);
  7.3135 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3136  }
  7.3137  
  7.3138  void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
  7.3139    NOT_LP64(assert(VM_Version::supports_sse(), ""));
  7.3140    InstructionMark im(this);
  7.3141    simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
  7.3142 -  emit_byte(0x2A);
  7.3143 +  emit_int8(0x2A);
  7.3144    emit_operand(dst, src);
  7.3145  }
  7.3146  
  7.3147  void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
  7.3148    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.3149    int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
  7.3150 -  emit_byte(0x2C);
  7.3151 -  emit_byte(0xC0 | encode);
  7.3152 +  emit_int8(0x2C);
  7.3153 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3154  }
  7.3155  
  7.3156  void Assembler::cvttss2siq(Register dst, XMMRegister src) {
  7.3157    NOT_LP64(assert(VM_Version::supports_sse(), ""));
  7.3158    int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
  7.3159 -  emit_byte(0x2C);
  7.3160 -  emit_byte(0xC0 | encode);
  7.3161 +  emit_int8(0x2C);
  7.3162 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3163  }
  7.3164  
  7.3165  void Assembler::decl(Register dst) {
  7.3166    // Don't use it directly. Use MacroAssembler::decrementl() instead.
  7.3167    // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
  7.3168    int encode = prefix_and_encode(dst->encoding());
  7.3169 -  emit_byte(0xFF);
  7.3170 -  emit_byte(0xC8 | encode);
  7.3171 +  emit_int8((unsigned char)0xFF);
  7.3172 +  emit_int8((unsigned char)(0xC8 | encode));
  7.3173  }
  7.3174  
  7.3175  void Assembler::decq(Register dst) {
  7.3176    // Don't use it directly. Use MacroAssembler::decrementq() instead.
  7.3177    // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
  7.3178    int encode = prefixq_and_encode(dst->encoding());
  7.3179 -  emit_byte(0xFF);
  7.3180 -  emit_byte(0xC8 | encode);
  7.3181 +  emit_int8((unsigned char)0xFF);
  7.3182 +  emit_int8(0xC8 | encode);
  7.3183  }
  7.3184  
  7.3185  void Assembler::decq(Address dst) {
  7.3186    // Don't use it directly. Use MacroAssembler::decrementq() instead.
  7.3187    InstructionMark im(this);
  7.3188    prefixq(dst);
  7.3189 -  emit_byte(0xFF);
  7.3190 +  emit_int8((unsigned char)0xFF);
  7.3191    emit_operand(rcx, dst);
  7.3192  }
  7.3193  
  7.3194  void Assembler::fxrstor(Address src) {
  7.3195    prefixq(src);
  7.3196 -  emit_byte(0x0F);
  7.3197 -  emit_byte(0xAE);
  7.3198 +  emit_int8(0x0F);
  7.3199 +  emit_int8((unsigned char)0xAE);
  7.3200    emit_operand(as_Register(1), src);
  7.3201  }
  7.3202  
  7.3203  void Assembler::fxsave(Address dst) {
  7.3204    prefixq(dst);
  7.3205 -  emit_byte(0x0F);
  7.3206 -  emit_byte(0xAE);
  7.3207 +  emit_int8(0x0F);
  7.3208 +  emit_int8((unsigned char)0xAE);
  7.3209    emit_operand(as_Register(0), dst);
  7.3210  }
  7.3211  
  7.3212  void Assembler::idivq(Register src) {
  7.3213    int encode = prefixq_and_encode(src->encoding());
  7.3214 -  emit_byte(0xF7);
  7.3215 -  emit_byte(0xF8 | encode);
  7.3216 +  emit_int8((unsigned char)0xF7);
  7.3217 +  emit_int8((unsigned char)(0xF8 | encode));
  7.3218  }
  7.3219  
  7.3220  void Assembler::imulq(Register dst, Register src) {
  7.3221    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3222 -  emit_byte(0x0F);
  7.3223 -  emit_byte(0xAF);
  7.3224 -  emit_byte(0xC0 | encode);
  7.3225 +  emit_int8(0x0F);
  7.3226 +  emit_int8((unsigned char)0xAF);
  7.3227 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3228  }
  7.3229  
  7.3230  void Assembler::imulq(Register dst, Register src, int value) {
  7.3231    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3232    if (is8bit(value)) {
  7.3233 -    emit_byte(0x6B);
  7.3234 -    emit_byte(0xC0 | encode);
  7.3235 -    emit_byte(value & 0xFF);
  7.3236 +    emit_int8(0x6B);
  7.3237 +    emit_int8((unsigned char)(0xC0 | encode));
  7.3238 +    emit_int8(value & 0xFF);
  7.3239    } else {
  7.3240 -    emit_byte(0x69);
  7.3241 -    emit_byte(0xC0 | encode);
  7.3242 +    emit_int8(0x69);
  7.3243 +    emit_int8((unsigned char)(0xC0 | encode));
  7.3244      emit_long(value);
  7.3245    }
  7.3246  }
  7.3247 @@ -4934,23 +4940,23 @@
  7.3248    // Don't use it directly. Use MacroAssembler::incrementl() instead.
  7.3249    // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
  7.3250    int encode = prefix_and_encode(dst->encoding());
  7.3251 -  emit_byte(0xFF);
  7.3252 -  emit_byte(0xC0 | encode);
  7.3253 +  emit_int8((unsigned char)0xFF);
  7.3254 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3255  }
  7.3256  
  7.3257  void Assembler::incq(Register dst) {
  7.3258    // Don't use it directly. Use MacroAssembler::incrementq() instead.
  7.3259    // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
  7.3260    int encode = prefixq_and_encode(dst->encoding());
  7.3261 -  emit_byte(0xFF);
  7.3262 -  emit_byte(0xC0 | encode);
  7.3263 +  emit_int8((unsigned char)0xFF);
  7.3264 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3265  }
  7.3266  
  7.3267  void Assembler::incq(Address dst) {
  7.3268    // Don't use it directly. Use MacroAssembler::incrementq() instead.
  7.3269    InstructionMark im(this);
  7.3270    prefixq(dst);
  7.3271 -  emit_byte(0xFF);
  7.3272 +  emit_int8((unsigned char)0xFF);
  7.3273    emit_operand(rax, dst);
  7.3274  }
  7.3275  
  7.3276 @@ -4961,35 +4967,35 @@
  7.3277  void Assembler::leaq(Register dst, Address src) {
  7.3278    InstructionMark im(this);
  7.3279    prefixq(src, dst);
  7.3280 -  emit_byte(0x8D);
  7.3281 +  emit_int8((unsigned char)0x8D);
  7.3282    emit_operand(dst, src);
  7.3283  }
  7.3284  
  7.3285  void Assembler::mov64(Register dst, int64_t imm64) {
  7.3286    InstructionMark im(this);
  7.3287    int encode = prefixq_and_encode(dst->encoding());
  7.3288 -  emit_byte(0xB8 | encode);
  7.3289 +  emit_int8((unsigned char)(0xB8 | encode));
  7.3290    emit_int64(imm64);
  7.3291  }
  7.3292  
  7.3293  void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
  7.3294    InstructionMark im(this);
  7.3295    int encode = prefixq_and_encode(dst->encoding());
  7.3296 -  emit_byte(0xB8 | encode);
  7.3297 +  emit_int8(0xB8 | encode);
  7.3298    emit_data64(imm64, rspec);
  7.3299  }
  7.3300  
  7.3301  void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
  7.3302    InstructionMark im(this);
  7.3303    int encode = prefix_and_encode(dst->encoding());
  7.3304 -  emit_byte(0xB8 | encode);
  7.3305 +  emit_int8((unsigned char)(0xB8 | encode));
  7.3306    emit_data((int)imm32, rspec, narrow_oop_operand);
  7.3307  }
  7.3308  
  7.3309  void Assembler::mov_narrow_oop(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
  7.3310    InstructionMark im(this);
  7.3311    prefix(dst);
  7.3312 -  emit_byte(0xC7);
  7.3313 +  emit_int8((unsigned char)0xC7);
  7.3314    emit_operand(rax, dst, 4);
  7.3315    emit_data((int)imm32, rspec, narrow_oop_operand);
  7.3316  }
  7.3317 @@ -4997,34 +5003,34 @@
  7.3318  void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
  7.3319    InstructionMark im(this);
  7.3320    int encode = prefix_and_encode(src1->encoding());
  7.3321 -  emit_byte(0x81);
  7.3322 -  emit_byte(0xF8 | encode);
  7.3323 +  emit_int8((unsigned char)0x81);
  7.3324 +  emit_int8((unsigned char)(0xF8 | encode));
  7.3325    emit_data((int)imm32, rspec, narrow_oop_operand);
  7.3326  }
  7.3327  
  7.3328  void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
  7.3329    InstructionMark im(this);
  7.3330    prefix(src1);
  7.3331 -  emit_byte(0x81);
  7.3332 +  emit_int8((unsigned char)0x81);
  7.3333    emit_operand(rax, src1, 4);
  7.3334    emit_data((int)imm32, rspec, narrow_oop_operand);
  7.3335  }
  7.3336  
  7.3337  void Assembler::lzcntq(Register dst, Register src) {
  7.3338    assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
  7.3339 -  emit_byte(0xF3);
  7.3340 +  emit_int8((unsigned char)0xF3);
  7.3341    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3342 -  emit_byte(0x0F);
  7.3343 -  emit_byte(0xBD);
  7.3344 -  emit_byte(0xC0 | encode);
  7.3345 +  emit_int8(0x0F);
  7.3346 +  emit_int8((unsigned char)0xBD);
  7.3347 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3348  }
  7.3349  
  7.3350  void Assembler::movdq(XMMRegister dst, Register src) {
  7.3351    // table D-1 says MMX/SSE2
  7.3352    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.3353    int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
  7.3354 -  emit_byte(0x6E);
  7.3355 -  emit_byte(0xC0 | encode);
  7.3356 +  emit_int8(0x6E);
  7.3357 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3358  }
  7.3359  
  7.3360  void Assembler::movdq(Register dst, XMMRegister src) {
  7.3361 @@ -5032,43 +5038,43 @@
  7.3362    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
  7.3363    // swap src/dst to get correct prefix
  7.3364    int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
  7.3365 -  emit_byte(0x7E);
  7.3366 -  emit_byte(0xC0 | encode);
  7.3367 +  emit_int8(0x7E);
  7.3368 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3369  }
  7.3370  
  7.3371  void Assembler::movq(Register dst, Register src) {
  7.3372    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3373 -  emit_byte(0x8B);
  7.3374 -  emit_byte(0xC0 | encode);
  7.3375 +  emit_int8((unsigned char)0x8B);
  7.3376 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3377  }
  7.3378  
  7.3379  void Assembler::movq(Register dst, Address src) {
  7.3380    InstructionMark im(this);
  7.3381    prefixq(src, dst);
  7.3382 -  emit_byte(0x8B);
  7.3383 +  emit_int8((unsigned char)0x8B);
  7.3384    emit_operand(dst, src);
  7.3385  }
  7.3386  
  7.3387  void Assembler::movq(Address dst, Register src) {
  7.3388    InstructionMark im(this);
  7.3389    prefixq(dst, src);
  7.3390 -  emit_byte(0x89);
  7.3391 +  emit_int8((unsigned char)0x89);
  7.3392    emit_operand(src, dst);
  7.3393  }
  7.3394  
  7.3395  void Assembler::movsbq(Register dst, Address src) {
  7.3396    InstructionMark im(this);
  7.3397    prefixq(src, dst);
  7.3398 -  emit_byte(0x0F);
  7.3399 -  emit_byte(0xBE);
  7.3400 +  emit_int8(0x0F);
  7.3401 +  emit_int8((unsigned char)0xBE);
  7.3402    emit_operand(dst, src);
  7.3403  }
  7.3404  
  7.3405  void Assembler::movsbq(Register dst, Register src) {
  7.3406    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3407 -  emit_byte(0x0F);
  7.3408 -  emit_byte(0xBE);
  7.3409 -  emit_byte(0xC0 | encode);
  7.3410 +  emit_int8(0x0F);
  7.3411 +  emit_int8((unsigned char)0xBE);
  7.3412 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3413  }
  7.3414  
  7.3415  void Assembler::movslq(Register dst, int32_t imm32) {
  7.3416 @@ -5078,7 +5084,7 @@
  7.3417    ShouldNotReachHere();
  7.3418    InstructionMark im(this);
  7.3419    int encode = prefixq_and_encode(dst->encoding());
  7.3420 -  emit_byte(0xC7 | encode);
  7.3421 +  emit_int8((unsigned char)(0xC7 | encode));
  7.3422    emit_long(imm32);
  7.3423  }
  7.3424  
  7.3425 @@ -5086,7 +5092,7 @@
  7.3426    assert(is_simm32(imm32), "lost bits");
  7.3427    InstructionMark im(this);
  7.3428    prefixq(dst);
  7.3429 -  emit_byte(0xC7);
  7.3430 +  emit_int8((unsigned char)0xC7);
  7.3431    emit_operand(rax, dst, 4);
  7.3432    emit_long(imm32);
  7.3433  }
  7.3434 @@ -5094,77 +5100,77 @@
  7.3435  void Assembler::movslq(Register dst, Address src) {
  7.3436    InstructionMark im(this);
  7.3437    prefixq(src, dst);
  7.3438 -  emit_byte(0x63);
  7.3439 +  emit_int8(0x63);
  7.3440    emit_operand(dst, src);
  7.3441  }
  7.3442  
  7.3443  void Assembler::movslq(Register dst, Register src) {
  7.3444    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3445 -  emit_byte(0x63);
  7.3446 -  emit_byte(0xC0 | encode);
  7.3447 +  emit_int8(0x63);
  7.3448 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3449  }
  7.3450  
  7.3451  void Assembler::movswq(Register dst, Address src) {
  7.3452    InstructionMark im(this);
  7.3453    prefixq(src, dst);
  7.3454 -  emit_byte(0x0F);
  7.3455 -  emit_byte(0xBF);
  7.3456 +  emit_int8(0x0F);
  7.3457 +  emit_int8((unsigned char)0xBF);
  7.3458    emit_operand(dst, src);
  7.3459  }
  7.3460  
  7.3461  void Assembler::movswq(Register dst, Register src) {
  7.3462    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3463 -  emit_byte(0x0F);
  7.3464 -  emit_byte(0xBF);
  7.3465 -  emit_byte(0xC0 | encode);
  7.3466 +  emit_int8((unsigned char)0x0F);
  7.3467 +  emit_int8((unsigned char)0xBF);
  7.3468 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3469  }
  7.3470  
  7.3471  void Assembler::movzbq(Register dst, Address src) {
  7.3472    InstructionMark im(this);
  7.3473    prefixq(src, dst);
  7.3474 -  emit_byte(0x0F);
  7.3475 -  emit_byte(0xB6);
  7.3476 +  emit_int8((unsigned char)0x0F);
  7.3477 +  emit_int8((unsigned char)0xB6);
  7.3478    emit_operand(dst, src);
  7.3479  }
  7.3480  
  7.3481  void Assembler::movzbq(Register dst, Register src) {
  7.3482    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3483 -  emit_byte(0x0F);
  7.3484 -  emit_byte(0xB6);
  7.3485 -  emit_byte(0xC0 | encode);
  7.3486 +  emit_int8(0x0F);
  7.3487 +  emit_int8((unsigned char)0xB6);
  7.3488 +  emit_int8(0xC0 | encode);
  7.3489  }
  7.3490  
  7.3491  void Assembler::movzwq(Register dst, Address src) {
  7.3492    InstructionMark im(this);
  7.3493    prefixq(src, dst);
  7.3494 -  emit_byte(0x0F);
  7.3495 -  emit_byte(0xB7);
  7.3496 +  emit_int8((unsigned char)0x0F);
  7.3497 +  emit_int8((unsigned char)0xB7);
  7.3498    emit_operand(dst, src);
  7.3499  }
  7.3500  
  7.3501  void Assembler::movzwq(Register dst, Register src) {
  7.3502    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3503 -  emit_byte(0x0F);
  7.3504 -  emit_byte(0xB7);
  7.3505 -  emit_byte(0xC0 | encode);
  7.3506 +  emit_int8((unsigned char)0x0F);
  7.3507 +  emit_int8((unsigned char)0xB7);
  7.3508 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3509  }
  7.3510  
  7.3511  void Assembler::negq(Register dst) {
  7.3512    int encode = prefixq_and_encode(dst->encoding());
  7.3513 -  emit_byte(0xF7);
  7.3514 -  emit_byte(0xD8 | encode);
  7.3515 +  emit_int8((unsigned char)0xF7);
  7.3516 +  emit_int8((unsigned char)(0xD8 | encode));
  7.3517  }
  7.3518  
  7.3519  void Assembler::notq(Register dst) {
  7.3520    int encode = prefixq_and_encode(dst->encoding());
  7.3521 -  emit_byte(0xF7);
  7.3522 -  emit_byte(0xD0 | encode);
  7.3523 +  emit_int8((unsigned char)0xF7);
  7.3524 +  emit_int8((unsigned char)(0xD0 | encode));
  7.3525  }
  7.3526  
  7.3527  void Assembler::orq(Address dst, int32_t imm32) {
  7.3528    InstructionMark im(this);
  7.3529    prefixq(dst);
  7.3530 -  emit_byte(0x81);
  7.3531 +  emit_int8((unsigned char)0x81);
  7.3532    emit_operand(rcx, dst, 4);
  7.3533    emit_long(imm32);
  7.3534  }
  7.3535 @@ -5177,7 +5183,7 @@
  7.3536  void Assembler::orq(Register dst, Address src) {
  7.3537    InstructionMark im(this);
  7.3538    prefixq(src, dst);
  7.3539 -  emit_byte(0x0B);
  7.3540 +  emit_int8(0x0B);
  7.3541    emit_operand(dst, src);
  7.3542  }
  7.3543  
  7.3544 @@ -5210,26 +5216,26 @@
  7.3545  void Assembler::popcntq(Register dst, Address src) {
  7.3546    assert(VM_Version::supports_popcnt(), "must support");
  7.3547    InstructionMark im(this);
  7.3548 -  emit_byte(0xF3);
  7.3549 +  emit_int8((unsigned char)0xF3);
  7.3550    prefixq(src, dst);
  7.3551 -  emit_byte(0x0F);
  7.3552 -  emit_byte(0xB8);
  7.3553 +  emit_int8((unsigned char)0x0F);
  7.3554 +  emit_int8((unsigned char)0xB8);
  7.3555    emit_operand(dst, src);
  7.3556  }
  7.3557  
  7.3558  void Assembler::popcntq(Register dst, Register src) {
  7.3559    assert(VM_Version::supports_popcnt(), "must support");
  7.3560 -  emit_byte(0xF3);
  7.3561 +  emit_int8((unsigned char)0xF3);
  7.3562    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3563 -  emit_byte(0x0F);
  7.3564 -  emit_byte(0xB8);
  7.3565 -  emit_byte(0xC0 | encode);
  7.3566 +  emit_int8((unsigned char)0x0F);
  7.3567 +  emit_int8((unsigned char)0xB8);
  7.3568 +  emit_int8((unsigned char)(0xC0 | encode));
  7.3569  }
  7.3570  
  7.3571  void Assembler::popq(Address dst) {
  7.3572    InstructionMark im(this);
  7.3573    prefixq(dst);
  7.3574 -  emit_byte(0x8F);
  7.3575 +  emit_int8((unsigned char)0x8F);
  7.3576    emit_operand(rax, dst);
  7.3577  }
  7.3578  
  7.3579 @@ -5261,7 +5267,7 @@
  7.3580  void Assembler::pushq(Address src) {
  7.3581    InstructionMark im(this);
  7.3582    prefixq(src);
  7.3583 -  emit_byte(0xFF);
  7.3584 +  emit_int8((unsigned char)0xFF);
  7.3585    emit_operand(rsi, src);
  7.3586  }
  7.3587  
  7.3588 @@ -5269,31 +5275,31 @@
  7.3589    assert(isShiftCount(imm8 >> 1), "illegal shift count");
  7.3590    int encode = prefixq_and_encode(dst->encoding());
  7.3591    if (imm8 == 1) {
  7.3592 -    emit_byte(0xD1);
  7.3593 -    emit_byte(0xD0 | encode);
  7.3594 +    emit_int8((unsigned char)0xD1);
  7.3595 +    emit_int8((unsigned char)(0xD0 | encode));
  7.3596    } else {
  7.3597 -    emit_byte(0xC1);
  7.3598 -    emit_byte(0xD0 | encode);
  7.3599 -    emit_byte(imm8);
  7.3600 +    emit_int8((unsigned char)0xC1);
  7.3601 +    emit_int8((unsigned char)(0xD0 | encode));
  7.3602 +    emit_int8(imm8);
  7.3603    }
  7.3604  }
  7.3605  void Assembler::sarq(Register dst, int imm8) {
  7.3606    assert(isShiftCount(imm8 >> 1), "illegal shift count");
  7.3607    int encode = prefixq_and_encode(dst->encoding());
  7.3608    if (imm8 == 1) {
  7.3609 -    emit_byte(0xD1);
  7.3610 -    emit_byte(0xF8 | encode);
  7.3611 +    emit_int8((unsigned char)0xD1);
  7.3612 +    emit_int8((unsigned char)(0xF8 | encode));
  7.3613    } else {
  7.3614 -    emit_byte(0xC1);
  7.3615 -    emit_byte(0xF8 | encode);
  7.3616 -    emit_byte(imm8);
  7.3617 +    emit_int8((unsigned char)0xC1);
  7.3618 +    emit_int8((unsigned char)(0xF8 | encode));
  7.3619 +    emit_int8(imm8);
  7.3620    }
  7.3621  }
  7.3622  
  7.3623  void Assembler::sarq(Register dst) {
  7.3624    int encode = prefixq_and_encode(dst->encoding());
  7.3625 -  emit_byte(0xD3);
  7.3626 -  emit_byte(0xF8 | encode);
  7.3627 +  emit_int8((unsigned char)0xD3);
  7.3628 +  emit_int8((unsigned char)(0xF8 | encode));
  7.3629  }
  7.3630  
  7.3631  void Assembler::sbbq(Address dst, int32_t imm32) {
  7.3632 @@ -5310,7 +5316,7 @@
  7.3633  void Assembler::sbbq(Register dst, Address src) {
  7.3634    InstructionMark im(this);
  7.3635    prefixq(src, dst);
  7.3636 -  emit_byte(0x1B);
  7.3637 +  emit_int8(0x1B);
  7.3638    emit_operand(dst, src);
  7.3639  }
  7.3640  
  7.3641 @@ -5323,33 +5329,33 @@
  7.3642    assert(isShiftCount(imm8 >> 1), "illegal shift count");
  7.3643    int encode = prefixq_and_encode(dst->encoding());
  7.3644    if (imm8 == 1) {
  7.3645 -    emit_byte(0xD1);
  7.3646 -    emit_byte(0xE0 | encode);
  7.3647 +    emit_int8((unsigned char)0xD1);
  7.3648 +    emit_int8((unsigned char)(0xE0 | encode));
  7.3649    } else {
  7.3650 -    emit_byte(0xC1);
  7.3651 -    emit_byte(0xE0 | encode);
  7.3652 -    emit_byte(imm8);
  7.3653 +    emit_int8((unsigned char)0xC1);
  7.3654 +    emit_int8((unsigned char)(0xE0 | encode));
  7.3655 +    emit_int8(imm8);
  7.3656    }
  7.3657  }
  7.3658  
  7.3659  void Assembler::shlq(Register dst) {
  7.3660    int encode = prefixq_and_encode(dst->encoding());
  7.3661 -  emit_byte(0xD3);
  7.3662 -  emit_byte(0xE0 | encode);
  7.3663 +  emit_int8((unsigned char)0xD3);
  7.3664 +  emit_int8((unsigned char)(0xE0 | encode));
  7.3665  }
  7.3666  
  7.3667  void Assembler::shrq(Register dst, int imm8) {
  7.3668    assert(isShiftCount(imm8 >> 1), "illegal shift count");
  7.3669    int encode = prefixq_and_encode(dst->encoding());
  7.3670 -  emit_byte(0xC1);
  7.3671 -  emit_byte(0xE8 | encode);
  7.3672 -  emit_byte(imm8);
  7.3673 +  emit_int8((unsigned char)0xC1);
  7.3674 +  emit_int8((unsigned char)(0xE8 | encode));
  7.3675 +  emit_int8(imm8);
  7.3676  }
  7.3677  
  7.3678  void Assembler::shrq(Register dst) {
  7.3679    int encode = prefixq_and_encode(dst->encoding());
  7.3680 -  emit_byte(0xD3);
  7.3681 -  emit_byte(0xE8 | encode);
  7.3682 +  emit_int8((unsigned char)0xD3);
  7.3683 +  emit_int8(0xE8 | encode);
  7.3684  }
  7.3685  
  7.3686  void Assembler::subq(Address dst, int32_t imm32) {
  7.3687 @@ -5361,7 +5367,7 @@
  7.3688  void Assembler::subq(Address dst, Register src) {
  7.3689    InstructionMark im(this);
  7.3690    prefixq(dst, src);
  7.3691 -  emit_byte(0x29);
  7.3692 +  emit_int8(0x29);
  7.3693    emit_operand(src, dst);
  7.3694  }
  7.3695  
  7.3696 @@ -5379,7 +5385,7 @@
  7.3697  void Assembler::subq(Register dst, Address src) {
  7.3698    InstructionMark im(this);
  7.3699    prefixq(src, dst);
  7.3700 -  emit_byte(0x2B);
  7.3701 +  emit_int8(0x2B);
  7.3702    emit_operand(dst, src);
  7.3703  }
  7.3704  
  7.3705 @@ -5395,11 +5401,11 @@
  7.3706    int encode = dst->encoding();
  7.3707    if (encode == 0) {
  7.3708      prefix(REX_W);
  7.3709 -    emit_byte(0xA9);
  7.3710 +    emit_int8((unsigned char)0xA9);
  7.3711    } else {
  7.3712      encode = prefixq_and_encode(encode);
  7.3713 -    emit_byte(0xF7);
  7.3714 -    emit_byte(0xC0 | encode);
  7.3715 +    emit_int8((unsigned char)0xF7);
  7.3716 +    emit_int8((unsigned char)(0xC0 | encode));
  7.3717    }
  7.3718    emit_long(imm32);
  7.3719  }
  7.3720 @@ -5412,22 +5418,22 @@
  7.3721  void Assembler::xaddq(Address dst, Register src) {
  7.3722    InstructionMark im(this);
  7.3723    prefixq(dst, src);
  7.3724 -  emit_byte(0x0F);
  7.3725 -  emit_byte(0xC1);
  7.3726 +  emit_int8(0x0F);
  7.3727 +  emit_int8((unsigned char)0xC1);
  7.3728    emit_operand(src, dst);
  7.3729  }
  7.3730  
  7.3731  void Assembler::xchgq(Register dst, Address src) {
  7.3732    InstructionMark im(this);
  7.3733    prefixq(src, dst);
  7.3734 -  emit_byte(0x87);
  7.3735 +  emit_int8((unsigned char)0x87);
  7.3736    emit_operand(dst, src);
  7.3737  }
  7.3738  
  7.3739  void Assembler::xchgq(Register dst, Register src) {
  7.3740    int encode = prefixq_and_encode(dst->encoding(), src->encoding());
  7.3741 -  emit_byte(0x87);
  7.3742 -  emit_byte(0xc0 | encode);
  7.3743 +  emit_int8((unsigned char)0x87);
  7.3744 +  emit_int8((unsigned char)(0xc0 | encode));
  7.3745  }
  7.3746  
  7.3747  void Assembler::xorq(Register dst, Register src) {
  7.3748 @@ -5438,7 +5444,7 @@
  7.3749  void Assembler::xorq(Register dst, Address src) {
  7.3750    InstructionMark im(this);
  7.3751    prefixq(src, dst);
  7.3752 -  emit_byte(0x33);
  7.3753 +  emit_int8(0x33);
  7.3754    emit_operand(dst, src);
  7.3755  }
  7.3756

     8.1 --- a/src/cpu/x86/vm/c1_CodeStubs_x86.cpp	Wed Dec 19 16:10:19 2012 -0800
     8.2 +++ b/src/cpu/x86/vm/c1_CodeStubs_x86.cpp	Fri Dec 21 01:39:34 2012 -0800
     8.3 @@ -313,10 +313,10 @@
     8.4  #endif
     8.5    } else {
     8.6      // make a copy the code which is going to be patched.
     8.7 -    for ( int i = 0; i < _bytes_to_copy; i++) {
     8.8 +    for (int i = 0; i < _bytes_to_copy; i++) {
     8.9        address ptr = (address)(_pc_start + i);
    8.10        int a_byte = (*ptr) & 0xFF;
    8.11 -      __ a_byte (a_byte);
    8.12 +      __ emit_int8(a_byte);
    8.13        *ptr = 0x90; // make the site look like a nop
    8.14      }
    8.15    }
    8.16 @@ -363,11 +363,11 @@
    8.17    // emit the offsets needed to find the code to patch
    8.18    int being_initialized_entry_offset = __ pc() - being_initialized_entry + sizeof_patch_record;
    8.19  
    8.20 -  __ a_byte(0xB8);
    8.21 -  __ a_byte(0);
    8.22 -  __ a_byte(being_initialized_entry_offset);
    8.23 -  __ a_byte(bytes_to_skip);
    8.24 -  __ a_byte(_bytes_to_copy);
    8.25 +  __ emit_int8((unsigned char)0xB8);
    8.26 +  __ emit_int8(0);
    8.27 +  __ emit_int8(being_initialized_entry_offset);
    8.28 +  __ emit_int8(bytes_to_skip);
    8.29 +  __ emit_int8(_bytes_to_copy);
    8.30    address patch_info_pc = __ pc();
    8.31    assert(patch_info_pc - end_of_patch == bytes_to_skip, "incorrect patch info");
    8.32

     9.1 --- a/src/cpu/x86/vm/macroAssembler_x86.cpp	Wed Dec 19 16:10:19 2012 -0800
     9.2 +++ b/src/cpu/x86/vm/macroAssembler_x86.cpp	Fri Dec 21 01:39:34 2012 -0800
     9.3 @@ -1023,7 +1023,7 @@
     9.4  
     9.5  void MacroAssembler::leave() {
     9.6    // %%% is this really better? Why not on 32bit too?
     9.7 -  emit_byte(0xC9); // LEAVE
     9.8 +  emit_int8((unsigned char)0xC9); // LEAVE
     9.9  }
    9.10  
    9.11  void MacroAssembler::lneg(Register hi, Register lo) {
    9.12 @@ -2112,11 +2112,11 @@
    9.13    if (UseAddressNop) {
    9.14      addr_nop_5();
    9.15    } else {
    9.16 -    emit_byte(0x26); // es:
    9.17 -    emit_byte(0x2e); // cs:
    9.18 -    emit_byte(0x64); // fs:
    9.19 -    emit_byte(0x65); // gs:
    9.20 -    emit_byte(0x90);
    9.21 +    emit_int8(0x26); // es:
    9.22 +    emit_int8(0x2e); // cs:
    9.23 +    emit_int8(0x64); // fs:
    9.24 +    emit_int8(0x65); // gs:
    9.25 +    emit_int8((unsigned char)0x90);
    9.26    }
    9.27  }
    9.28  
    9.29 @@ -2534,12 +2534,12 @@
    9.30      int offs = (intptr_t)dst.target() - ((intptr_t)pc());
    9.31      if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
    9.32        // 0111 tttn #8-bit disp
    9.33 -      emit_byte(0x70 | cc);
    9.34 -      emit_byte((offs - short_size) & 0xFF);
    9.35 +      emit_int8(0x70 | cc);
    9.36 +      emit_int8((offs - short_size) & 0xFF);
    9.37      } else {
    9.38        // 0000 1111 1000 tttn #32-bit disp
    9.39 -      emit_byte(0x0F);
    9.40 -      emit_byte(0x80 | cc);
    9.41 +      emit_int8(0x0F);
    9.42 +      emit_int8((unsigned char)(0x80 | cc));
    9.43        emit_long(offs - long_size);
    9.44      }
    9.45    } else {
    9.46 @@ -3085,7 +3085,8 @@
    9.47  
    9.48  void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
    9.49    // Used in sign-bit flipping with aligned address.
    9.50 -  assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
    9.51 +  bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
    9.52 +  assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
    9.53    if (reachable(src)) {
    9.54      Assembler::pshufb(dst, as_Address(src));
    9.55    } else {

    10.1 --- a/src/cpu/x86/vm/macroAssembler_x86.hpp	Wed Dec 19 16:10:19 2012 -0800
    10.2 +++ b/src/cpu/x86/vm/macroAssembler_x86.hpp	Fri Dec 21 01:39:34 2012 -0800
    10.3 @@ -126,25 +126,6 @@
    10.4      }
    10.5    }
    10.6  
    10.7 -#ifndef PRODUCT
    10.8 -  static void pd_print_patched_instruction(address branch) {
    10.9 -    const char* s;
   10.10 -    unsigned char op = branch[0];
   10.11 -    if (op == 0xE8) {
   10.12 -      s = "call";
   10.13 -    } else if (op == 0xE9 || op == 0xEB) {
   10.14 -      s = "jmp";
   10.15 -    } else if ((op & 0xF0) == 0x70) {
   10.16 -      s = "jcc";
   10.17 -    } else if (op == 0x0F) {
   10.18 -      s = "jcc";
   10.19 -    } else {
   10.20 -      s = "????";
   10.21 -    }
   10.22 -    tty->print("%s (unresolved)", s);
   10.23 -  }
   10.24 -#endif
   10.25 -
   10.26    // The following 4 methods return the offset of the appropriate move instruction
   10.27  
   10.28    // Support for fast byte/short loading with zero extension (depending on particular CPU)

    11.1 --- a/src/cpu/x86/vm/stubGenerator_x86_32.cpp	Wed Dec 19 16:10:19 2012 -0800
    11.2 +++ b/src/cpu/x86/vm/stubGenerator_x86_32.cpp	Fri Dec 21 01:39:34 2012 -0800
    11.3 @@ -2174,13 +2174,13 @@
    11.4    //   c_rarg2   - K (key) in little endian int array
    11.5    //
    11.6    address generate_aescrypt_encryptBlock() {
    11.7 -    assert(UseAES && (UseAVX > 0), "need AES instructions and misaligned SSE support");
    11.8 +    assert(UseAES, "need AES instructions and misaligned SSE support");
    11.9      __ align(CodeEntryAlignment);
   11.10      StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock");
   11.11      Label L_doLast;
   11.12      address start = __ pc();
   11.13  
   11.14 -    const Register from        = rsi;      // source array address
   11.15 +    const Register from        = rdx;      // source array address
   11.16      const Register to          = rdx;      // destination array address
   11.17      const Register key         = rcx;      // key array address
   11.18      const Register keylen      = rax;
   11.19 @@ -2189,47 +2189,74 @@
   11.20      const Address  key_param (rbp, 8+8);
   11.21  
   11.22      const XMMRegister xmm_result = xmm0;
   11.23 -    const XMMRegister xmm_temp   = xmm1;
   11.24 -    const XMMRegister xmm_key_shuf_mask = xmm2;
   11.25 -
   11.26 -    __ enter(); // required for proper stackwalking of RuntimeStub frame
   11.27 -    __ push(rsi);
   11.28 -    __ movptr(from , from_param);
   11.29 -    __ movptr(to   , to_param);
   11.30 -    __ movptr(key  , key_param);
   11.31 -
   11.32 +    const XMMRegister xmm_key_shuf_mask = xmm1;
   11.33 +    const XMMRegister xmm_temp1  = xmm2;
   11.34 +    const XMMRegister xmm_temp2  = xmm3;
   11.35 +    const XMMRegister xmm_temp3  = xmm4;
   11.36 +    const XMMRegister xmm_temp4  = xmm5;
   11.37 +
   11.38 +    __ enter();   // required for proper stackwalking of RuntimeStub frame
   11.39 +    __ movptr(from, from_param);
   11.40 +    __ movptr(key, key_param);
   11.41 +
   11.42 +    // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
   11.43      __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
   11.44 -    // keylen = # of 32-bit words, convert to 128-bit words
   11.45 -    __ shrl(keylen, 2);
   11.46 -    __ subl(keylen, 11);   // every key has at least 11 128-bit words, some have more
   11.47  
   11.48      __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
   11.49      __ movdqu(xmm_result, Address(from, 0));  // get 16 bytes of input
   11.50 +    __ movptr(to, to_param);
   11.51  
   11.52      // For encryption, the java expanded key ordering is just what we need
   11.53  
   11.54 -    load_key(xmm_temp, key, 0x00, xmm_key_shuf_mask);
   11.55 -    __ pxor(xmm_result, xmm_temp);
   11.56 -    for (int offset = 0x10; offset <= 0x90; offset += 0x10) {
   11.57 -      aes_enc_key(xmm_result, xmm_temp, key, offset, xmm_key_shuf_mask);
   11.58 -    }
   11.59 -    load_key  (xmm_temp, key, 0xa0, xmm_key_shuf_mask);
   11.60 -    __ cmpl(keylen, 0);
   11.61 -    __ jcc(Assembler::equal, L_doLast);
   11.62 -    __ aesenc(xmm_result, xmm_temp);                   // only in 192 and 256 bit keys
   11.63 -    aes_enc_key(xmm_result, xmm_temp, key, 0xb0, xmm_key_shuf_mask);
   11.64 -    load_key(xmm_temp, key, 0xc0, xmm_key_shuf_mask);
   11.65 -    __ subl(keylen, 2);
   11.66 -    __ jcc(Assembler::equal, L_doLast);
   11.67 -    __ aesenc(xmm_result, xmm_temp);                   // only in 256 bit keys
   11.68 -    aes_enc_key(xmm_result, xmm_temp, key, 0xd0, xmm_key_shuf_mask);
   11.69 -    load_key(xmm_temp, key, 0xe0, xmm_key_shuf_mask);
   11.70 +    load_key(xmm_temp1, key, 0x00, xmm_key_shuf_mask);
   11.71 +    __ pxor(xmm_result, xmm_temp1);
   11.72 +
   11.73 +    load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
   11.74 +    load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
   11.75 +    load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
   11.76 +    load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
   11.77 +
   11.78 +    __ aesenc(xmm_result, xmm_temp1);
   11.79 +    __ aesenc(xmm_result, xmm_temp2);
   11.80 +    __ aesenc(xmm_result, xmm_temp3);
   11.81 +    __ aesenc(xmm_result, xmm_temp4);
   11.82 +
   11.83 +    load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
   11.84 +    load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
   11.85 +    load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
   11.86 +    load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
   11.87 +
   11.88 +    __ aesenc(xmm_result, xmm_temp1);
   11.89 +    __ aesenc(xmm_result, xmm_temp2);
   11.90 +    __ aesenc(xmm_result, xmm_temp3);
   11.91 +    __ aesenc(xmm_result, xmm_temp4);
   11.92 +
   11.93 +    load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
   11.94 +    load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
   11.95 +
   11.96 +    __ cmpl(keylen, 44);
   11.97 +    __ jccb(Assembler::equal, L_doLast);
   11.98 +
   11.99 +    __ aesenc(xmm_result, xmm_temp1);
  11.100 +    __ aesenc(xmm_result, xmm_temp2);
  11.101 +
  11.102 +    load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
  11.103 +    load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
  11.104 +
  11.105 +    __ cmpl(keylen, 52);
  11.106 +    __ jccb(Assembler::equal, L_doLast);
  11.107 +
  11.108 +    __ aesenc(xmm_result, xmm_temp1);
  11.109 +    __ aesenc(xmm_result, xmm_temp2);
  11.110 +
  11.111 +    load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
  11.112 +    load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
  11.113  
  11.114      __ BIND(L_doLast);
  11.115 -    __ aesenclast(xmm_result, xmm_temp);
  11.116 +    __ aesenc(xmm_result, xmm_temp1);
  11.117 +    __ aesenclast(xmm_result, xmm_temp2);
  11.118      __ movdqu(Address(to, 0), xmm_result);        // store the result
  11.119      __ xorptr(rax, rax); // return 0
  11.120 -    __ pop(rsi);
  11.121      __ leave(); // required for proper stackwalking of RuntimeStub frame
  11.122      __ ret(0);
  11.123  
  11.124 @@ -2245,13 +2272,13 @@
  11.125    //   c_rarg2   - K (key) in little endian int array
  11.126    //
  11.127    address generate_aescrypt_decryptBlock() {
  11.128 -    assert(UseAES && (UseAVX > 0), "need AES instructions and misaligned SSE support");
  11.129 +    assert(UseAES, "need AES instructions and misaligned SSE support");
  11.130      __ align(CodeEntryAlignment);
  11.131      StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock");
  11.132      Label L_doLast;
  11.133      address start = __ pc();
  11.134  
  11.135 -    const Register from        = rsi;      // source array address
  11.136 +    const Register from        = rdx;      // source array address
  11.137      const Register to          = rdx;      // destination array address
  11.138      const Register key         = rcx;      // key array address
  11.139      const Register keylen      = rax;
  11.140 @@ -2260,51 +2287,76 @@
  11.141      const Address  key_param (rbp, 8+8);
  11.142  
  11.143      const XMMRegister xmm_result = xmm0;
  11.144 -    const XMMRegister xmm_temp   = xmm1;
  11.145 -    const XMMRegister xmm_key_shuf_mask = xmm2;
  11.146 +    const XMMRegister xmm_key_shuf_mask = xmm1;
  11.147 +    const XMMRegister xmm_temp1  = xmm2;
  11.148 +    const XMMRegister xmm_temp2  = xmm3;
  11.149 +    const XMMRegister xmm_temp3  = xmm4;
  11.150 +    const XMMRegister xmm_temp4  = xmm5;
  11.151  
  11.152      __ enter(); // required for proper stackwalking of RuntimeStub frame
  11.153 -    __ push(rsi);
  11.154 -    __ movptr(from , from_param);
  11.155 -    __ movptr(to   , to_param);
  11.156 -    __ movptr(key  , key_param);
  11.157 -
  11.158 +    __ movptr(from, from_param);
  11.159 +    __ movptr(key, key_param);
  11.160 +
  11.161 +    // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
  11.162      __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
  11.163 -    // keylen = # of 32-bit words, convert to 128-bit words
  11.164 -    __ shrl(keylen, 2);
  11.165 -    __ subl(keylen, 11);   // every key has at least 11 128-bit words, some have more
  11.166  
  11.167      __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
  11.168      __ movdqu(xmm_result, Address(from, 0));
  11.169 +    __ movptr(to, to_param);
  11.170  
  11.171      // for decryption java expanded key ordering is rotated one position from what we want
  11.172      // so we start from 0x10 here and hit 0x00 last
  11.173      // we don't know if the key is aligned, hence not using load-execute form
  11.174 -    load_key(xmm_temp, key, 0x10, xmm_key_shuf_mask);
  11.175 -    __ pxor  (xmm_result, xmm_temp);
  11.176 -    for (int offset = 0x20; offset <= 0xa0; offset += 0x10) {
  11.177 -      aes_dec_key(xmm_result, xmm_temp, key, offset, xmm_key_shuf_mask);
  11.178 -    }
  11.179 -    __ cmpl(keylen, 0);
  11.180 -    __ jcc(Assembler::equal, L_doLast);
  11.181 -    // only in 192 and 256 bit keys
  11.182 -    aes_dec_key(xmm_result, xmm_temp, key, 0xb0, xmm_key_shuf_mask);
  11.183 -    aes_dec_key(xmm_result, xmm_temp, key, 0xc0, xmm_key_shuf_mask);
  11.184 -    __ subl(keylen, 2);
  11.185 -    __ jcc(Assembler::equal, L_doLast);
  11.186 -    // only in 256 bit keys
  11.187 -    aes_dec_key(xmm_result, xmm_temp, key, 0xd0, xmm_key_shuf_mask);
  11.188 -    aes_dec_key(xmm_result, xmm_temp, key, 0xe0, xmm_key_shuf_mask);
  11.189 +    load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
  11.190 +    load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
  11.191 +    load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
  11.192 +    load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
  11.193 +
  11.194 +    __ pxor  (xmm_result, xmm_temp1);
  11.195 +    __ aesdec(xmm_result, xmm_temp2);
  11.196 +    __ aesdec(xmm_result, xmm_temp3);
  11.197 +    __ aesdec(xmm_result, xmm_temp4);
  11.198 +
  11.199 +    load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
  11.200 +    load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
  11.201 +    load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
  11.202 +    load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
  11.203 +
  11.204 +    __ aesdec(xmm_result, xmm_temp1);
  11.205 +    __ aesdec(xmm_result, xmm_temp2);
  11.206 +    __ aesdec(xmm_result, xmm_temp3);
  11.207 +    __ aesdec(xmm_result, xmm_temp4);
  11.208 +
  11.209 +    load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
  11.210 +    load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
  11.211 +    load_key(xmm_temp3, key, 0x00, xmm_key_shuf_mask);
  11.212 +
  11.213 +    __ cmpl(keylen, 44);
  11.214 +    __ jccb(Assembler::equal, L_doLast);
  11.215 +
  11.216 +    __ aesdec(xmm_result, xmm_temp1);
  11.217 +    __ aesdec(xmm_result, xmm_temp2);
  11.218 +
  11.219 +    load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
  11.220 +    load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
  11.221 +
  11.222 +    __ cmpl(keylen, 52);
  11.223 +    __ jccb(Assembler::equal, L_doLast);
  11.224 +
  11.225 +    __ aesdec(xmm_result, xmm_temp1);
  11.226 +    __ aesdec(xmm_result, xmm_temp2);
  11.227 +
  11.228 +    load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
  11.229 +    load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
  11.230  
  11.231      __ BIND(L_doLast);
  11.232 +    __ aesdec(xmm_result, xmm_temp1);
  11.233 +    __ aesdec(xmm_result, xmm_temp2);
  11.234 +
  11.235      // for decryption the aesdeclast operation is always on key+0x00
  11.236 -    load_key(xmm_temp, key, 0x00, xmm_key_shuf_mask);
  11.237 -    __ aesdeclast(xmm_result, xmm_temp);
  11.238 -
  11.239 +    __ aesdeclast(xmm_result, xmm_temp3);
  11.240      __ movdqu(Address(to, 0), xmm_result);  // store the result
  11.241 -
  11.242      __ xorptr(rax, rax); // return 0
  11.243 -    __ pop(rsi);
  11.244      __ leave(); // required for proper stackwalking of RuntimeStub frame
  11.245      __ ret(0);
  11.246  
  11.247 @@ -2340,7 +2392,7 @@
  11.248    //   c_rarg4   - input length
  11.249    //
  11.250    address generate_cipherBlockChaining_encryptAESCrypt() {
  11.251 -    assert(UseAES && (UseAVX > 0), "need AES instructions and misaligned SSE support");
  11.252 +    assert(UseAES, "need AES instructions and misaligned SSE support");
  11.253      __ align(CodeEntryAlignment);
  11.254      StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt");
  11.255      address start = __ pc();
  11.256 @@ -2393,7 +2445,7 @@
  11.257      __ jcc(Assembler::notEqual, L_key_192_256);
  11.258  
  11.259      // 128 bit code follows here
  11.260 -    __ movptr(pos, 0);
  11.261 +    __ movl(pos, 0);
  11.262      __ align(OptoLoopAlignment);
  11.263      __ BIND(L_loopTop_128);
  11.264      __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
  11.265 @@ -2423,15 +2475,15 @@
  11.266      __ leave();                                  // required for proper stackwalking of RuntimeStub frame
  11.267      __ ret(0);
  11.268  
  11.269 -  __ BIND(L_key_192_256);
  11.270 -  // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
  11.271 +    __ BIND(L_key_192_256);
  11.272 +    // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
  11.273      __ cmpl(rax, 52);
  11.274      __ jcc(Assembler::notEqual, L_key_256);
  11.275  
  11.276      // 192-bit code follows here (could be changed to use more xmm registers)
  11.277 -    __ movptr(pos, 0);
  11.278 -  __ align(OptoLoopAlignment);
  11.279 -  __ BIND(L_loopTop_192);
  11.280 +    __ movl(pos, 0);
  11.281 +    __ align(OptoLoopAlignment);
  11.282 +    __ BIND(L_loopTop_192);
  11.283      __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
  11.284      __ pxor  (xmm_result, xmm_temp);                                // xor with the current r vector
  11.285  
  11.286 @@ -2452,11 +2504,11 @@
  11.287      __ jcc(Assembler::notEqual, L_loopTop_192);
  11.288      __ jmp(L_exit);
  11.289  
  11.290 -  __ BIND(L_key_256);
  11.291 +    __ BIND(L_key_256);
  11.292      // 256-bit code follows here (could be changed to use more xmm registers)
  11.293 -    __ movptr(pos, 0);
  11.294 -  __ align(OptoLoopAlignment);
  11.295 -  __ BIND(L_loopTop_256);
  11.296 +    __ movl(pos, 0);
  11.297 +    __ align(OptoLoopAlignment);
  11.298 +    __ BIND(L_loopTop_256);
  11.299      __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
  11.300      __ pxor  (xmm_result, xmm_temp);                                // xor with the current r vector
  11.301  
  11.302 @@ -2495,7 +2547,7 @@
  11.303    //
  11.304  
  11.305    address generate_cipherBlockChaining_decryptAESCrypt() {
  11.306 -    assert(UseAES && (UseAVX > 0), "need AES instructions and misaligned SSE support");
  11.307 +    assert(UseAES, "need AES instructions and misaligned SSE support");
  11.308      __ align(CodeEntryAlignment);
  11.309      StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt");
  11.310      address start = __ pc();
  11.311 @@ -2556,9 +2608,9 @@
  11.312  
  11.313  
  11.314      // 128-bit code follows here, parallelized
  11.315 -    __ movptr(pos, 0);
  11.316 -  __ align(OptoLoopAlignment);
  11.317 -  __ BIND(L_singleBlock_loopTop_128);
  11.318 +    __ movl(pos, 0);
  11.319 +    __ align(OptoLoopAlignment);
  11.320 +    __ BIND(L_singleBlock_loopTop_128);
  11.321      __ cmpptr(len_reg, 0);           // any blocks left??
  11.322      __ jcc(Assembler::equal, L_exit);
  11.323      __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of cipher input
  11.324 @@ -2597,7 +2649,7 @@
  11.325      __ jcc(Assembler::notEqual, L_key_256);
  11.326  
  11.327      // 192-bit code follows here (could be optimized to use parallelism)
  11.328 -    __ movptr(pos, 0);
  11.329 +    __ movl(pos, 0);
  11.330      __ align(OptoLoopAlignment);
  11.331      __ BIND(L_singleBlock_loopTop_192);
  11.332      __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of cipher input
  11.333 @@ -2622,7 +2674,7 @@
  11.334  
  11.335      __ BIND(L_key_256);
  11.336      // 256-bit code follows here (could be optimized to use parallelism)
  11.337 -    __ movptr(pos, 0);
  11.338 +    __ movl(pos, 0);
  11.339      __ align(OptoLoopAlignment);
  11.340      __ BIND(L_singleBlock_loopTop_256);
  11.341      __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of cipher input

    12.1 --- a/src/cpu/x86/vm/stubGenerator_x86_64.cpp	Wed Dec 19 16:10:19 2012 -0800
    12.2 +++ b/src/cpu/x86/vm/stubGenerator_x86_64.cpp	Fri Dec 21 01:39:34 2012 -0800
    12.3 @@ -2953,21 +2953,6 @@
    12.4      }
    12.5    }
    12.6  
    12.7 -  // aesenc using specified key+offset
    12.8 -  // can optionally specify that the shuffle mask is already in an xmmregister
    12.9 -  void aes_enc_key(XMMRegister xmmdst, XMMRegister xmmtmp, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
   12.10 -    load_key(xmmtmp, key, offset, xmm_shuf_mask);
   12.11 -    __ aesenc(xmmdst, xmmtmp);
   12.12 -  }
   12.13 -
   12.14 -  // aesdec using specified key+offset
   12.15 -  // can optionally specify that the shuffle mask is already in an xmmregister
   12.16 -  void aes_dec_key(XMMRegister xmmdst, XMMRegister xmmtmp, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
   12.17 -    load_key(xmmtmp, key, offset, xmm_shuf_mask);
   12.18 -    __ aesdec(xmmdst, xmmtmp);
   12.19 -  }
   12.20 -
   12.21 -
   12.22    // Arguments:
   12.23    //
   12.24    // Inputs:
   12.25 @@ -2976,7 +2961,7 @@
   12.26    //   c_rarg2   - K (key) in little endian int array
   12.27    //
   12.28    address generate_aescrypt_encryptBlock() {
   12.29 -    assert(UseAES && (UseAVX > 0), "need AES instructions and misaligned SSE support");
   12.30 +    assert(UseAES, "need AES instructions and misaligned SSE support");
   12.31      __ align(CodeEntryAlignment);
   12.32      StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock");
   12.33      Label L_doLast;
   12.34 @@ -2988,15 +2973,17 @@
   12.35      const Register keylen      = rax;
   12.36  
   12.37      const XMMRegister xmm_result = xmm0;
   12.38 -    const XMMRegister xmm_temp   = xmm1;
   12.39 -    const XMMRegister xmm_key_shuf_mask = xmm2;
   12.40 +    const XMMRegister xmm_key_shuf_mask = xmm1;
   12.41 +    // On win64 xmm6-xmm15 must be preserved so don't use them.
   12.42 +    const XMMRegister xmm_temp1  = xmm2;
   12.43 +    const XMMRegister xmm_temp2  = xmm3;
   12.44 +    const XMMRegister xmm_temp3  = xmm4;
   12.45 +    const XMMRegister xmm_temp4  = xmm5;
   12.46  
   12.47      __ enter(); // required for proper stackwalking of RuntimeStub frame
   12.48  
   12.49 +    // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
   12.50      __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
   12.51 -    // keylen = # of 32-bit words, convert to 128-bit words
   12.52 -    __ shrl(keylen, 2);
   12.53 -    __ subl(keylen, 11);   // every key has at least 11 128-bit words, some have more
   12.54  
   12.55      __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
   12.56      __ movdqu(xmm_result, Address(from, 0));  // get 16 bytes of input
   12.57 @@ -3004,25 +2991,53 @@
   12.58      // For encryption, the java expanded key ordering is just what we need
   12.59      // we don't know if the key is aligned, hence not using load-execute form
   12.60  
   12.61 -    load_key(xmm_temp, key, 0x00, xmm_key_shuf_mask);
   12.62 -    __ pxor(xmm_result, xmm_temp);
   12.63 -    for (int offset = 0x10; offset <= 0x90; offset += 0x10) {
   12.64 -      aes_enc_key(xmm_result, xmm_temp, key, offset, xmm_key_shuf_mask);
   12.65 -    }
   12.66 -    load_key  (xmm_temp, key, 0xa0, xmm_key_shuf_mask);
   12.67 -    __ cmpl(keylen, 0);
   12.68 -    __ jcc(Assembler::equal, L_doLast);
   12.69 -    __ aesenc(xmm_result, xmm_temp);                   // only in 192 and 256 bit keys
   12.70 -    aes_enc_key(xmm_result, xmm_temp, key, 0xb0, xmm_key_shuf_mask);
   12.71 -    load_key(xmm_temp, key, 0xc0, xmm_key_shuf_mask);
   12.72 -    __ subl(keylen, 2);
   12.73 -    __ jcc(Assembler::equal, L_doLast);
   12.74 -    __ aesenc(xmm_result, xmm_temp);                   // only in 256 bit keys
   12.75 -    aes_enc_key(xmm_result, xmm_temp, key, 0xd0, xmm_key_shuf_mask);
   12.76 -    load_key(xmm_temp, key, 0xe0, xmm_key_shuf_mask);
   12.77 +    load_key(xmm_temp1, key, 0x00, xmm_key_shuf_mask);
   12.78 +    __ pxor(xmm_result, xmm_temp1);
   12.79 +
   12.80 +    load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
   12.81 +    load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
   12.82 +    load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
   12.83 +    load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
   12.84 +
   12.85 +    __ aesenc(xmm_result, xmm_temp1);
   12.86 +    __ aesenc(xmm_result, xmm_temp2);
   12.87 +    __ aesenc(xmm_result, xmm_temp3);
   12.88 +    __ aesenc(xmm_result, xmm_temp4);
   12.89 +
   12.90 +    load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
   12.91 +    load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
   12.92 +    load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
   12.93 +    load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
   12.94 +
   12.95 +    __ aesenc(xmm_result, xmm_temp1);
   12.96 +    __ aesenc(xmm_result, xmm_temp2);
   12.97 +    __ aesenc(xmm_result, xmm_temp3);
   12.98 +    __ aesenc(xmm_result, xmm_temp4);
   12.99 +
  12.100 +    load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
  12.101 +    load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
  12.102 +
  12.103 +    __ cmpl(keylen, 44);
  12.104 +    __ jccb(Assembler::equal, L_doLast);
  12.105 +
  12.106 +    __ aesenc(xmm_result, xmm_temp1);
  12.107 +    __ aesenc(xmm_result, xmm_temp2);
  12.108 +
  12.109 +    load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
  12.110 +    load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
  12.111 +
  12.112 +    __ cmpl(keylen, 52);
  12.113 +    __ jccb(Assembler::equal, L_doLast);
  12.114 +
  12.115 +    __ aesenc(xmm_result, xmm_temp1);
  12.116 +    __ aesenc(xmm_result, xmm_temp2);
  12.117 +
  12.118 +    load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
  12.119 +    load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
  12.120  
  12.121      __ BIND(L_doLast);
  12.122 -    __ aesenclast(xmm_result, xmm_temp);
  12.123 +    __ aesenc(xmm_result, xmm_temp1);
  12.124 +    __ aesenclast(xmm_result, xmm_temp2);
  12.125      __ movdqu(Address(to, 0), xmm_result);        // store the result
  12.126      __ xorptr(rax, rax); // return 0
  12.127      __ leave(); // required for proper stackwalking of RuntimeStub frame
  12.128 @@ -3040,7 +3055,7 @@
  12.129    //   c_rarg2   - K (key) in little endian int array
  12.130    //
  12.131    address generate_aescrypt_decryptBlock() {
  12.132 -    assert(UseAES && (UseAVX > 0), "need AES instructions and misaligned SSE support");
  12.133 +    assert(UseAES, "need AES instructions and misaligned SSE support");
  12.134      __ align(CodeEntryAlignment);
  12.135      StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock");
  12.136      Label L_doLast;
  12.137 @@ -3052,15 +3067,17 @@
  12.138      const Register keylen      = rax;
  12.139  
  12.140      const XMMRegister xmm_result = xmm0;
  12.141 -    const XMMRegister xmm_temp   = xmm1;
  12.142 -    const XMMRegister xmm_key_shuf_mask = xmm2;
  12.143 +    const XMMRegister xmm_key_shuf_mask = xmm1;
  12.144 +    // On win64 xmm6-xmm15 must be preserved so don't use them.
  12.145 +    const XMMRegister xmm_temp1  = xmm2;
  12.146 +    const XMMRegister xmm_temp2  = xmm3;
  12.147 +    const XMMRegister xmm_temp3  = xmm4;
  12.148 +    const XMMRegister xmm_temp4  = xmm5;
  12.149  
  12.150      __ enter(); // required for proper stackwalking of RuntimeStub frame
  12.151  
  12.152 +    // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
  12.153      __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
  12.154 -    // keylen = # of 32-bit words, convert to 128-bit words
  12.155 -    __ shrl(keylen, 2);
  12.156 -    __ subl(keylen, 11);   // every key has at least 11 128-bit words, some have more
  12.157  
  12.158      __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
  12.159      __ movdqu(xmm_result, Address(from, 0));
  12.160 @@ -3068,29 +3085,55 @@
  12.161      // for decryption java expanded key ordering is rotated one position from what we want
  12.162      // so we start from 0x10 here and hit 0x00 last
  12.163      // we don't know if the key is aligned, hence not using load-execute form
  12.164 -    load_key(xmm_temp, key, 0x10, xmm_key_shuf_mask);
  12.165 -    __ pxor  (xmm_result, xmm_temp);
  12.166 -    for (int offset = 0x20; offset <= 0xa0; offset += 0x10) {
  12.167 -      aes_dec_key(xmm_result, xmm_temp, key, offset, xmm_key_shuf_mask);
  12.168 -    }
  12.169 -    __ cmpl(keylen, 0);
  12.170 -    __ jcc(Assembler::equal, L_doLast);
  12.171 -    // only in 192 and 256 bit keys
  12.172 -    aes_dec_key(xmm_result, xmm_temp, key, 0xb0, xmm_key_shuf_mask);
  12.173 -    aes_dec_key(xmm_result, xmm_temp, key, 0xc0, xmm_key_shuf_mask);
  12.174 -    __ subl(keylen, 2);
  12.175 -    __ jcc(Assembler::equal, L_doLast);
  12.176 -    // only in 256 bit keys
  12.177 -    aes_dec_key(xmm_result, xmm_temp, key, 0xd0, xmm_key_shuf_mask);
  12.178 -    aes_dec_key(xmm_result, xmm_temp, key, 0xe0, xmm_key_shuf_mask);
  12.179 +    load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
  12.180 +    load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
  12.181 +    load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
  12.182 +    load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
  12.183 +
  12.184 +    __ pxor  (xmm_result, xmm_temp1);
  12.185 +    __ aesdec(xmm_result, xmm_temp2);
  12.186 +    __ aesdec(xmm_result, xmm_temp3);
  12.187 +    __ aesdec(xmm_result, xmm_temp4);
  12.188 +
  12.189 +    load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
  12.190 +    load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
  12.191 +    load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
  12.192 +    load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
  12.193 +
  12.194 +    __ aesdec(xmm_result, xmm_temp1);
  12.195 +    __ aesdec(xmm_result, xmm_temp2);
  12.196 +    __ aesdec(xmm_result, xmm_temp3);
  12.197 +    __ aesdec(xmm_result, xmm_temp4);
  12.198 +
  12.199 +    load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
  12.200 +    load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
  12.201 +    load_key(xmm_temp3, key, 0x00, xmm_key_shuf_mask);
  12.202 +
  12.203 +    __ cmpl(keylen, 44);
  12.204 +    __ jccb(Assembler::equal, L_doLast);
  12.205 +
  12.206 +    __ aesdec(xmm_result, xmm_temp1);
  12.207 +    __ aesdec(xmm_result, xmm_temp2);
  12.208 +
  12.209 +    load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
  12.210 +    load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
  12.211 +
  12.212 +    __ cmpl(keylen, 52);
  12.213 +    __ jccb(Assembler::equal, L_doLast);
  12.214 +
  12.215 +    __ aesdec(xmm_result, xmm_temp1);
  12.216 +    __ aesdec(xmm_result, xmm_temp2);
  12.217 +
  12.218 +    load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
  12.219 +    load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
  12.220  
  12.221      __ BIND(L_doLast);
  12.222 +    __ aesdec(xmm_result, xmm_temp1);
  12.223 +    __ aesdec(xmm_result, xmm_temp2);
  12.224 +
  12.225      // for decryption the aesdeclast operation is always on key+0x00
  12.226 -    load_key(xmm_temp, key, 0x00, xmm_key_shuf_mask);
  12.227 -    __ aesdeclast(xmm_result, xmm_temp);
  12.228 -
  12.229 +    __ aesdeclast(xmm_result, xmm_temp3);
  12.230      __ movdqu(Address(to, 0), xmm_result);  // store the result
  12.231 -
  12.232      __ xorptr(rax, rax); // return 0
  12.233      __ leave(); // required for proper stackwalking of RuntimeStub frame
  12.234      __ ret(0);
  12.235 @@ -3109,7 +3152,7 @@
  12.236    //   c_rarg4   - input length
  12.237    //
  12.238    address generate_cipherBlockChaining_encryptAESCrypt() {
  12.239 -    assert(UseAES && (UseAVX > 0), "need AES instructions and misaligned SSE support");
  12.240 +    assert(UseAES, "need AES instructions and misaligned SSE support");
  12.241      __ align(CodeEntryAlignment);
  12.242      StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt");
  12.243      address start = __ pc();
  12.244 @@ -3133,16 +3176,19 @@
  12.245      const XMMRegister xmm_temp   = xmm1;
  12.246      // keys 0-10 preloaded into xmm2-xmm12
  12.247      const int XMM_REG_NUM_KEY_FIRST = 2;
  12.248 -    const int XMM_REG_NUM_KEY_LAST  = 12;
  12.249 +    const int XMM_REG_NUM_KEY_LAST  = 15;
  12.250      const XMMRegister xmm_key0   = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
  12.251 -    const XMMRegister xmm_key10  = as_XMMRegister(XMM_REG_NUM_KEY_LAST);
  12.252 +    const XMMRegister xmm_key10  = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+10);
  12.253 +    const XMMRegister xmm_key11  = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+11);
  12.254 +    const XMMRegister xmm_key12  = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+12);
  12.255 +    const XMMRegister xmm_key13  = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+13);
  12.256  
  12.257      __ enter(); // required for proper stackwalking of RuntimeStub frame
  12.258  
  12.259  #ifdef _WIN64
  12.260      // on win64, fill len_reg from stack position
  12.261      __ movl(len_reg, len_mem);
  12.262 -    // save the xmm registers which must be preserved 6-12
  12.263 +    // save the xmm registers which must be preserved 6-15
  12.264      __ subptr(rsp, -rsp_after_call_off * wordSize);
  12.265      for (int i = 6; i <= XMM_REG_NUM_KEY_LAST; i++) {
  12.266        __ movdqu(xmm_save(i), as_XMMRegister(i));
  12.267 @@ -3151,12 +3197,11 @@
  12.268  
  12.269      const XMMRegister xmm_key_shuf_mask = xmm_temp;  // used temporarily to swap key bytes up front
  12.270      __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
  12.271 -    // load up xmm regs 2 thru 12 with key 0x00 - 0xa0
  12.272 -    for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x00; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
  12.273 +    // load up xmm regs xmm2 thru xmm12 with key 0x00 - 0xa0
  12.274 +    for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x00; rnum <= XMM_REG_NUM_KEY_FIRST+10; rnum++) {
  12.275        load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask);
  12.276        offset += 0x10;
  12.277      }
  12.278 -
  12.279      __ movdqu(xmm_result, Address(rvec, 0x00));   // initialize xmm_result with r vec
  12.280  
  12.281      // now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256))
  12.282 @@ -3167,16 +3212,15 @@
  12.283      // 128 bit code follows here
  12.284      __ movptr(pos, 0);
  12.285      __ align(OptoLoopAlignment);
  12.286 +
  12.287      __ BIND(L_loopTop_128);
  12.288      __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
  12.289      __ pxor  (xmm_result, xmm_temp);               // xor with the current r vector
  12.290 -
  12.291      __ pxor  (xmm_result, xmm_key0);               // do the aes rounds
  12.292 -    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST - 1; rnum++) {
  12.293 +    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_FIRST + 9; rnum++) {
  12.294        __ aesenc(xmm_result, as_XMMRegister(rnum));
  12.295      }
  12.296      __ aesenclast(xmm_result, xmm_key10);
  12.297 -
  12.298      __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
  12.299      // no need to store r to memory until we exit
  12.300      __ addptr(pos, AESBlockSize);
  12.301 @@ -3198,24 +3242,23 @@
  12.302  
  12.303      __ BIND(L_key_192_256);
  12.304      // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
  12.305 +    load_key(xmm_key11, key, 0xb0, xmm_key_shuf_mask);
  12.306 +    load_key(xmm_key12, key, 0xc0, xmm_key_shuf_mask);
  12.307      __ cmpl(rax, 52);
  12.308      __ jcc(Assembler::notEqual, L_key_256);
  12.309  
  12.310      // 192-bit code follows here (could be changed to use more xmm registers)
  12.311      __ movptr(pos, 0);
  12.312      __ align(OptoLoopAlignment);
  12.313 +
  12.314      __ BIND(L_loopTop_192);
  12.315      __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
  12.316      __ pxor  (xmm_result, xmm_temp);               // xor with the current r vector
  12.317 -
  12.318      __ pxor  (xmm_result, xmm_key0);               // do the aes rounds
  12.319 -    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_LAST; rnum++) {
  12.320 +    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_FIRST + 11; rnum++) {
  12.321        __ aesenc(xmm_result, as_XMMRegister(rnum));
  12.322      }
  12.323 -    aes_enc_key(xmm_result, xmm_temp, key, 0xb0);
  12.324 -    load_key(xmm_temp, key, 0xc0);
  12.325 -    __ aesenclast(xmm_result, xmm_temp);
  12.326 -
  12.327 +    __ aesenclast(xmm_result, xmm_key12);
  12.328      __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
  12.329      // no need to store r to memory until we exit
  12.330      __ addptr(pos, AESBlockSize);
  12.331 @@ -3225,22 +3268,19 @@
  12.332  
  12.333      __ BIND(L_key_256);
  12.334      // 256-bit code follows here (could be changed to use more xmm registers)
  12.335 +    load_key(xmm_key13, key, 0xd0, xmm_key_shuf_mask);
  12.336      __ movptr(pos, 0);
  12.337      __ align(OptoLoopAlignment);
  12.338 +
  12.339      __ BIND(L_loopTop_256);
  12.340      __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
  12.341      __ pxor  (xmm_result, xmm_temp);               // xor with the current r vector
  12.342 -
  12.343      __ pxor  (xmm_result, xmm_key0);               // do the aes rounds
  12.344 -    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_LAST; rnum++) {
  12.345 +    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_FIRST + 13; rnum++) {
  12.346        __ aesenc(xmm_result, as_XMMRegister(rnum));
  12.347      }
  12.348 -    aes_enc_key(xmm_result, xmm_temp, key, 0xb0);
  12.349 -    aes_enc_key(xmm_result, xmm_temp, key, 0xc0);
  12.350 -    aes_enc_key(xmm_result, xmm_temp, key, 0xd0);
  12.351      load_key(xmm_temp, key, 0xe0);
  12.352      __ aesenclast(xmm_result, xmm_temp);
  12.353 -
  12.354      __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
  12.355      // no need to store r to memory until we exit
  12.356      __ addptr(pos, AESBlockSize);
  12.357 @@ -3267,7 +3307,7 @@
  12.358    //
  12.359  
  12.360    address generate_cipherBlockChaining_decryptAESCrypt_Parallel() {
  12.361 -    assert(UseAES && (UseAVX > 0), "need AES instructions and misaligned SSE support");
  12.362 +    assert(UseAES, "need AES instructions and misaligned SSE support");
  12.363      __ align(CodeEntryAlignment);
  12.364      StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt");
  12.365      address start = __ pc();
  12.366 @@ -3288,12 +3328,10 @@
  12.367  #endif
  12.368      const Register pos         = rax;
  12.369  
  12.370 -    // xmm register assignments for the loops below
  12.371 -    const XMMRegister xmm_result = xmm0;
  12.372      // keys 0-10 preloaded into xmm2-xmm12
  12.373      const int XMM_REG_NUM_KEY_FIRST = 5;
  12.374      const int XMM_REG_NUM_KEY_LAST  = 15;
  12.375 -    const XMMRegister xmm_key_first   = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
  12.376 +    const XMMRegister xmm_key_first = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
  12.377      const XMMRegister xmm_key_last  = as_XMMRegister(XMM_REG_NUM_KEY_LAST);
  12.378  
  12.379      __ enter(); // required for proper stackwalking of RuntimeStub frame
  12.380 @@ -3312,13 +3350,14 @@
  12.381      const XMMRegister xmm_key_shuf_mask = xmm1;  // used temporarily to swap key bytes up front
  12.382      __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
  12.383      // load up xmm regs 5 thru 15 with key 0x10 - 0xa0 - 0x00
  12.384 -    for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x10; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
  12.385 -      if (rnum == XMM_REG_NUM_KEY_LAST) offset = 0x00;
  12.386 +    for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x10; rnum < XMM_REG_NUM_KEY_LAST; rnum++) {
  12.387        load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask);
  12.388        offset += 0x10;
  12.389      }
  12.390 +    load_key(xmm_key_last, key, 0x00, xmm_key_shuf_mask);
  12.391  
  12.392      const XMMRegister xmm_prev_block_cipher = xmm1;  // holds cipher of previous block
  12.393 +
  12.394      // registers holding the four results in the parallelized loop
  12.395      const XMMRegister xmm_result0 = xmm0;
  12.396      const XMMRegister xmm_result1 = xmm2;
  12.397 @@ -3376,8 +3415,12 @@
  12.398      __ jmp(L_multiBlock_loopTop_128);
  12.399  
  12.400      // registers used in the non-parallelized loops
  12.401 +    // xmm register assignments for the loops below
  12.402 +    const XMMRegister xmm_result = xmm0;
  12.403      const XMMRegister xmm_prev_block_cipher_save = xmm2;
  12.404 -    const XMMRegister xmm_temp   = xmm3;
  12.405 +    const XMMRegister xmm_key11 = xmm3;
  12.406 +    const XMMRegister xmm_key12 = xmm4;
  12.407 +    const XMMRegister xmm_temp  = xmm4;
  12.408  
  12.409      __ align(OptoLoopAlignment);
  12.410      __ BIND(L_singleBlock_loopTop_128);
  12.411 @@ -3415,12 +3458,15 @@
  12.412  
  12.413      __ BIND(L_key_192_256);
  12.414      // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
  12.415 +    load_key(xmm_key11, key, 0xb0);
  12.416      __ cmpl(rax, 52);
  12.417      __ jcc(Assembler::notEqual, L_key_256);
  12.418  
  12.419      // 192-bit code follows here (could be optimized to use parallelism)
  12.420 +    load_key(xmm_key12, key, 0xc0);     // 192-bit key goes up to c0
  12.421      __ movptr(pos, 0);
  12.422      __ align(OptoLoopAlignment);
  12.423 +
  12.424      __ BIND(L_singleBlock_loopTop_192);
  12.425      __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of cipher input
  12.426      __ movdqa(xmm_prev_block_cipher_save, xmm_result);              // save for next r vector
  12.427 @@ -3428,14 +3474,13 @@
  12.428      for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST - 1; rnum++) {
  12.429        __ aesdec(xmm_result, as_XMMRegister(rnum));
  12.430      }
  12.431 -    aes_dec_key(xmm_result, xmm_temp, key, 0xb0);     // 192-bit key goes up to c0
  12.432 -    aes_dec_key(xmm_result, xmm_temp, key, 0xc0);
  12.433 +    __ aesdec(xmm_result, xmm_key11);
  12.434 +    __ aesdec(xmm_result, xmm_key12);
  12.435      __ aesdeclast(xmm_result, xmm_key_last);                    // xmm15 always came from key+0
  12.436      __ pxor  (xmm_result, xmm_prev_block_cipher);               // xor with the current r vector
  12.437 -    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
  12.438 +    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);  // store into the next 16 bytes of output
  12.439      // no need to store r to memory until we exit
  12.440 -    __ movdqa(xmm_prev_block_cipher, xmm_prev_block_cipher_save);              // set up next r vector with cipher input from this block
  12.441 -
  12.442 +    __ movdqa(xmm_prev_block_cipher, xmm_prev_block_cipher_save);  // set up next r vector with cipher input from this block
  12.443      __ addptr(pos, AESBlockSize);
  12.444      __ subptr(len_reg, AESBlockSize);
  12.445      __ jcc(Assembler::notEqual,L_singleBlock_loopTop_192);
  12.446 @@ -3445,23 +3490,26 @@
  12.447      // 256-bit code follows here (could be optimized to use parallelism)
  12.448      __ movptr(pos, 0);
  12.449      __ align(OptoLoopAlignment);
  12.450 +
  12.451      __ BIND(L_singleBlock_loopTop_256);
  12.452 -    __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of cipher input
  12.453 +    __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of cipher input
  12.454      __ movdqa(xmm_prev_block_cipher_save, xmm_result);              // save for next r vector
  12.455      __ pxor  (xmm_result, xmm_key_first);               // do the aes dec rounds
  12.456      for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST - 1; rnum++) {
  12.457        __ aesdec(xmm_result, as_XMMRegister(rnum));
  12.458      }
  12.459 -    aes_dec_key(xmm_result, xmm_temp, key, 0xb0);     // 256-bit key goes up to e0
  12.460 -    aes_dec_key(xmm_result, xmm_temp, key, 0xc0);
  12.461 -    aes_dec_key(xmm_result, xmm_temp, key, 0xd0);
  12.462 -    aes_dec_key(xmm_result, xmm_temp, key, 0xe0);
  12.463 -    __ aesdeclast(xmm_result, xmm_key_last);             // xmm15 came from key+0
  12.464 +    __ aesdec(xmm_result, xmm_key11);
  12.465 +    load_key(xmm_temp, key, 0xc0);
  12.466 +    __ aesdec(xmm_result, xmm_temp);
  12.467 +    load_key(xmm_temp, key, 0xd0);
  12.468 +    __ aesdec(xmm_result, xmm_temp);
  12.469 +    load_key(xmm_temp, key, 0xe0);     // 256-bit key goes up to e0
  12.470 +    __ aesdec(xmm_result, xmm_temp);
  12.471 +    __ aesdeclast(xmm_result, xmm_key_last);          // xmm15 came from key+0
  12.472      __ pxor  (xmm_result, xmm_prev_block_cipher);               // xor with the current r vector
  12.473 -    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
  12.474 +    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);  // store into the next 16 bytes of output
  12.475      // no need to store r to memory until we exit
  12.476 -    __ movdqa(xmm_prev_block_cipher, xmm_prev_block_cipher_save);              // set up next r vector with cipher input from this block
  12.477 -
  12.478 +    __ movdqa(xmm_prev_block_cipher, xmm_prev_block_cipher_save);  // set up next r vector with cipher input from this block
  12.479      __ addptr(pos, AESBlockSize);
  12.480      __ subptr(len_reg, AESBlockSize);
  12.481      __ jcc(Assembler::notEqual,L_singleBlock_loopTop_256);

    13.1 --- a/src/cpu/x86/vm/vm_version_x86.cpp	Wed Dec 19 16:10:19 2012 -0800
    13.2 +++ b/src/cpu/x86/vm/vm_version_x86.cpp	Fri Dec 21 01:39:34 2012 -0800
    13.3 @@ -489,8 +489,8 @@
    13.4    }
    13.5  
    13.6    // The AES intrinsic stubs require AES instruction support (of course)
    13.7 -  // but also require AVX and sse3 modes for instructions it use.
    13.8 -  if (UseAES && (UseAVX > 0) && (UseSSE > 2)) {
    13.9 +  // but also require sse3 mode for instructions it use.
   13.10 +  if (UseAES && (UseSSE > 2)) {
   13.11      if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
   13.12        UseAESIntrinsics = true;
   13.13      }

    14.1 --- a/src/cpu/zero/vm/assembler_zero.cpp	Wed Dec 19 16:10:19 2012 -0800
    14.2 +++ b/src/cpu/zero/vm/assembler_zero.cpp	Fri Dec 21 01:39:34 2012 -0800
    14.3 @@ -56,15 +56,9 @@
    14.4    ShouldNotCallThis();
    14.5  }
    14.6  
    14.7 -#ifndef PRODUCT
    14.8 -void Assembler::pd_print_patched_instruction(address branch) {
    14.9 -  ShouldNotCallThis();
   14.10 -}
   14.11 -#endif // PRODUCT
   14.12 -
   14.13  void MacroAssembler::align(int modulus) {
   14.14    while (offset() % modulus != 0)
   14.15 -    emit_byte(AbstractAssembler::code_fill_byte());
   14.16 +    emit_int8(AbstractAssembler::code_fill_byte());
   14.17  }
   14.18  
   14.19  void MacroAssembler::bang_stack_with_offset(int offset) {
   14.20 @@ -72,8 +66,7 @@
   14.21  }
   14.22  
   14.23  void MacroAssembler::advance(int bytes) {
   14.24 -  _code_pos += bytes;
   14.25 -  sync();
   14.26 +  code_section()->set_end(code_section()->end() + bytes);
   14.27  }
   14.28  
   14.29  RegisterOrConstant MacroAssembler::delayed_value_impl(

    15.1 --- a/src/cpu/zero/vm/assembler_zero.hpp	Wed Dec 19 16:10:19 2012 -0800
    15.2 +++ b/src/cpu/zero/vm/assembler_zero.hpp	Fri Dec 21 01:39:34 2012 -0800
    15.3 @@ -37,9 +37,6 @@
    15.4  
    15.5   public:
    15.6    void pd_patch_instruction(address branch, address target);
    15.7 -#ifndef PRODUCT
    15.8 -  static void pd_print_patched_instruction(address branch);
    15.9 -#endif // PRODUCT
   15.10  };
   15.11  
   15.12  class MacroAssembler : public Assembler {

    16.1 --- a/src/os_cpu/solaris_x86/vm/assembler_solaris_x86.cpp	Wed Dec 19 16:10:19 2012 -0800
    16.2 +++ b/src/os_cpu/solaris_x86/vm/assembler_solaris_x86.cpp	Fri Dec 21 01:39:34 2012 -0800
    16.3 @@ -116,7 +116,7 @@
    16.4    ThreadLocalStorage::pd_tlsAccessMode tlsMode = ThreadLocalStorage::pd_getTlsAccessMode ();
    16.5    if (tlsMode == ThreadLocalStorage::pd_tlsAccessIndirect) {            // T1
    16.6       // Use thread as a temporary: mov r, gs:[0]; mov r, [r+tlsOffset]
    16.7 -     emit_byte (segment);
    16.8 +     emit_int8 (segment);
    16.9       // ExternalAddress doesn't work because it can't take NULL
   16.10       AddressLiteral null(0, relocInfo::none);
   16.11       movptr (thread, null);
   16.12 @@ -125,7 +125,7 @@
   16.13    } else
   16.14    if (tlsMode == ThreadLocalStorage::pd_tlsAccessDirect) {              // T2
   16.15       // mov r, gs:[tlsOffset]
   16.16 -     emit_byte (segment);
   16.17 +     emit_int8 (segment);
   16.18       AddressLiteral tls_off((address)ThreadLocalStorage::pd_getTlsOffset(), relocInfo::none);
   16.19       movptr (thread, tls_off);
   16.20       return ;

    17.1 --- a/src/os_cpu/windows_x86/vm/assembler_windows_x86.cpp	Wed Dec 19 16:10:19 2012 -0800
    17.2 +++ b/src/os_cpu/windows_x86/vm/assembler_windows_x86.cpp	Fri Dec 21 01:39:34 2012 -0800
    17.3 @@ -30,7 +30,7 @@
    17.4  
    17.5  
    17.6  void MacroAssembler::int3() {
    17.7 -  emit_byte(0xCC);
    17.8 +  emit_int8((unsigned char)0xCC);
    17.9  }
   17.10  
   17.11  #ifndef _LP64

    18.1 --- a/src/share/vm/asm/assembler.cpp	Wed Dec 19 16:10:19 2012 -0800
    18.2 +++ b/src/share/vm/asm/assembler.cpp	Fri Dec 21 01:39:34 2012 -0800
    18.3 @@ -109,37 +109,6 @@
    18.4    ICache::invalidate_range(addr_at(0), offset());
    18.5  }
    18.6  
    18.7 -
    18.8 -void AbstractAssembler::a_byte(int x) {
    18.9 -  emit_byte(x);
   18.10 -}
   18.11 -
   18.12 -
   18.13 -void AbstractAssembler::a_long(jint x) {
   18.14 -  emit_long(x);
   18.15 -}
   18.16 -
   18.17 -// Labels refer to positions in the (to be) generated code.  There are bound
   18.18 -// and unbound
   18.19 -//
   18.20 -// Bound labels refer to known positions in the already generated code.
   18.21 -// offset() is the position the label refers to.
   18.22 -//
   18.23 -// Unbound labels refer to unknown positions in the code to be generated; it
   18.24 -// may contain a list of unresolved displacements that refer to it
   18.25 -#ifndef PRODUCT
   18.26 -void AbstractAssembler::print(Label& L) {
   18.27 -  if (L.is_bound()) {
   18.28 -    tty->print_cr("bound label to %d|%d", L.loc_pos(), L.loc_sect());
   18.29 -  } else if (L.is_unbound()) {
   18.30 -    L.print_instructions((MacroAssembler*)this);
   18.31 -  } else {
   18.32 -    tty->print_cr("label in inconsistent state (loc = %d)", L.loc());
   18.33 -  }
   18.34 -}
   18.35 -#endif // PRODUCT
   18.36 -
   18.37 -
   18.38  void AbstractAssembler::bind(Label& L) {
   18.39    if (L.is_bound()) {
   18.40      // Assembler can bind a label more than once to the same place.
   18.41 @@ -342,28 +311,3 @@
   18.42  #endif
   18.43    return offset < 0 || os::vm_page_size() <= offset;
   18.44  }
   18.45 -
   18.46 -#ifndef PRODUCT
   18.47 -void Label::print_instructions(MacroAssembler* masm) const {
   18.48 -  CodeBuffer* cb = masm->code();
   18.49 -  for (int i = 0; i < _patch_index; ++i) {
   18.50 -    int branch_loc;
   18.51 -    if (i >= PatchCacheSize) {
   18.52 -      branch_loc = _patch_overflow->at(i - PatchCacheSize);
   18.53 -    } else {
   18.54 -      branch_loc = _patches[i];
   18.55 -    }
   18.56 -    int branch_pos  = CodeBuffer::locator_pos(branch_loc);
   18.57 -    int branch_sect = CodeBuffer::locator_sect(branch_loc);
   18.58 -    address branch = cb->locator_address(branch_loc);
   18.59 -    tty->print_cr("unbound label");
   18.60 -    tty->print("@ %d|%d ", branch_pos, branch_sect);
   18.61 -    if (branch_sect == CodeBuffer::SECT_CONSTS) {
   18.62 -      tty->print_cr(PTR_FORMAT, *(address*)branch);
   18.63 -      continue;
   18.64 -    }
   18.65 -    masm->pd_print_patched_instruction(branch);
   18.66 -    tty->cr();
   18.67 -  }
   18.68 -}
   18.69 -#endif // ndef PRODUCT

    19.1 --- a/src/share/vm/asm/assembler.hpp	Wed Dec 19 16:10:19 2012 -0800
    19.2 +++ b/src/share/vm/asm/assembler.hpp	Fri Dec 21 01:39:34 2012 -0800
    19.3 @@ -216,17 +216,6 @@
    19.4    bool isByte(int x) const             { return 0 <= x && x < 0x100; }
    19.5    bool isShiftCount(int x) const       { return 0 <= x && x < 32; }
    19.6  
    19.7 -  void emit_int8(   int8_t  x) { code_section()->emit_int8(   x); }
    19.8 -  void emit_int16(  int16_t x) { code_section()->emit_int16(  x); }
    19.9 -  void emit_int32(  int32_t x) { code_section()->emit_int32(  x); }
   19.10 -  void emit_int64(  int64_t x) { code_section()->emit_int64(  x); }
   19.11 -
   19.12 -  void emit_float(  jfloat  x) { code_section()->emit_float(  x); }
   19.13 -  void emit_double( jdouble x) { code_section()->emit_double( x); }
   19.14 -  void emit_address(address x) { code_section()->emit_address(x); }
   19.15 -
   19.16 -  void emit_byte(int x)  { emit_int8 (x); }  // deprecated
   19.17 -  void emit_word(int x)  { emit_int16(x); }  // deprecated
   19.18    void emit_long(jint x) { emit_int32(x); }  // deprecated
   19.19  
   19.20    // Instruction boundaries (required when emitting relocatable values).
   19.21 @@ -277,9 +266,6 @@
   19.22    };
   19.23  #endif
   19.24  
   19.25 -  // Label functions
   19.26 -  void print(Label& L);
   19.27 -
   19.28   public:
   19.29  
   19.30    // Creation
   19.31 @@ -288,6 +274,15 @@
   19.32    // ensure buf contains all code (call this before using/copying the code)
   19.33    void flush();
   19.34  
   19.35 +  void emit_int8(   int8_t  x) { code_section()->emit_int8(   x); }
   19.36 +  void emit_int16(  int16_t x) { code_section()->emit_int16(  x); }
   19.37 +  void emit_int32(  int32_t x) { code_section()->emit_int32(  x); }
   19.38 +  void emit_int64(  int64_t x) { code_section()->emit_int64(  x); }
   19.39 +
   19.40 +  void emit_float(  jfloat  x) { code_section()->emit_float(  x); }
   19.41 +  void emit_double( jdouble x) { code_section()->emit_double( x); }
   19.42 +  void emit_address(address x) { code_section()->emit_address(x); }
   19.43 +
   19.44    // min and max values for signed immediate ranges
   19.45    static int min_simm(int nbits) { return -(intptr_t(1) << (nbits - 1))    ; }
   19.46    static int max_simm(int nbits) { return  (intptr_t(1) << (nbits - 1)) - 1; }
   19.47 @@ -327,8 +322,6 @@
   19.48    void    clear_inst_mark()       {        code_section()->clear_mark(); }
   19.49  
   19.50    // Constants in code
   19.51 -  void a_byte(int x);
   19.52 -  void a_long(jint x);
   19.53    void relocate(RelocationHolder const& rspec, int format = 0) {
   19.54      assert(!pd_check_instruction_mark()
   19.55          || inst_mark() == NULL || inst_mark() == code_section()->end(),
   19.56 @@ -441,15 +434,6 @@
   19.57     */
   19.58    void pd_patch_instruction(address branch, address target);
   19.59  
   19.60 -#ifndef PRODUCT
   19.61 -  /**
   19.62 -   * Platform-dependent method of printing an instruction that needs to be
   19.63 -   * patched.
   19.64 -   *
   19.65 -   * @param branch the instruction to be patched in the buffer.
   19.66 -   */
   19.67 -  static void pd_print_patched_instruction(address branch);
   19.68 -#endif // PRODUCT
   19.69  };
   19.70  
   19.71  #ifdef TARGET_ARCH_x86

    20.1 --- a/src/share/vm/c1/c1_GraphBuilder.cpp	Wed Dec 19 16:10:19 2012 -0800
    20.2 +++ b/src/share/vm/c1/c1_GraphBuilder.cpp	Fri Dec 21 01:39:34 2012 -0800
    20.3 @@ -3442,6 +3442,11 @@
    20.4        preserves_state = true;
    20.5        break;
    20.6  
    20.7 +    case vmIntrinsics::_loadFence :
    20.8 +    case vmIntrinsics::_storeFence:
    20.9 +    case vmIntrinsics::_fullFence :
   20.10 +      break;
   20.11 +
   20.12      default                       : return false; // do not inline
   20.13    }
   20.14    // create intrinsic node

    21.1 --- a/src/share/vm/c1/c1_LIRGenerator.cpp	Wed Dec 19 16:10:19 2012 -0800
    21.2 +++ b/src/share/vm/c1/c1_LIRGenerator.cpp	Fri Dec 21 01:39:34 2012 -0800
    21.3 @@ -2977,6 +2977,16 @@
    21.4      do_CompareAndSwap(x, longType);
    21.5      break;
    21.6  
    21.7 +  case vmIntrinsics::_loadFence :
    21.8 +    if (os::is_MP()) __ membar_acquire();
    21.9 +    break;
   21.10 +  case vmIntrinsics::_storeFence:
   21.11 +    if (os::is_MP()) __ membar_release();
   21.12 +    break;
   21.13 +  case vmIntrinsics::_fullFence :
   21.14 +    if (os::is_MP()) __ membar();
   21.15 +    break;
   21.16 +
   21.17    case vmIntrinsics::_Reference_get:
   21.18      do_Reference_get(x);
   21.19      break;

    22.1 --- a/src/share/vm/ci/ciField.cpp	Wed Dec 19 16:10:19 2012 -0800
    22.2 +++ b/src/share/vm/ci/ciField.cpp	Fri Dec 21 01:39:34 2012 -0800
    22.3 @@ -366,10 +366,12 @@
    22.4  // ------------------------------------------------------------------
    22.5  // ciField::print
    22.6  void ciField::print() {
    22.7 -  tty->print("<ciField ");
    22.8 +  tty->print("<ciField name=");
    22.9    _holder->print_name();
   22.10    tty->print(".");
   22.11    _name->print_symbol();
   22.12 +  tty->print(" signature=");
   22.13 +  _signature->print_symbol();
   22.14    tty->print(" offset=%d type=", _offset);
   22.15    if (_type != NULL) _type->print_name();
   22.16    else               tty->print("(reference)");

    23.1 --- a/src/share/vm/classfile/classLoaderData.cpp	Wed Dec 19 16:10:19 2012 -0800
    23.2 +++ b/src/share/vm/classfile/classLoaderData.cpp	Fri Dec 21 01:39:34 2012 -0800
    23.3 @@ -169,16 +169,18 @@
    23.4      ok = (objArrayOop)ok->obj_at(1);
    23.5    }
    23.6  
    23.7 +  // Must handle over GC points
    23.8 +  assert (last != NULL, "dependencies should be initialized");
    23.9 +  objArrayHandle last_handle(THREAD, last);
   23.10 +
   23.11    // Create a new dependency node with fields for (class_loader or mirror, next)
   23.12    objArrayOop deps = oopFactory::new_objectArray(2, CHECK);
   23.13    deps->obj_at_put(0, dependency());
   23.14  
   23.15 -  // Must handle over more GC points
   23.16 +  // Must handle over GC points
   23.17    objArrayHandle new_dependency(THREAD, deps);
   23.18  
   23.19    // Add the dependency under lock
   23.20 -  assert (last != NULL, "dependencies should be initialized");
   23.21 -  objArrayHandle last_handle(THREAD, last);
   23.22    locked_add_dependency(last_handle, new_dependency);
   23.23  }
   23.24

    24.1 --- a/src/share/vm/classfile/vmSymbols.hpp	Wed Dec 19 16:10:19 2012 -0800
    24.2 +++ b/src/share/vm/classfile/vmSymbols.hpp	Fri Dec 21 01:39:34 2012 -0800
    24.3 @@ -756,6 +756,15 @@
    24.4    do_intrinsic(_unpark,                   sun_misc_Unsafe,        unpark_name, unpark_signature,                 F_RN)  \
    24.5     do_name(     unpark_name,                                     "unpark")                                              \
    24.6     do_alias(    unpark_signature,                               /*(LObject;)V*/ object_void_signature)                  \
    24.7 +  do_intrinsic(_loadFence,                sun_misc_Unsafe,        loadFence_name, loadFence_signature,           F_RN)  \
    24.8 +   do_name(     loadFence_name,                                  "loadFence")                                           \
    24.9 +   do_alias(    loadFence_signature,                              void_method_signature)                                \
   24.10 +  do_intrinsic(_storeFence,               sun_misc_Unsafe,        storeFence_name, storeFence_signature,         F_RN)  \
   24.11 +   do_name(     storeFence_name,                                 "storeFence")                                          \
   24.12 +   do_alias(    storeFence_signature,                             void_method_signature)                                \
   24.13 +  do_intrinsic(_fullFence,                sun_misc_Unsafe,        fullFence_name, fullFence_signature,           F_RN)  \
   24.14 +   do_name(     fullFence_name,                                  "fullFence")                                           \
   24.15 +   do_alias(    fullFence_signature,                              void_method_signature)                                \
   24.16                                                                                                                          \
   24.17    /* unsafe memory references (there are a lot of them...) */                                                           \
   24.18    do_signature(getObject_signature,       "(Ljava/lang/Object;J)Ljava/lang/Object;")                                    \
   24.19 @@ -897,12 +906,14 @@
   24.20    do_intrinsic(_getAndAddLong,            sun_misc_Unsafe,        getAndAddLong_name, getAndAddLong_signature, F_R)     \
   24.21     do_name(     getAndAddLong_name,                               "getAndAddLong")                                      \
   24.22     do_signature(getAndAddLong_signature,                          "(Ljava/lang/Object;JJ)J" )                           \
   24.23 -  do_intrinsic(_getAndSetInt,             sun_misc_Unsafe,        getAndSet_name, getAndSetInt_signature, F_R)          \
   24.24 -   do_name(     getAndSet_name,                                   "getAndSet")                                          \
   24.25 +  do_intrinsic(_getAndSetInt,             sun_misc_Unsafe,        getAndSetInt_name, getAndSetInt_signature, F_R)       \
   24.26 +   do_name(     getAndSetInt_name,                                "getAndSetInt")                                       \
   24.27     do_alias(    getAndSetInt_signature,                         /*"(Ljava/lang/Object;JI)I"*/ getAndAddInt_signature)   \
   24.28 -  do_intrinsic(_getAndSetLong,            sun_misc_Unsafe,        getAndSet_name, getAndSetLong_signature, F_R)         \
   24.29 +  do_intrinsic(_getAndSetLong,            sun_misc_Unsafe,        getAndSetLong_name, getAndSetLong_signature, F_R)     \
   24.30 +   do_name(     getAndSetLong_name,                               "getAndSetLong")                                      \
   24.31     do_alias(    getAndSetLong_signature,                        /*"(Ljava/lang/Object;JJ)J"*/ getAndAddLong_signature)  \
   24.32 -  do_intrinsic(_getAndSetObject,          sun_misc_Unsafe,        getAndSet_name, getAndSetObject_signature,  F_R)      \
   24.33 +  do_intrinsic(_getAndSetObject,          sun_misc_Unsafe,        getAndSetObject_name, getAndSetObject_signature,  F_R)\
   24.34 +   do_name(     getAndSetObject_name,                             "getAndSetObject")                                    \
   24.35     do_signature(getAndSetObject_signature,                        "(Ljava/lang/Object;JLjava/lang/Object;)Ljava/lang/Object;" ) \
   24.36                                                                                                                          \
   24.37    /* prefetch_signature is shared by all prefetch variants */                                                           \

    25.1 --- a/src/share/vm/compiler/compilerOracle.cpp	Wed Dec 19 16:10:19 2012 -0800
    25.2 +++ b/src/share/vm/compiler/compilerOracle.cpp	Fri Dec 21 01:39:34 2012 -0800
    25.3 @@ -538,6 +538,7 @@
    25.4  
    25.5    if (match != NULL) {
    25.6      if (!_quiet) {
    25.7 +      ResourceMark rm;
    25.8        tty->print("CompilerOracle: %s ", command_names[command]);
    25.9        match->print();
   25.10      }

    26.1 --- a/src/share/vm/opto/addnode.cpp	Wed Dec 19 16:10:19 2012 -0800
    26.2 +++ b/src/share/vm/opto/addnode.cpp	Fri Dec 21 01:39:34 2012 -0800
    26.3 @@ -189,6 +189,11 @@
    26.4        set_req(1, addx);
    26.5        set_req(2, a22);
    26.6        progress = this;
    26.7 +      PhaseIterGVN *igvn = phase->is_IterGVN();
    26.8 +      if (add2->outcnt() == 0 && igvn) {
    26.9 +        // add disconnected.
   26.10 +        igvn->_worklist.push(add2);
   26.11 +      }
   26.12      }
   26.13    }
   26.14  
   26.15 @@ -624,6 +629,11 @@
   26.16      if( t22->singleton() && (t22 != Type::TOP) ) {  // Right input is an add of a constant?
   26.17        set_req(Address, phase->transform(new (phase->C) AddPNode(in(Base),in(Address),add->in(1))));
   26.18        set_req(Offset, add->in(2));
   26.19 +      PhaseIterGVN *igvn = phase->is_IterGVN();
   26.20 +      if (add->outcnt() == 0 && igvn) {
   26.21 +        // add disconnected.
   26.22 +        igvn->_worklist.push((Node*)add);
   26.23 +      }
   26.24        return this;              // Made progress
   26.25      }
   26.26    }

    27.1 --- a/src/share/vm/opto/bytecodeInfo.cpp	Wed Dec 19 16:10:19 2012 -0800
    27.2 +++ b/src/share/vm/opto/bytecodeInfo.cpp	Fri Dec 21 01:39:34 2012 -0800
    27.3 @@ -403,7 +403,7 @@
    27.4  //------------------------------print_inlining---------------------------------
    27.5  // Really, the failure_msg can be a success message also.
    27.6  void InlineTree::print_inlining(ciMethod* callee_method, int caller_bci, const char* failure_msg) const {
    27.7 -  CompileTask::print_inlining(callee_method, inline_level(), caller_bci, failure_msg ? failure_msg : "inline");
    27.8 +  C->print_inlining(callee_method, inline_level(), caller_bci, failure_msg ? failure_msg : "inline");
    27.9    if (callee_method == NULL)  tty->print(" callee not monotonic or profiled");
   27.10    if (Verbose && callee_method) {
   27.11      const InlineTree *top = this;

    28.1 --- a/src/share/vm/opto/callGenerator.cpp	Wed Dec 19 16:10:19 2012 -0800
    28.2 +++ b/src/share/vm/opto/callGenerator.cpp	Fri Dec 21 01:39:34 2012 -0800
    28.3 @@ -274,6 +274,9 @@
    28.4    virtual void do_late_inline();
    28.5  
    28.6    virtual JVMState* generate(JVMState* jvms) {
    28.7 +    Compile *C = Compile::current();
    28.8 +    C->print_inlining_skip(this);
    28.9 +
   28.10      // Record that this call site should be revisited once the main
   28.11      // parse is finished.
   28.12      Compile::current()->add_late_inline(this);
   28.13 @@ -284,7 +287,6 @@
   28.14      // as is done for allocations and macro expansion.
   28.15      return DirectCallGenerator::generate(jvms);
   28.16    }
   28.17 -
   28.18  };
   28.19  
   28.20  
   28.21 @@ -307,7 +309,9 @@
   28.22  
   28.23    // Make sure the state is a MergeMem for parsing.
   28.24    if (!map->in(TypeFunc::Memory)->is_MergeMem()) {
   28.25 -    map->set_req(TypeFunc::Memory, MergeMemNode::make(C, map->in(TypeFunc::Memory)));
   28.26 +    Node* mem = MergeMemNode::make(C, map->in(TypeFunc::Memory));
   28.27 +    C->initial_gvn()->set_type_bottom(mem);
   28.28 +    map->set_req(TypeFunc::Memory, mem);
   28.29    }
   28.30  
   28.31    // Make enough space for the expression stack and transfer the incoming arguments
   28.32 @@ -320,6 +324,8 @@
   28.33      }
   28.34    }
   28.35  
   28.36 +  C->print_inlining_insert(this);
   28.37 +
   28.38    CompileLog* log = C->log();
   28.39    if (log != NULL) {
   28.40      log->head("late_inline method='%d'", log->identify(method()));
   28.41 @@ -608,7 +614,7 @@
   28.42          if (cg != NULL && cg->is_inline())
   28.43            return cg;
   28.44        } else {
   28.45 -        if (PrintInlining)  CompileTask::print_inlining(callee, jvms->depth() - 1, jvms->bci(), "receiver not constant");
   28.46 +        if (PrintInlining)  C->print_inlining(callee, jvms->depth() - 1, jvms->bci(), "receiver not constant");
   28.47        }
   28.48      }
   28.49      break;

    29.1 --- a/src/share/vm/opto/callGenerator.hpp	Wed Dec 19 16:10:19 2012 -0800
    29.2 +++ b/src/share/vm/opto/callGenerator.hpp	Fri Dec 21 01:39:34 2012 -0800
    29.3 @@ -147,9 +147,9 @@
    29.4                                                  CallGenerator* cg);
    29.5    virtual Node* generate_predicate(JVMState* jvms) { return NULL; };
    29.6  
    29.7 -  static void print_inlining(ciMethod* callee, int inline_level, int bci, const char* msg) {
    29.8 +  static void print_inlining(Compile* C, ciMethod* callee, int inline_level, int bci, const char* msg) {
    29.9      if (PrintInlining)
   29.10 -      CompileTask::print_inlining(callee, inline_level, bci, msg);
   29.11 +      C->print_inlining(callee, inline_level, bci, msg);
   29.12    }
   29.13  };
   29.14

    30.1 --- a/src/share/vm/opto/callnode.cpp	Wed Dec 19 16:10:19 2012 -0800
    30.2 +++ b/src/share/vm/opto/callnode.cpp	Fri Dec 21 01:39:34 2012 -0800
    30.3 @@ -751,7 +751,7 @@
    30.4          projs->fallthrough_ioproj = pn;
    30.5        for (DUIterator j = pn->outs(); pn->has_out(j); j++) {
    30.6          Node* e = pn->out(j);
    30.7 -        if (e->Opcode() == Op_CreateEx && e->in(0)->is_CatchProj()) {
    30.8 +        if (e->Opcode() == Op_CreateEx && e->in(0)->is_CatchProj() && e->outcnt() > 0) {
    30.9            assert(projs->exobj == NULL, "only one");
   30.10            projs->exobj = e;
   30.11          }

    31.1 --- a/src/share/vm/opto/cfgnode.cpp	Wed Dec 19 16:10:19 2012 -0800
    31.2 +++ b/src/share/vm/opto/cfgnode.cpp	Fri Dec 21 01:39:34 2012 -0800
    31.3 @@ -1566,6 +1566,10 @@
    31.4      Node* n = in(j);            // Get the input
    31.5      if (rc == NULL || phase->type(rc) == Type::TOP) {
    31.6        if (n != top) {           // Not already top?
    31.7 +        PhaseIterGVN *igvn = phase->is_IterGVN();
    31.8 +        if (can_reshape && igvn != NULL) {
    31.9 +          igvn->_worklist.push(r);
   31.10 +        }
   31.11          set_req(j, top);        // Nuke it down
   31.12          progress = this;        // Record progress
   31.13        }

    32.1 --- a/src/share/vm/opto/compile.cpp	Wed Dec 19 16:10:19 2012 -0800
    32.2 +++ b/src/share/vm/opto/compile.cpp	Fri Dec 21 01:39:34 2012 -0800
    32.3 @@ -610,7 +610,9 @@
    32.4                    _trace_opto_output(TraceOptoOutput || method()->has_option("TraceOptoOutput")),
    32.5                    _printer(IdealGraphPrinter::printer()),
    32.6  #endif
    32.7 -                  _congraph(NULL) {
    32.8 +                  _congraph(NULL),
    32.9 +                  _print_inlining_list(NULL),
   32.10 +                  _print_inlining(0) {
   32.11    C = this;
   32.12  
   32.13    CompileWrapper cw(this);
   32.14 @@ -666,6 +668,9 @@
   32.15    PhaseGVN gvn(node_arena(), estimated_size);
   32.16    set_initial_gvn(&gvn);
   32.17  
   32.18 +  if (PrintInlining) {
   32.19 +    _print_inlining_list = new (comp_arena())GrowableArray<PrintInliningBuffer>(comp_arena(), 1, 1, PrintInliningBuffer());
   32.20 +  }
   32.21    { // Scope for timing the parser
   32.22      TracePhase t3("parse", &_t_parser, true);
   32.23  
   32.24 @@ -754,6 +759,7 @@
   32.25        }
   32.26      }
   32.27      assert(_late_inlines.length() == 0, "should have been processed");
   32.28 +    dump_inlining();
   32.29  
   32.30      print_method("Before RemoveUseless", 3);
   32.31  
   32.32 @@ -899,7 +905,9 @@
   32.33  #endif
   32.34      _dead_node_list(comp_arena()),
   32.35      _dead_node_count(0),
   32.36 -    _congraph(NULL) {
   32.37 +    _congraph(NULL),
   32.38 +    _print_inlining_list(NULL),
   32.39 +    _print_inlining(0) {
   32.40    C = this;
   32.41  
   32.42  #ifndef PRODUCT
   32.43 @@ -3351,3 +3359,11 @@
   32.44      cb.consts()->relocate((address) constant_addr, relocInfo::internal_word_type);
   32.45    }
   32.46  }
   32.47 +
   32.48 +void Compile::dump_inlining() {
   32.49 +  if (PrintInlining) {
   32.50 +    for (int i = 0; i < _print_inlining_list->length(); i++) {
   32.51 +      tty->print(_print_inlining_list->at(i).ss()->as_string());
   32.52 +    }
   32.53 +  }
   32.54 +}

    33.1 --- a/src/share/vm/opto/compile.hpp	Wed Dec 19 16:10:19 2012 -0800
    33.2 +++ b/src/share/vm/opto/compile.hpp	Fri Dec 21 01:39:34 2012 -0800
    33.3 @@ -30,6 +30,7 @@
    33.4  #include "code/debugInfoRec.hpp"
    33.5  #include "code/exceptionHandlerTable.hpp"
    33.6  #include "compiler/compilerOracle.hpp"
    33.7 +#include "compiler/compileBroker.hpp"
    33.8  #include "libadt/dict.hpp"
    33.9  #include "libadt/port.hpp"
   33.10  #include "libadt/vectset.hpp"
   33.11 @@ -369,6 +370,61 @@
   33.12    GrowableArray<CallGenerator*> _late_inlines;  // List of CallGenerators to be revisited after
   33.13                                                  // main parsing has finished.
   33.14  
   33.15 +  // Inlining may not happen in parse order which would make
   33.16 +  // PrintInlining output confusing. Keep track of PrintInlining
   33.17 +  // pieces in order.
   33.18 +  class PrintInliningBuffer : public ResourceObj {
   33.19 +   private:
   33.20 +    CallGenerator* _cg;
   33.21 +    stringStream* _ss;
   33.22 +
   33.23 +   public:
   33.24 +    PrintInliningBuffer()
   33.25 +      : _cg(NULL) { _ss = new stringStream(); }
   33.26 +
   33.27 +    stringStream* ss() const { return _ss; }
   33.28 +    CallGenerator* cg() const { return _cg; }
   33.29 +    void set_cg(CallGenerator* cg) { _cg = cg; }
   33.30 +  };
   33.31 +
   33.32 +  GrowableArray<PrintInliningBuffer>* _print_inlining_list;
   33.33 +  int _print_inlining;
   33.34 +
   33.35 + public:
   33.36 +
   33.37 +  outputStream* print_inlining_stream() const {
   33.38 +    return _print_inlining_list->at(_print_inlining).ss();
   33.39 +  }
   33.40 +
   33.41 +  void print_inlining_skip(CallGenerator* cg) {
   33.42 +    if (PrintInlining) {
   33.43 +      _print_inlining_list->at(_print_inlining).set_cg(cg);
   33.44 +      _print_inlining++;
   33.45 +      _print_inlining_list->insert_before(_print_inlining, PrintInliningBuffer());
   33.46 +    }
   33.47 +  }
   33.48 +
   33.49 +  void print_inlining_insert(CallGenerator* cg) {
   33.50 +    if (PrintInlining) {
   33.51 +      for (int i = 0; i < _print_inlining_list->length(); i++) {
   33.52 +        if (_print_inlining_list->at(i).cg() == cg) {
   33.53 +          _print_inlining_list->insert_before(i+1, PrintInliningBuffer());
   33.54 +          _print_inlining = i+1;
   33.55 +          _print_inlining_list->at(i).set_cg(NULL);
   33.56 +          return;
   33.57 +        }
   33.58 +      }
   33.59 +      ShouldNotReachHere();
   33.60 +    }
   33.61 +  }
   33.62 +
   33.63 +  void print_inlining(ciMethod* method, int inline_level, int bci, const char* msg = NULL) {
   33.64 +    stringStream ss;
   33.65 +    CompileTask::print_inlining(&ss, method, inline_level, bci, msg);
   33.66 +    print_inlining_stream()->print(ss.as_string());
   33.67 +  }
   33.68 +
   33.69 + private:
   33.70    // Matching, CFG layout, allocation, code generation
   33.71    PhaseCFG*             _cfg;                   // Results of CFG finding
   33.72    bool                  _select_24_bit_instr;   // We selected an instruction with a 24-bit result
   33.73 @@ -591,7 +647,7 @@
   33.74    void         reset_dead_node_list()      { _dead_node_list.Reset();
   33.75                                               _dead_node_count = 0;
   33.76                                             }
   33.77 -  uint          live_nodes()               {
   33.78 +  uint          live_nodes() const         {
   33.79      int  val = _unique - _dead_node_count;
   33.80      assert (val >= 0, err_msg_res("number of tracked dead nodes %d more than created nodes %d", _unique, _dead_node_count));
   33.81              return (uint) val;
   33.82 @@ -702,7 +758,7 @@
   33.83  
   33.84    void              identify_useful_nodes(Unique_Node_List &useful);
   33.85    void              update_dead_node_list(Unique_Node_List &useful);
   33.86 -  void              remove_useless_nodes  (Unique_Node_List &useful);
   33.87 +  void              remove_useless_nodes (Unique_Node_List &useful);
   33.88  
   33.89    WarmCallInfo*     warm_calls() const          { return _warm_calls; }
   33.90    void          set_warm_calls(WarmCallInfo* l) { _warm_calls = l; }
   33.91 @@ -711,6 +767,8 @@
   33.92    // Record this CallGenerator for inlining at the end of parsing.
   33.93    void              add_late_inline(CallGenerator* cg) { _late_inlines.push(cg); }
   33.94  
   33.95 +  void dump_inlining();
   33.96 +
   33.97    // Matching, CFG layout, allocation, code generation
   33.98    PhaseCFG*         cfg()                       { return _cfg; }
   33.99    bool              select_24_bit_instr() const { return _select_24_bit_instr; }

    34.1 --- a/src/share/vm/opto/doCall.cpp	Wed Dec 19 16:10:19 2012 -0800
    34.2 +++ b/src/share/vm/opto/doCall.cpp	Fri Dec 21 01:39:34 2012 -0800
    34.3 @@ -40,19 +40,24 @@
    34.4  #include "prims/nativeLookup.hpp"
    34.5  #include "runtime/sharedRuntime.hpp"
    34.6  
    34.7 -void trace_type_profile(ciMethod *method, int depth, int bci, ciMethod *prof_method, ciKlass *prof_klass, int site_count, int receiver_count) {
    34.8 +void trace_type_profile(Compile* C, ciMethod *method, int depth, int bci, ciMethod *prof_method, ciKlass *prof_klass, int site_count, int receiver_count) {
    34.9    if (TraceTypeProfile || PrintInlining NOT_PRODUCT(|| PrintOptoInlining)) {
   34.10 +    outputStream* out = tty;
   34.11      if (!PrintInlining) {
   34.12        if (NOT_PRODUCT(!PrintOpto &&) !PrintCompilation) {
   34.13          method->print_short_name();
   34.14          tty->cr();
   34.15        }
   34.16        CompileTask::print_inlining(prof_method, depth, bci);
   34.17 +    } else {
   34.18 +      out = C->print_inlining_stream();
   34.19      }
   34.20 -    CompileTask::print_inline_indent(depth);
   34.21 -    tty->print(" \\-> TypeProfile (%d/%d counts) = ", receiver_count, site_count);
   34.22 -    prof_klass->name()->print_symbol();
   34.23 -    tty->cr();
   34.24 +    CompileTask::print_inline_indent(depth, out);
   34.25 +    out->print(" \\-> TypeProfile (%d/%d counts) = ", receiver_count, site_count);
   34.26 +    stringStream ss;
   34.27 +    prof_klass->name()->print_symbol_on(&ss);
   34.28 +    out->print(ss.as_string());
   34.29 +    out->cr();
   34.30    }
   34.31  }
   34.32  
   34.33 @@ -233,13 +238,13 @@
   34.34            }
   34.35            if (miss_cg != NULL) {
   34.36              if (next_hit_cg != NULL) {
   34.37 -              trace_type_profile(jvms->method(), jvms->depth() - 1, jvms->bci(), next_receiver_method, profile.receiver(1), site_count, profile.receiver_count(1));
   34.38 +              trace_type_profile(C, jvms->method(), jvms->depth() - 1, jvms->bci(), next_receiver_method, profile.receiver(1), site_count, profile.receiver_count(1));
   34.39                // We don't need to record dependency on a receiver here and below.
   34.40                // Whenever we inline, the dependency is added by Parse::Parse().
   34.41                miss_cg = CallGenerator::for_predicted_call(profile.receiver(1), miss_cg, next_hit_cg, PROB_MAX);
   34.42              }
   34.43              if (miss_cg != NULL) {
   34.44 -              trace_type_profile(jvms->method(), jvms->depth() - 1, jvms->bci(), receiver_method, profile.receiver(0), site_count, receiver_count);
   34.45 +              trace_type_profile(C, jvms->method(), jvms->depth() - 1, jvms->bci(), receiver_method, profile.receiver(0), site_count, receiver_count);
   34.46                CallGenerator* cg = CallGenerator::for_predicted_call(profile.receiver(0), miss_cg, hit_cg, profile.receiver_prob(0));
   34.47                if (cg != NULL)  return cg;
   34.48              }

    35.1 --- a/src/share/vm/opto/graphKit.cpp	Wed Dec 19 16:10:19 2012 -0800
    35.2 +++ b/src/share/vm/opto/graphKit.cpp	Fri Dec 21 01:39:34 2012 -0800
    35.3 @@ -1771,11 +1771,21 @@
    35.4    CallProjections callprojs;
    35.5    call->extract_projections(&callprojs, true);
    35.6  
    35.7 +  Node* init_mem = call->in(TypeFunc::Memory);
    35.8 +  Node* final_mem = final_state->in(TypeFunc::Memory);
    35.9 +  Node* final_ctl = final_state->in(TypeFunc::Control);
   35.10 +  Node* final_io = final_state->in(TypeFunc::I_O);
   35.11 +
   35.12    // Replace all the old call edges with the edges from the inlining result
   35.13 -  C->gvn_replace_by(callprojs.fallthrough_catchproj, final_state->in(TypeFunc::Control));
   35.14 -  C->gvn_replace_by(callprojs.fallthrough_memproj,   final_state->in(TypeFunc::Memory));
   35.15 -  C->gvn_replace_by(callprojs.fallthrough_ioproj,    final_state->in(TypeFunc::I_O));
   35.16 -  Node* final_mem = final_state->in(TypeFunc::Memory);
   35.17 +  if (callprojs.fallthrough_catchproj != NULL) {
   35.18 +    C->gvn_replace_by(callprojs.fallthrough_catchproj, final_ctl);
   35.19 +  }
   35.20 +  if (callprojs.fallthrough_memproj != NULL) {
   35.21 +    C->gvn_replace_by(callprojs.fallthrough_memproj,   final_mem);
   35.22 +  }
   35.23 +  if (callprojs.fallthrough_ioproj != NULL) {
   35.24 +    C->gvn_replace_by(callprojs.fallthrough_ioproj,    final_io);
   35.25 +  }
   35.26  
   35.27    // Replace the result with the new result if it exists and is used
   35.28    if (callprojs.resproj != NULL && result != NULL) {
   35.29 @@ -2980,7 +2990,7 @@
   35.30    set_control( _gvn.transform(new (C) ProjNode(allocx, TypeFunc::Control) ) );
   35.31    // create memory projection for i_o
   35.32    set_memory ( _gvn.transform( new (C) ProjNode(allocx, TypeFunc::Memory, true) ), rawidx );
   35.33 -  make_slow_call_ex(allocx, env()->OutOfMemoryError_klass(), true);
   35.34 +  make_slow_call_ex(allocx, env()->Throwable_klass(), true);
   35.35  
   35.36    // create a memory projection as for the normal control path
   35.37    Node* malloc = _gvn.transform(new (C) ProjNode(allocx, TypeFunc::Memory));

    36.1 --- a/src/share/vm/opto/library_call.cpp	Wed Dec 19 16:10:19 2012 -0800
    36.2 +++ b/src/share/vm/opto/library_call.cpp	Fri Dec 21 01:39:34 2012 -0800
    36.3 @@ -282,6 +282,7 @@
    36.4    typedef enum { LS_xadd, LS_xchg, LS_cmpxchg } LoadStoreKind;
    36.5    bool inline_unsafe_load_store(BasicType type,  LoadStoreKind kind);
    36.6    bool inline_unsafe_ordered_store(BasicType type);
    36.7 +  bool inline_unsafe_fence(vmIntrinsics::ID id);
    36.8    bool inline_fp_conversions(vmIntrinsics::ID id);
    36.9    bool inline_number_methods(vmIntrinsics::ID id);
   36.10    bool inline_reference_get();
   36.11 @@ -334,6 +335,9 @@
   36.12      case vmIntrinsics::_getAndSetInt:
   36.13      case vmIntrinsics::_getAndSetLong:
   36.14      case vmIntrinsics::_getAndSetObject:
   36.15 +    case vmIntrinsics::_loadFence:
   36.16 +    case vmIntrinsics::_storeFence:
   36.17 +    case vmIntrinsics::_fullFence:
   36.18        break;  // InlineNatives does not control String.compareTo
   36.19      case vmIntrinsics::_Reference_get:
   36.20        break;  // InlineNatives does not control Reference.get
   36.21 @@ -536,7 +540,7 @@
   36.22    // Try to inline the intrinsic.
   36.23    if (kit.try_to_inline()) {
   36.24      if (PrintIntrinsics || PrintInlining NOT_PRODUCT( || PrintOptoInlining) ) {
   36.25 -      CompileTask::print_inlining(callee, jvms->depth() - 1, bci, is_virtual() ? "(intrinsic, virtual)" : "(intrinsic)");
   36.26 +      C->print_inlining(callee, jvms->depth() - 1, bci, is_virtual() ? "(intrinsic, virtual)" : "(intrinsic)");
   36.27      }
   36.28      C->gather_intrinsic_statistics(intrinsic_id(), is_virtual(), Compile::_intrinsic_worked);
   36.29      if (C->log()) {
   36.30 @@ -555,7 +559,7 @@
   36.31      if (jvms->has_method()) {
   36.32        // Not a root compile.
   36.33        const char* msg = is_virtual() ? "failed to inline (intrinsic, virtual)" : "failed to inline (intrinsic)";
   36.34 -      CompileTask::print_inlining(callee, jvms->depth() - 1, bci, msg);
   36.35 +      C->print_inlining(callee, jvms->depth() - 1, bci, msg);
   36.36      } else {
   36.37        // Root compile
   36.38        tty->print("Did not generate intrinsic %s%s at bci:%d in",
   36.39 @@ -585,7 +589,7 @@
   36.40    Node* slow_ctl = kit.try_to_predicate();
   36.41    if (!kit.failing()) {
   36.42      if (PrintIntrinsics || PrintInlining NOT_PRODUCT( || PrintOptoInlining) ) {
   36.43 -      CompileTask::print_inlining(callee, jvms->depth() - 1, bci, is_virtual() ? "(intrinsic, virtual)" : "(intrinsic)");
   36.44 +      C->print_inlining(callee, jvms->depth() - 1, bci, is_virtual() ? "(intrinsic, virtual)" : "(intrinsic)");
   36.45      }
   36.46      C->gather_intrinsic_statistics(intrinsic_id(), is_virtual(), Compile::_intrinsic_worked);
   36.47      if (C->log()) {
   36.48 @@ -602,12 +606,12 @@
   36.49      if (jvms->has_method()) {
   36.50        // Not a root compile.
   36.51        const char* msg = "failed to generate predicate for intrinsic";
   36.52 -      CompileTask::print_inlining(kit.callee(), jvms->depth() - 1, bci, msg);
   36.53 +      C->print_inlining(kit.callee(), jvms->depth() - 1, bci, msg);
   36.54      } else {
   36.55        // Root compile
   36.56 -      tty->print("Did not generate predicate for intrinsic %s%s at bci:%d in",
   36.57 -               vmIntrinsics::name_at(intrinsic_id()),
   36.58 -               (is_virtual() ? " (virtual)" : ""), bci);
   36.59 +      C->print_inlining_stream()->print("Did not generate predicate for intrinsic %s%s at bci:%d in",
   36.60 +                                        vmIntrinsics::name_at(intrinsic_id()),
   36.61 +                                        (is_virtual() ? " (virtual)" : ""), bci);
   36.62      }
   36.63    }
   36.64    C->gather_intrinsic_statistics(intrinsic_id(), is_virtual(), Compile::_intrinsic_failed);
   36.65 @@ -732,6 +736,10 @@
   36.66    case vmIntrinsics::_getAndSetLong:            return inline_unsafe_load_store(T_LONG,   LS_xchg);
   36.67    case vmIntrinsics::_getAndSetObject:          return inline_unsafe_load_store(T_OBJECT, LS_xchg);
   36.68  
   36.69 +  case vmIntrinsics::_loadFence:
   36.70 +  case vmIntrinsics::_storeFence:
   36.71 +  case vmIntrinsics::_fullFence:                return inline_unsafe_fence(intrinsic_id());
   36.72 +
   36.73    case vmIntrinsics::_currentThread:            return inline_native_currentThread();
   36.74    case vmIntrinsics::_isInterrupted:            return inline_native_isInterrupted();
   36.75  
   36.76 @@ -2840,6 +2848,26 @@
   36.77    return true;
   36.78  }
   36.79  
   36.80 +bool LibraryCallKit::inline_unsafe_fence(vmIntrinsics::ID id) {
   36.81 +  // Regardless of form, don't allow previous ld/st to move down,
   36.82 +  // then issue acquire, release, or volatile mem_bar.
   36.83 +  insert_mem_bar(Op_MemBarCPUOrder);
   36.84 +  switch(id) {
   36.85 +    case vmIntrinsics::_loadFence:
   36.86 +      insert_mem_bar(Op_MemBarAcquire);
   36.87 +      return true;
   36.88 +    case vmIntrinsics::_storeFence:
   36.89 +      insert_mem_bar(Op_MemBarRelease);
   36.90 +      return true;
   36.91 +    case vmIntrinsics::_fullFence:
   36.92 +      insert_mem_bar(Op_MemBarVolatile);
   36.93 +      return true;
   36.94 +    default:
   36.95 +      fatal_unexpected_iid(id);
   36.96 +      return false;
   36.97 +  }
   36.98 +}
   36.99 +
  36.100  //----------------------------inline_unsafe_allocate---------------------------
  36.101  // public native Object sun.mics.Unsafe.allocateInstance(Class<?> cls);
  36.102  bool LibraryCallKit::inline_unsafe_allocate() {
  36.103 @@ -2952,14 +2980,23 @@
  36.104  
  36.105    // We only go to the fast case code if we pass two guards.
  36.106    // Paths which do not pass are accumulated in the slow_region.
  36.107 +
  36.108 +  enum {
  36.109 +    no_int_result_path   = 1, // t == Thread.current() && !TLS._osthread._interrupted
  36.110 +    no_clear_result_path = 2, // t == Thread.current() &&  TLS._osthread._interrupted && !clear_int
  36.111 +    slow_result_path     = 3, // slow path: t.isInterrupted(clear_int)
  36.112 +    PATH_LIMIT
  36.113 +  };
  36.114 +
  36.115 +  // Ensure that it's not possible to move the load of TLS._osthread._interrupted flag
  36.116 +  // out of the function.
  36.117 +  insert_mem_bar(Op_MemBarCPUOrder);
  36.118 +
  36.119 +  RegionNode* result_rgn = new (C) RegionNode(PATH_LIMIT);
  36.120 +  PhiNode*    result_val = new (C) PhiNode(result_rgn, TypeInt::BOOL);
  36.121 +
  36.122    RegionNode* slow_region = new (C) RegionNode(1);
  36.123    record_for_igvn(slow_region);
  36.124 -  RegionNode* result_rgn = new (C) RegionNode(1+3); // fast1, fast2, slow
  36.125 -  PhiNode*    result_val = new (C) PhiNode(result_rgn, TypeInt::BOOL);
  36.126 -  enum { no_int_result_path   = 1,
  36.127 -         no_clear_result_path = 2,
  36.128 -         slow_result_path     = 3
  36.129 -  };
  36.130  
  36.131    // (a) Receiving thread must be the current thread.
  36.132    Node* rec_thr = argument(0);
  36.133 @@ -2968,14 +3005,13 @@
  36.134    Node* cmp_thr = _gvn.transform( new (C) CmpPNode(cur_thr, rec_thr) );
  36.135    Node* bol_thr = _gvn.transform( new (C) BoolNode(cmp_thr, BoolTest::ne) );
  36.136  
  36.137 -  bool known_current_thread = (_gvn.type(bol_thr) == TypeInt::ZERO);
  36.138 -  if (!known_current_thread)
  36.139 -    generate_slow_guard(bol_thr, slow_region);
  36.140 +  generate_slow_guard(bol_thr, slow_region);
  36.141  
  36.142    // (b) Interrupt bit on TLS must be false.
  36.143    Node* p = basic_plus_adr(top()/*!oop*/, tls_ptr, in_bytes(JavaThread::osthread_offset()));
  36.144    Node* osthread = make_load(NULL, p, TypeRawPtr::NOTNULL, T_ADDRESS);
  36.145    p = basic_plus_adr(top()/*!oop*/, osthread, in_bytes(OSThread::interrupted_offset()));
  36.146 +
  36.147    // Set the control input on the field _interrupted read to prevent it floating up.
  36.148    Node* int_bit = make_load(control(), p, TypeInt::BOOL, T_INT);
  36.149    Node* cmp_bit = _gvn.transform( new (C) CmpINode(int_bit, intcon(0)) );
  36.150 @@ -3020,22 +3056,20 @@
  36.151      Node* slow_val = set_results_for_java_call(slow_call);
  36.152      // this->control() comes from set_results_for_java_call
  36.153  
  36.154 -    // If we know that the result of the slow call will be true, tell the optimizer!
  36.155 -    if (known_current_thread)  slow_val = intcon(1);
  36.156 -
  36.157      Node* fast_io  = slow_call->in(TypeFunc::I_O);
  36.158      Node* fast_mem = slow_call->in(TypeFunc::Memory);
  36.159 +
  36.160      // These two phis are pre-filled with copies of of the fast IO and Memory
  36.161 -    Node* io_phi   = PhiNode::make(result_rgn, fast_io,  Type::ABIO);
  36.162 -    Node* mem_phi  = PhiNode::make(result_rgn, fast_mem, Type::MEMORY, TypePtr::BOTTOM);
  36.163 +    PhiNode* result_mem  = PhiNode::make(result_rgn, fast_mem, Type::MEMORY, TypePtr::BOTTOM);
  36.164 +    PhiNode* result_io   = PhiNode::make(result_rgn, fast_io,  Type::ABIO);
  36.165  
  36.166      result_rgn->init_req(slow_result_path, control());
  36.167 -    io_phi    ->init_req(slow_result_path, i_o());
  36.168 -    mem_phi   ->init_req(slow_result_path, reset_memory());
  36.169 +    result_io ->init_req(slow_result_path, i_o());
  36.170 +    result_mem->init_req(slow_result_path, reset_memory());
  36.171      result_val->init_req(slow_result_path, slow_val);
  36.172  
  36.173 -    set_all_memory( _gvn.transform(mem_phi) );
  36.174 -    set_i_o(        _gvn.transform(io_phi) );
  36.175 +    set_all_memory(_gvn.transform(result_mem));
  36.176 +    set_i_o(       _gvn.transform(result_io));
  36.177    }
  36.178  
  36.179    C->set_has_split_ifs(true); // Has chance for split-if optimization
  36.180 @@ -3319,7 +3353,7 @@
  36.181      Node* arg = args[which_arg];
  36.182      arg = null_check(arg);
  36.183      if (stopped())  break;
  36.184 -    args[which_arg] = _gvn.transform(arg);
  36.185 +    args[which_arg] = arg;
  36.186  
  36.187      Node* p = basic_plus_adr(arg, class_klass_offset);
  36.188      Node* kls = LoadKlassNode::make(_gvn, immutable_memory(), p, adr_type, kls_type);

    37.1 --- a/src/share/vm/opto/parse3.cpp	Wed Dec 19 16:10:19 2012 -0800
    37.2 +++ b/src/share/vm/opto/parse3.cpp	Fri Dec 21 01:39:34 2012 -0800
    37.3 @@ -509,6 +509,7 @@
    37.4                            makecon(TypeKlassPtr::make(array_klass)),
    37.5                            dims);
    37.6    }
    37.7 +  make_slow_call_ex(c, env()->Throwable_klass(), false);
    37.8  
    37.9    Node* res = _gvn.transform(new (C) ProjNode(c, TypeFunc::Parms));
   37.10

    38.1 --- a/src/share/vm/opto/runtime.cpp	Wed Dec 19 16:10:19 2012 -0800
    38.2 +++ b/src/share/vm/opto/runtime.cpp	Fri Dec 21 01:39:34 2012 -0800
    38.3 @@ -989,7 +989,7 @@
    38.4        // since we're notifying the VM on every catch.
    38.5        // Force deoptimization and the rest of the lookup
    38.6        // will be fine.
    38.7 -      deoptimize_caller_frame(thread, true);
    38.8 +      deoptimize_caller_frame(thread);
    38.9      }
   38.10  
   38.11      // Check the stack guard pages.  If enabled, look for handler in this frame;
   38.12 @@ -1143,17 +1143,22 @@
   38.13  
   38.14  
   38.15  void OptoRuntime::deoptimize_caller_frame(JavaThread *thread, bool doit) {
   38.16 -  // Deoptimize frame
   38.17 -  if (doit) {
   38.18 -    // Called from within the owner thread, so no need for safepoint
   38.19 -    RegisterMap reg_map(thread);
   38.20 -    frame stub_frame = thread->last_frame();
   38.21 -    assert(stub_frame.is_runtime_frame() || exception_blob()->contains(stub_frame.pc()), "sanity check");
   38.22 -    frame caller_frame = stub_frame.sender(&reg_map);
   38.23 +  // Deoptimize the caller before continuing, as the compiled
   38.24 +  // exception handler table may not be valid.
   38.25 +  if (!StressCompiledExceptionHandlers && doit) {
   38.26 +    deoptimize_caller_frame(thread);
   38.27 +  }
   38.28 +}
   38.29  
   38.30 -    // Deoptimize the caller frame.
   38.31 -    Deoptimization::deoptimize_frame(thread, caller_frame.id());
   38.32 -  }
   38.33 +void OptoRuntime::deoptimize_caller_frame(JavaThread *thread) {
   38.34 +  // Called from within the owner thread, so no need for safepoint
   38.35 +  RegisterMap reg_map(thread);
   38.36 +  frame stub_frame = thread->last_frame();
   38.37 +  assert(stub_frame.is_runtime_frame() || exception_blob()->contains(stub_frame.pc()), "sanity check");
   38.38 +  frame caller_frame = stub_frame.sender(&reg_map);
   38.39 +
   38.40 +  // Deoptimize the caller frame.
   38.41 +  Deoptimization::deoptimize_frame(thread, caller_frame.id());
   38.42  }
   38.43  
   38.44

    39.1 --- a/src/share/vm/opto/runtime.hpp	Wed Dec 19 16:10:19 2012 -0800
    39.2 +++ b/src/share/vm/opto/runtime.hpp	Fri Dec 21 01:39:34 2012 -0800
    39.3 @@ -174,6 +174,7 @@
    39.4    static address handle_exception_C       (JavaThread* thread);
    39.5    static address handle_exception_C_helper(JavaThread* thread, nmethod*& nm);
    39.6    static address rethrow_C                (oopDesc* exception, JavaThread *thread, address return_pc );
    39.7 +  static void deoptimize_caller_frame     (JavaThread *thread);
    39.8    static void deoptimize_caller_frame     (JavaThread *thread, bool doit);
    39.9    static bool is_deoptimized_caller_frame (JavaThread *thread);
   39.10

    40.1 --- a/src/share/vm/opto/stringopts.cpp	Wed Dec 19 16:10:19 2012 -0800
    40.2 +++ b/src/share/vm/opto/stringopts.cpp	Fri Dec 21 01:39:34 2012 -0800
    40.3 @@ -744,7 +744,9 @@
    40.4        ctrl_path.push(cn);
    40.5        ctrl_path.push(cn->proj_out(0));
    40.6        ctrl_path.push(cn->proj_out(0)->unique_out());
    40.7 -      ctrl_path.push(cn->proj_out(0)->unique_out()->as_Catch()->proj_out(0));
    40.8 +      if (cn->proj_out(0)->unique_out()->as_Catch()->proj_out(0) != NULL) {
    40.9 +        ctrl_path.push(cn->proj_out(0)->unique_out()->as_Catch()->proj_out(0));
   40.10 +      }
   40.11      } else {
   40.12        ShouldNotReachHere();
   40.13      }
   40.14 @@ -762,6 +764,12 @@
   40.15      } else if (ptr->is_IfTrue()) {
   40.16        IfNode* iff = ptr->in(0)->as_If();
   40.17        BoolNode* b = iff->in(1)->isa_Bool();
   40.18 +
   40.19 +      if (b == NULL) {
   40.20 +        fail = true;
   40.21 +        break;
   40.22 +      }
   40.23 +
   40.24        Node* cmp = b->in(1);
   40.25        Node* v1 = cmp->in(1);
   40.26        Node* v2 = cmp->in(2);
   40.27 @@ -1408,71 +1416,76 @@
   40.28                        Deoptimization::Action_make_not_entrant);
   40.29    }
   40.30  
   40.31 -  // length now contains the number of characters needed for the
   40.32 -  // char[] so create a new AllocateArray for the char[]
   40.33 -  Node* char_array = NULL;
   40.34 -  {
   40.35 -    PreserveReexecuteState preexecs(&kit);
   40.36 -    // The original jvms is for an allocation of either a String or
   40.37 -    // StringBuffer so no stack adjustment is necessary for proper
   40.38 -    // reexecution.  If we deoptimize in the slow path the bytecode
   40.39 -    // will be reexecuted and the char[] allocation will be thrown away.
   40.40 -    kit.jvms()->set_should_reexecute(true);
   40.41 -    char_array = kit.new_array(__ makecon(TypeKlassPtr::make(ciTypeArrayKlass::make(T_CHAR))),
   40.42 -                               length, 1);
   40.43 +  Node* result;
   40.44 +  if (!kit.stopped()) {
   40.45 +
   40.46 +    // length now contains the number of characters needed for the
   40.47 +    // char[] so create a new AllocateArray for the char[]
   40.48 +    Node* char_array = NULL;
   40.49 +    {
   40.50 +      PreserveReexecuteState preexecs(&kit);
   40.51 +      // The original jvms is for an allocation of either a String or
   40.52 +      // StringBuffer so no stack adjustment is necessary for proper
   40.53 +      // reexecution.  If we deoptimize in the slow path the bytecode
   40.54 +      // will be reexecuted and the char[] allocation will be thrown away.
   40.55 +      kit.jvms()->set_should_reexecute(true);
   40.56 +      char_array = kit.new_array(__ makecon(TypeKlassPtr::make(ciTypeArrayKlass::make(T_CHAR))),
   40.57 +                                 length, 1);
   40.58 +    }
   40.59 +
   40.60 +    // Mark the allocation so that zeroing is skipped since the code
   40.61 +    // below will overwrite the entire array
   40.62 +    AllocateArrayNode* char_alloc = AllocateArrayNode::Ideal_array_allocation(char_array, _gvn);
   40.63 +    char_alloc->maybe_set_complete(_gvn);
   40.64 +
   40.65 +    // Now copy the string representations into the final char[]
   40.66 +    Node* start = __ intcon(0);
   40.67 +    for (int argi = 0; argi < sc->num_arguments(); argi++) {
   40.68 +      Node* arg = sc->argument(argi);
   40.69 +      switch (sc->mode(argi)) {
   40.70 +        case StringConcat::IntMode: {
   40.71 +          Node* end = __ AddI(start, string_sizes->in(argi));
   40.72 +          // getChars words backwards so pass the ending point as well as the start
   40.73 +          int_getChars(kit, arg, char_array, start, end);
   40.74 +          start = end;
   40.75 +          break;
   40.76 +        }
   40.77 +        case StringConcat::StringNullCheckMode:
   40.78 +        case StringConcat::StringMode: {
   40.79 +          start = copy_string(kit, arg, char_array, start);
   40.80 +          break;
   40.81 +        }
   40.82 +        case StringConcat::CharMode: {
   40.83 +          __ store_to_memory(kit.control(), kit.array_element_address(char_array, start, T_CHAR),
   40.84 +                             arg, T_CHAR, char_adr_idx);
   40.85 +          start = __ AddI(start, __ intcon(1));
   40.86 +          break;
   40.87 +        }
   40.88 +        default:
   40.89 +          ShouldNotReachHere();
   40.90 +      }
   40.91 +    }
   40.92 +
   40.93 +    // If we're not reusing an existing String allocation then allocate one here.
   40.94 +    result = sc->string_alloc();
   40.95 +    if (result == NULL) {
   40.96 +      PreserveReexecuteState preexecs(&kit);
   40.97 +      // The original jvms is for an allocation of either a String or
   40.98 +      // StringBuffer so no stack adjustment is necessary for proper
   40.99 +      // reexecution.
  40.100 +      kit.jvms()->set_should_reexecute(true);
  40.101 +      result = kit.new_instance(__ makecon(TypeKlassPtr::make(C->env()->String_klass())));
  40.102 +    }
  40.103 +
  40.104 +    // Intialize the string
  40.105 +    if (java_lang_String::has_offset_field()) {
  40.106 +      kit.store_String_offset(kit.control(), result, __ intcon(0));
  40.107 +      kit.store_String_length(kit.control(), result, length);
  40.108 +    }
  40.109 +    kit.store_String_value(kit.control(), result, char_array);
  40.110 +  } else {
  40.111 +    result = C->top();
  40.112    }
  40.113 -
  40.114 -  // Mark the allocation so that zeroing is skipped since the code
  40.115 -  // below will overwrite the entire array
  40.116 -  AllocateArrayNode* char_alloc = AllocateArrayNode::Ideal_array_allocation(char_array, _gvn);
  40.117 -  char_alloc->maybe_set_complete(_gvn);
  40.118 -
  40.119 -  // Now copy the string representations into the final char[]
  40.120 -  Node* start = __ intcon(0);
  40.121 -  for (int argi = 0; argi < sc->num_arguments(); argi++) {
  40.122 -    Node* arg = sc->argument(argi);
  40.123 -    switch (sc->mode(argi)) {
  40.124 -      case StringConcat::IntMode: {
  40.125 -        Node* end = __ AddI(start, string_sizes->in(argi));
  40.126 -        // getChars words backwards so pass the ending point as well as the start
  40.127 -        int_getChars(kit, arg, char_array, start, end);
  40.128 -        start = end;
  40.129 -        break;
  40.130 -      }
  40.131 -      case StringConcat::StringNullCheckMode:
  40.132 -      case StringConcat::StringMode: {
  40.133 -        start = copy_string(kit, arg, char_array, start);
  40.134 -        break;
  40.135 -      }
  40.136 -      case StringConcat::CharMode: {
  40.137 -        __ store_to_memory(kit.control(), kit.array_element_address(char_array, start, T_CHAR),
  40.138 -                           arg, T_CHAR, char_adr_idx);
  40.139 -        start = __ AddI(start, __ intcon(1));
  40.140 -        break;
  40.141 -      }
  40.142 -      default:
  40.143 -        ShouldNotReachHere();
  40.144 -    }
  40.145 -  }
  40.146 -
  40.147 -  // If we're not reusing an existing String allocation then allocate one here.
  40.148 -  Node* result = sc->string_alloc();
  40.149 -  if (result == NULL) {
  40.150 -    PreserveReexecuteState preexecs(&kit);
  40.151 -    // The original jvms is for an allocation of either a String or
  40.152 -    // StringBuffer so no stack adjustment is necessary for proper
  40.153 -    // reexecution.
  40.154 -    kit.jvms()->set_should_reexecute(true);
  40.155 -    result = kit.new_instance(__ makecon(TypeKlassPtr::make(C->env()->String_klass())));
  40.156 -  }
  40.157 -
  40.158 -  // Intialize the string
  40.159 -  if (java_lang_String::has_offset_field()) {
  40.160 -    kit.store_String_offset(kit.control(), result, __ intcon(0));
  40.161 -    kit.store_String_length(kit.control(), result, length);
  40.162 -  }
  40.163 -  kit.store_String_value(kit.control(), result, char_array);
  40.164 -
  40.165    // hook up the outgoing control and result
  40.166    kit.replace_call(sc->end(), result);
  40.167

    41.1 --- a/src/share/vm/prims/methodHandles.cpp	Wed Dec 19 16:10:19 2012 -0800
    41.2 +++ b/src/share/vm/prims/methodHandles.cpp	Fri Dec 21 01:39:34 2012 -0800
    41.3 @@ -1168,8 +1168,8 @@
    41.4      // Walk all nmethods depending on this call site.
    41.5      MutexLocker mu(Compile_lock, thread);
    41.6      Universe::flush_dependents_on(call_site, target);
    41.7 +    java_lang_invoke_CallSite::set_target(call_site(), target());
    41.8    }
    41.9 -  java_lang_invoke_CallSite::set_target(call_site(), target());
   41.10  }
   41.11  JVM_END
   41.12  
   41.13 @@ -1180,8 +1180,8 @@
   41.14      // Walk all nmethods depending on this call site.
   41.15      MutexLocker mu(Compile_lock, thread);
   41.16      Universe::flush_dependents_on(call_site, target);
   41.17 +    java_lang_invoke_CallSite::set_target_volatile(call_site(), target());
   41.18    }
   41.19 -  java_lang_invoke_CallSite::set_target_volatile(call_site(), target());
   41.20  }
   41.21  JVM_END
   41.22

    42.1 --- a/src/share/vm/prims/unsafe.cpp	Wed Dec 19 16:10:19 2012 -0800
    42.2 +++ b/src/share/vm/prims/unsafe.cpp	Fri Dec 21 01:39:34 2012 -0800
    42.3 @@ -468,6 +468,21 @@
    42.4  #endif
    42.5  UNSAFE_END
    42.6  
    42.7 +UNSAFE_ENTRY(void, Unsafe_LoadFence(JNIEnv *env, jobject unsafe))
    42.8 +  UnsafeWrapper("Unsafe_LoadFence");
    42.9 +  OrderAccess::acquire();
   42.10 +UNSAFE_END
   42.11 +
   42.12 +UNSAFE_ENTRY(void, Unsafe_StoreFence(JNIEnv *env, jobject unsafe))
   42.13 +  UnsafeWrapper("Unsafe_StoreFence");
   42.14 +  OrderAccess::release();
   42.15 +UNSAFE_END
   42.16 +
   42.17 +UNSAFE_ENTRY(void, Unsafe_FullFence(JNIEnv *env, jobject unsafe))
   42.18 +  UnsafeWrapper("Unsafe_FullFence");
   42.19 +  OrderAccess::fence();
   42.20 +UNSAFE_END
   42.21 +
   42.22  ////// Data in the C heap.
   42.23  
   42.24  // Note:  These do not throw NullPointerException for bad pointers.
   42.25 @@ -1550,6 +1565,9 @@
   42.26      {CC"putOrderedObject",   CC"("OBJ"J"OBJ")V",         FN_PTR(Unsafe_SetOrderedObject)},
   42.27      {CC"putOrderedInt",      CC"("OBJ"JI)V",             FN_PTR(Unsafe_SetOrderedInt)},
   42.28      {CC"putOrderedLong",     CC"("OBJ"JJ)V",             FN_PTR(Unsafe_SetOrderedLong)},
   42.29 +    {CC"loadFence",          CC"()V",                    FN_PTR(Unsafe_LoadFence)},
   42.30 +    {CC"storeFence",         CC"()V",                    FN_PTR(Unsafe_StoreFence)},
   42.31 +    {CC"fullFence",          CC"()V",                    FN_PTR(Unsafe_FullFence)},
   42.32      {CC"park",               CC"(ZJ)V",                  FN_PTR(Unsafe_Park)},
   42.33      {CC"unpark",             CC"("OBJ")V",               FN_PTR(Unsafe_Unpark)}
   42.34

    43.1 --- a/src/share/vm/runtime/globals.hpp	Wed Dec 19 16:10:19 2012 -0800
    43.2 +++ b/src/share/vm/runtime/globals.hpp	Fri Dec 21 01:39:34 2012 -0800
    43.3 @@ -922,6 +922,9 @@
    43.4    develop(bool, PrintExceptionHandlers, false,                              \
    43.5            "Print exception handler tables for all nmethods when generated") \
    43.6                                                                              \
    43.7 +  develop(bool, StressCompiledExceptionHandlers, false,                     \
    43.8 +         "Exercise compiled exception handlers")                            \
    43.9 +                                                                            \
   43.10    develop(bool, InterceptOSException, false,                                \
   43.11            "Starts debugger when an implicit OS (e.g., NULL) "               \
   43.12            "exception happens")                                              \

    44.1 --- a/src/share/vm/runtime/thread.cpp	Wed Dec 19 16:10:19 2012 -0800
    44.2 +++ b/src/share/vm/runtime/thread.cpp	Fri Dec 21 01:39:34 2012 -0800
    44.3 @@ -2190,7 +2190,7 @@
    44.4            // BiasedLocking needs an updated RegisterMap for the revoke monitors pass
    44.5            RegisterMap reg_map(this, UseBiasedLocking);
    44.6            frame compiled_frame = f.sender(&reg_map);
    44.7 -          if (compiled_frame.can_be_deoptimized()) {
    44.8 +          if (!StressCompiledExceptionHandlers && compiled_frame.can_be_deoptimized()) {
    44.9              Deoptimization::deoptimize(this, compiled_frame, &reg_map);
   44.10            }
   44.11          }

    45.1 --- a/test/compiler/7184394/TestAESBase.java	Wed Dec 19 16:10:19 2012 -0800
    45.2 +++ b/test/compiler/7184394/TestAESBase.java	Fri Dec 21 01:39:34 2012 -0800
    45.3 @@ -54,7 +54,6 @@
    45.4    String paddingStr = "PKCS5Padding";
    45.5    AlgorithmParameters algParams;
    45.6    SecretKey key;
    45.7 -  int ivLen;
    45.8  
    45.9    static int numThreads = 0;
   45.10    int  threadId;
   45.11 @@ -68,7 +67,7 @@
   45.12  
   45.13    public void prepare() {
   45.14      try {
   45.15 -    System.out.println("\nmsgSize=" + msgSize + ", key size=" + keySize + ", reInit=" + !noReinit + ", checkOutput=" + checkOutput);
   45.16 +    System.out.println("\nalgorithm=" + algorithm + ", mode=" + mode + ", msgSize=" + msgSize + ", keySize=" + keySize + ", noReinit=" + noReinit + ", checkOutput=" + checkOutput);
   45.17  
   45.18        int keyLenBytes = (keySize == 0 ? 16 : keySize/8);
   45.19        byte keyBytes[] = new byte[keyLenBytes];
   45.20 @@ -90,10 +89,14 @@
   45.21        cipher = Cipher.getInstance(algorithm + "/" + mode + "/" + paddingStr, "SunJCE");
   45.22        dCipher = Cipher.getInstance(algorithm + "/" + mode + "/" + paddingStr, "SunJCE");
   45.23  
   45.24 -      ivLen = (algorithm.equals("AES") ? 16 : algorithm.equals("DES") ? 8 : 0);
   45.25 -      IvParameterSpec initVector = new IvParameterSpec(new byte[ivLen]);
   45.26 -
   45.27 -      cipher.init(Cipher.ENCRYPT_MODE, key, initVector);
   45.28 +      if (mode.equals("CBC")) {
   45.29 +        int ivLen = (algorithm.equals("AES") ? 16 : algorithm.equals("DES") ? 8 : 0);
   45.30 +        IvParameterSpec initVector = new IvParameterSpec(new byte[ivLen]);
   45.31 +        cipher.init(Cipher.ENCRYPT_MODE, key, initVector);
   45.32 +      } else {
   45.33 +        algParams = cipher.getParameters();
   45.34 +        cipher.init(Cipher.ENCRYPT_MODE, key, algParams);
   45.35 +      }
   45.36        algParams = cipher.getParameters();
   45.37        dCipher.init(Cipher.DECRYPT_MODE, key, algParams);
   45.38        if (threadId == 0) {

    46.1 --- a/test/compiler/7184394/TestAESMain.java	Wed Dec 19 16:10:19 2012 -0800
    46.2 +++ b/test/compiler/7184394/TestAESMain.java	Fri Dec 21 01:39:34 2012 -0800
    46.3 @@ -27,7 +27,8 @@
    46.4   * @bug 7184394
    46.5   * @summary add intrinsics to use AES instructions
    46.6   *
    46.7 - * @run main/othervm/timeout=600 -Xbatch -DcheckOutput=true TestAESMain
    46.8 + * @run main/othervm/timeout=600 -Xbatch -DcheckOutput=true -Dmode=CBC TestAESMain
    46.9 + * @run main/othervm/timeout=600 -Xbatch -DcheckOutput=true -Dmode=ECB TestAESMain
   46.10   *
   46.11   * @author Tom Deneau
   46.12   */

    47.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    47.2 +++ b/test/compiler/8004741/Test8004741.java	Fri Dec 21 01:39:34 2012 -0800
    47.3 @@ -0,0 +1,94 @@
    47.4 +/*
    47.5 + * Copyright (c) 2012, Oracle and/or its affiliates. All rights reserved.
    47.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    47.7 + *
    47.8 + * This code is free software; you can redistribute it and/or modify it
    47.9 + * under the terms of the GNU General Public License version 2 only, as
   47.10 + * published by the Free Software Foundation.
   47.11 + *
   47.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
   47.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   47.14 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   47.15 + * version 2 for more details (a copy is included in the LICENSE file that
   47.16 + * accompanied this code).
   47.17 + *
   47.18 + * You should have received a copy of the GNU General Public License version
   47.19 + * 2 along with this work; if not, write to the Free Software Foundation,
   47.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   47.21 + *
   47.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   47.23 + * or visit www.oracle.com if you need additional information or have any
   47.24 + * questions.
   47.25 + */
   47.26 +
   47.27 +/*
   47.28 + * @test Test8004741.java
   47.29 + * @bug 8004741
   47.30 + * @summary Missing compiled exception handle table entry for multidimensional array allocation
   47.31 + * @run main/othervm -Xmx64m -Xbatch -XX:+IgnoreUnrecognizedVMOptions -XX:-TieredCompilation -XX:+StressCompiledExceptionHandlers Test8004741
   47.32 + *
   47.33 + */
   47.34 +
   47.35 +import java.util.*;
   47.36 +
   47.37 +public class Test8004741 extends Thread {
   47.38 +
   47.39 +  static int[][] test(int a, int b) throws Exception {
   47.40 +    int[][] ar = null;
   47.41 +    try {
   47.42 +      ar = new int[a][b];
   47.43 +    } catch (Error e) {
   47.44 +      System.out.println("test got Error");
   47.45 +      passed = true;
   47.46 +      throw(e);
   47.47 +    } catch (Exception e) {
   47.48 +      System.out.println("test got Exception");
   47.49 +      throw(e);
   47.50 +    }
   47.51 +    return ar;
   47.52 +  }
   47.53 +
   47.54 +  static boolean passed = false;
   47.55 +
   47.56 +  public void run() {
   47.57 +      System.out.println("test started");
   47.58 +      try {
   47.59 +        while(true) {
   47.60 +          test(2,20000);
   47.61 +        }
   47.62 +      } catch (ThreadDeath e) {
   47.63 +        System.out.println("test got ThreadDeath");
   47.64 +        passed = true;
   47.65 +      } catch (Error e) {
   47.66 +        e.printStackTrace();
   47.67 +        System.out.println("test got Error");
   47.68 +      } catch (Exception e) {
   47.69 +        e.printStackTrace();
   47.70 +        System.out.println("test got Exception");
   47.71 +      }
   47.72 +  }
   47.73 +
   47.74 +  public static void main(String[] args) throws Exception {
   47.75 +    for (int n = 0; n < 11000; n++) {
   47.76 +      test(2, 20);
   47.77 +    }
   47.78 +
   47.79 +    // First test exception catch
   47.80 +    Test8004741 t = new Test8004741();
   47.81 +
   47.82 +    passed = false;
   47.83 +    t.start();
   47.84 +    Thread.sleep(1000);
   47.85 +    t.stop();
   47.86 +
   47.87 +    Thread.sleep(5000);
   47.88 +    t.join();
   47.89 +    if (passed) {
   47.90 +      System.out.println("PASSED");
   47.91 +    } else {
   47.92 +      System.out.println("FAILED");
   47.93 +      System.exit(97);
   47.94 +    }
   47.95 +  }
   47.96 +
   47.97 +};

    48.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    48.2 +++ b/test/compiler/8005033/Test8005033.java	Fri Dec 21 01:39:34 2012 -0800
    48.3 @@ -0,0 +1,50 @@
    48.4 +/*
    48.5 + * Copyright 2012 SAP AG.  All Rights Reserved.
    48.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    48.7 + *
    48.8 + * This code is free software; you can redistribute it and/or modify it
    48.9 + * under the terms of the GNU General Public License version 2 only, as
   48.10 + * published by the Free Software Foundation.
   48.11 + *
   48.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
   48.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   48.14 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   48.15 + * version 2 for more details (a copy is included in the LICENSE file that
   48.16 + * accompanied this code).
   48.17 + *
   48.18 + * You should have received a copy of the GNU General Public License version
   48.19 + * 2 along with this work; if not, write to the Free Software Foundation,
   48.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   48.21 + *
   48.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   48.23 + * or visit www.oracle.com if you need additional information or have any
   48.24 + * questions.
   48.25 + */
   48.26 +
   48.27 +/**
   48.28 + * @test
   48.29 + * @bug 8005033
   48.30 + * @summary On sparcv9, C2's intrinsic for Integer.bitCount(OV) returns wrong result if OV is the result of an operation with int overflow.
   48.31 + * @run main/othervm -Xcomp -XX:CompileOnly=Test8005033::testBitCount Test8005033
   48.32 + * @author Richard Reingruber richard DOT reingruber AT sap DOT com
   48.33 + */
   48.34 +
   48.35 +public class Test8005033 {
   48.36 +    public static int MINUS_ONE = -1;
   48.37 +
   48.38 +    public static void main(String[] args) {
   48.39 +        System.out.println("EXECUTING test.");
   48.40 +        Integer.bitCount(1);   // load class
   48.41 +        int expectedBitCount = 0;
   48.42 +        int calculatedBitCount = testBitCount();
   48.43 +        if (expectedBitCount != calculatedBitCount) {
   48.44 +            throw new InternalError("got " + calculatedBitCount + " but expected " + expectedBitCount);
   48.45 +        }
   48.46 +        System.out.println("SUCCESSFULLY passed test.");
   48.47 +    }
   48.48 +
   48.49 +    // testBitCount will be compiled using the Integer.bitCount() intrinsic if possible
   48.50 +    private static int testBitCount() {
   48.51 +        return Integer.bitCount(MINUS_ONE+1);   // -1 + 1 => int overflow
   48.52 +    }
   48.53 +}

src/cpu/sparc/vm/templateInterpreter_sparc.cpp		file \| annotate \| diff \| comparison \| revisions
src/share/vm/classfile/classLoaderData.cpp		file \| annotate \| diff \| comparison \| revisions
src/share/vm/opto/library_call.cpp		file \| annotate \| diff \| comparison \| revisions

Mercurial > jdk8-mips64-public > hotspot / changeset

changeset

Merge