Thu, 18 Aug 2016 11:33:16 +0800
Add gsswxc1 and gssdxc1 instructions.
src/cpu/mips/vm/assembler_mips.cpp | file | annotate | diff | comparison | revisions | |
src/cpu/mips/vm/assembler_mips.hpp | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp Thu Aug 18 11:29:03 2016 +0800 1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp Thu Aug 18 11:33:16 2016 +0800 1.3 @@ -234,7 +234,7 @@ 1.4 }; 1.5 1.6 const char* Assembler::gs_sdc2_name[] = { 1.7 - "gssbx", "gsshx", "gsswx", "gssdx", "", "", "", "" 1.8 + "gssbx", "gsshx", "gsswx", "gssdx", "", "", "gsswxc1", "gssdxc1" 1.9 }; 1.10 1.11 //misleading name, print only branch/jump instruction
2.1 --- a/src/cpu/mips/vm/assembler_mips.hpp Thu Aug 18 11:29:03 2016 +0800 2.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp Thu Aug 18 11:33:16 2016 +0800 2.3 @@ -619,7 +619,7 @@ 2.4 gslwx_op = 0x2, 2.5 gsldx_op = 0x3, 2.6 gslwxc1_op = 0x6, 2.7 - gsldxc1_op = 0x7, 2.8 + gsldxc1_op = 0x7 2.9 }; 2.10 2.11 static const char* gs_ldc2_name[]; 2.12 @@ -629,6 +629,8 @@ 2.13 gsshx_op = 0x1, 2.14 gsswx_op = 0x2, 2.15 gssdx_op = 0x3, 2.16 + gsswxc1_op = 0x6, 2.17 + gssdxc1_op = 0x7 2.18 }; 2.19 2.20 static const char* gs_sdc2_name[]; 2.21 @@ -1231,6 +1233,16 @@ 2.22 emit_long((gs_ldc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gslbx_op); 2.23 } 2.24 2.25 + void gssdxc1(Register rt, Register base, Register index, int off) { 2.26 + assert(is_simm(off, 8), "gssdxc1: off exceeds 8 bits"); 2.27 + emit_long((gs_sdc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gssdxc1_op); 2.28 + } 2.29 + 2.30 + void gsswxc1(Register rt, Register base, Register index, int off) { 2.31 + assert(is_simm(off, 8), "gsswxc1: off exceeds 8 bits"); 2.32 + emit_long((gs_sdc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gsswxc1_op); 2.33 + } 2.34 + 2.35 void gssdx(Register rt, Register base, Register index, int off) { 2.36 assert(is_simm(off, 8), "gssdx: off exceeds 8 bits"); 2.37 emit_long((gs_sdc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gssdx_op);