Thu, 18 Aug 2016 15:23:16 +0800
Remove unnecessary sync instructions in mips_64.ad
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Aug 18 14:17:07 2016 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Aug 18 15:23:16 2016 +0800 1.3 @@ -1896,6 +1896,61 @@ 1.4 __ daddu(AT, as_Register(base), as_Register(index)); 1.5 if( Assembler::is_simm16(disp) ) { 1.6 if (value == 0) { 1.7 + __ sb(R0, AT, disp); 1.8 + } else { 1.9 + __ move(T9, value); 1.10 + __ sb(T9, AT, disp); 1.11 + } 1.12 + } else { 1.13 + if (value == 0) { 1.14 + __ move(T9, disp); 1.15 + __ daddu(AT, AT, T9); 1.16 + __ sb(R0, AT, 0); 1.17 + } else { 1.18 + __ move(T9, disp); 1.19 + __ daddu(AT, AT, T9); 1.20 + __ move(T9, value); 1.21 + __ sb(T9, AT, 0); 1.22 + } 1.23 + } 1.24 + } else { 1.25 + if( Assembler::is_simm16(disp) ) { 1.26 + if (value == 0) { 1.27 + __ sb(R0, as_Register(base), disp); 1.28 + } else { 1.29 + __ move(AT, value); 1.30 + __ sb(AT, as_Register(base), disp); 1.31 + } 1.32 + } else { 1.33 + if (value == 0) { 1.34 + __ move(T9, disp); 1.35 + __ daddu(AT, as_Register(base), T9); 1.36 + __ sb(R0, AT, 0); 1.37 + } else { 1.38 + __ move(T9, disp); 1.39 + __ daddu(AT, as_Register(base), T9); 1.40 + __ move(T9, value); 1.41 + __ sb(T9, AT, 0); 1.42 + } 1.43 + } 1.44 + } 1.45 + %} 1.46 + 1.47 + 1.48 + enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{ 1.49 + MacroAssembler _masm(&cbuf); 1.50 + int base = $mem$$base; 1.51 + int index = $mem$$index; 1.52 + int scale = $mem$$scale; 1.53 + int disp = $mem$$disp; 1.54 + int value = $src$$constant; 1.55 + 1.56 + guarantee(scale == 0, "scale is not zero !"); 1.57 + 1.58 + if( index != 0 ) { 1.59 + __ daddu(AT, as_Register(base), as_Register(index)); 1.60 + if( Assembler::is_simm16(disp) ) { 1.61 + if (value == 0) { 1.62 __ sync(); 1.63 __ sb(R0, AT, disp); 1.64 } else { 1.65 @@ -10136,7 +10191,7 @@ 1.66 ins_cost(150); 1.67 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} 1.68 // opcode(0xC6); 1.69 - ins_encode(store_B_immI_enc(mem, src)); 1.70 + ins_encode(store_B_immI_enc_sync(mem, src)); 1.71 ins_pipe( ialu_storeI ); 1.72 %} 1.73