Thu, 18 Aug 2016 11:41:31 +0800
Enable gslwxc1 in load_F_enc for Loongson processors.
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Aug 18 11:33:16 2016 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Aug 18 11:41:31 2016 +0800 1.3 @@ -2695,21 +2695,34 @@ 1.4 guarantee(scale == 0, "scale is not zero !"); 1.5 1.6 if( index != 0 ) { 1.7 - __ daddu(AT, as_Register(base), as_Register(index)); 1.8 if( Assembler::is_simm16(disp) ) { 1.9 - __ lwc1(dst, AT, disp); 1.10 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 1.11 + __ gslwxc1(dst, as_Register(base), as_Register(index), disp); 1.12 + } else { 1.13 + __ daddu(AT, as_Register(base), as_Register(index)); 1.14 + __ lwc1(dst, AT, disp); 1.15 + } 1.16 } else { 1.17 + __ daddu(AT, as_Register(base), as_Register(index)); 1.18 __ move(T9, disp); 1.19 - __ daddu(AT, AT, T9); 1.20 - __ lwc1(dst, AT, 0); 1.21 + if( UseLoongsonISA ) { 1.22 + __ gslwxc1(dst, AT, T9, 0); 1.23 + } else { 1.24 + __ daddu(AT, AT, T9); 1.25 + __ lwc1(dst, AT, 0); 1.26 + } 1.27 } 1.28 } else { 1.29 if( Assembler::is_simm16(disp) ) { 1.30 __ lwc1(dst, as_Register(base), disp); 1.31 } else { 1.32 __ move(T9, disp); 1.33 - __ daddu(AT, as_Register(base), T9); 1.34 - __ lwc1(dst, AT, 0); 1.35 + if( UseLoongsonISA ) { 1.36 + __ gslwxc1(dst, as_Register(base), T9, 0); 1.37 + } else { 1.38 + __ daddu(AT, as_Register(base), T9); 1.39 + __ lwc1(dst, AT, 0); 1.40 + } 1.41 } 1.42 } 1.43 %}