Mon, 23 Mar 2015 10:15:53 +0100
8075136: Unnecessary sign extension for byte array access
Summary: Added C2 matching rules to remove unnecessary sign extension for byte array access.
Reviewed-by: roland, kvn, aph, adinn
src/cpu/x86/vm/x86_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/x86/vm/x86_64.ad Wed Jul 24 21:43:36 2019 +0200 1.2 +++ b/src/cpu/x86/vm/x86_64.ad Mon Mar 23 10:15:53 2015 +0100 1.3 @@ -3740,6 +3740,23 @@ 1.4 %} 1.5 %} 1.6 1.7 +// Indirect Memory Plus Positive Index Register Plus Offset Operand 1.8 +operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx) 1.9 +%{ 1.10 + constraint(ALLOC_IN_RC(ptr_reg)); 1.11 + predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0); 1.12 + match(AddP (AddP reg (ConvI2L idx)) off); 1.13 + 1.14 + op_cost(10); 1.15 + format %{"[$reg + $off + $idx]" %} 1.16 + interface(MEMORY_INTER) %{ 1.17 + base($reg); 1.18 + index($idx); 1.19 + scale(0x0); 1.20 + disp($off); 1.21 + %} 1.22 +%} 1.23 + 1.24 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand 1.25 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) 1.26 %{ 1.27 @@ -3891,6 +3908,23 @@ 1.28 %} 1.29 %} 1.30 1.31 +// Indirect Memory Times Plus Positive Index Register Plus Offset Operand 1.32 +operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx) 1.33 +%{ 1.34 + constraint(ALLOC_IN_RC(ptr_reg)); 1.35 + predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0); 1.36 + match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off); 1.37 + 1.38 + op_cost(10); 1.39 + format %{"[$reg + $off + $idx]" %} 1.40 + interface(MEMORY_INTER) %{ 1.41 + base($reg); 1.42 + index($idx); 1.43 + scale(0x0); 1.44 + disp($off); 1.45 + %} 1.46 +%} 1.47 + 1.48 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand 1.49 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) 1.50 %{ 1.51 @@ -4082,11 +4116,11 @@ 1.52 // case of this is memory operands. 1.53 1.54 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, 1.55 - indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, 1.56 + indIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset, 1.57 indCompressedOopOffset, 1.58 indirectNarrow, indOffset8Narrow, indOffset32Narrow, 1.59 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, 1.60 - indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); 1.61 + indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow); 1.62 1.63 //----------PIPELINE----------------------------------------------------------- 1.64 // Rules which define the behavior of the target architectures pipeline. 1.65 @@ -5120,6 +5154,17 @@ 1.66 ins_pipe(ialu_reg_reg_fat); 1.67 %} 1.68 1.69 +instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem) 1.70 +%{ 1.71 + match(Set dst mem); 1.72 + 1.73 + ins_cost(110); 1.74 + format %{ "leaq $dst, $mem\t# ptr posidxoff" %} 1.75 + opcode(0x8D); 1.76 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 1.77 + ins_pipe(ialu_reg_reg_fat); 1.78 +%} 1.79 + 1.80 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) 1.81 %{ 1.82 match(Set dst mem); 1.83 @@ -5204,6 +5249,18 @@ 1.84 ins_pipe(ialu_reg_reg_fat); 1.85 %} 1.86 1.87 +instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem) 1.88 +%{ 1.89 + predicate(Universe::narrow_oop_shift() == 0); 1.90 + match(Set dst mem); 1.91 + 1.92 + ins_cost(110); 1.93 + format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %} 1.94 + opcode(0x8D); 1.95 + ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 1.96 + ins_pipe(ialu_reg_reg_fat); 1.97 +%} 1.98 + 1.99 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) 1.100 %{ 1.101 predicate(Universe::narrow_oop_shift() == 0);