Add andL_Reg_imm_0_65535 for AndL.

Mon, 22 Aug 2016 17:29:54 +0800

author
fujie
date
Mon, 22 Aug 2016 17:29:54 +0800
changeset 90
a544e350c9c7
parent 89
179d203c9b2b
child 91
c1ec45981302

Add andL_Reg_imm_0_65535 for AndL.

* Before Opt.
li S1, #7 #@loadConL
AND S0, S0, S1 @ andL_Reg_Reg

* After Opt.
AND S0, S0, 7 @ andL_Reg_imm_0_65535

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu Aug 25 22:31:58 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Mon Aug 22 17:29:54 2016 +0800
     1.3 @@ -3531,6 +3531,15 @@
     1.4    interface(CONST_INTER);
     1.5  %}
     1.6  
     1.7 +operand immL_0_65535() %{
     1.8 +  predicate( n->get_long() >= 0 && n->get_long() <= 65535 );
     1.9 +  match(ConL);
    1.10 +  op_cost(0);
    1.11 +
    1.12 +  format %{ %}
    1.13 +  interface(CONST_INTER);
    1.14 +%}
    1.15 +
    1.16  
    1.17  // Long Immediate: low 32-bit mask
    1.18  operand immL_32bits() %{
    1.19 @@ -8968,6 +8977,21 @@
    1.20    ins_pipe( ialu_regL_regL );
    1.21  %}
    1.22  
    1.23 +instruct andL_Reg_imm_0_65535(mRegL dst, mRegL src1,  immL_0_65535 src2) %{
    1.24 +  match(Set dst (AndL src1 src2));
    1.25 +  ins_cost(60);
    1.26 +
    1.27 +  format %{ "and  $dst, $src1, $src2 #@andL_Reg_imm_0_65535" %}
    1.28 +  ins_encode %{
    1.29 +    Register dst = $dst$$Register;
    1.30 +    Register src = $src1$$Register;
    1.31 +    long     val = $src2$$constant;
    1.32 +    
    1.33 +       __ andi(dst, src, val);
    1.34 +  %}
    1.35 +  ins_pipe( ialu_regI_regI );
    1.36 +%}
    1.37 +
    1.38  // Or Long Register with Register
    1.39  instruct orL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
    1.40    match(Set dst (OrL src1 src2));

mercurial