Sync after card marking in C2 compiler.

Sun, 25 Sep 2016 17:38:33 -0400

author
fujie
date
Sun, 25 Sep 2016 17:38:33 -0400
changeset 115
9f3a515f06ee
parent 114
eb8a5893f3c4
child 116
09e17e497778

Sync after card marking in C2 compiler.

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Mon Sep 26 14:38:30 2016 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Sun Sep 25 17:38:33 2016 -0400
     1.3 @@ -1947,56 +1947,52 @@
     1.4  
     1.5       guarantee(scale == 0, "scale is not zero !");
     1.6  
     1.7 +     __ sync();
     1.8 +
     1.9       if( index != 0 ) {
    1.10          __ daddu(AT, as_Register(base), as_Register(index));
    1.11          if( Assembler::is_simm16(disp) ) { 
    1.12             if (value == 0) {
    1.13 -              __ sync();
    1.14                __ sb(R0, AT, disp);
    1.15             } else {
    1.16                __ move(T9, value);
    1.17 -              __ sync();
    1.18                __ sb(T9, AT, disp);
    1.19             }
    1.20          } else {
    1.21             if (value == 0) {
    1.22                __ move(T9, disp);
    1.23                __ daddu(AT, AT, T9); 
    1.24 -              __ sync();
    1.25                __ sb(R0, AT, 0);
    1.26             } else {
    1.27                __ move(T9, disp);
    1.28                __ daddu(AT, AT, T9); 
    1.29                __ move(T9, value);
    1.30 -              __ sync();
    1.31                __ sb(T9, AT, 0);
    1.32             }
    1.33          }    
    1.34       } else {
    1.35          if( Assembler::is_simm16(disp) ) { 
    1.36             if (value == 0) {
    1.37 -              __ sync();
    1.38                __ sb(R0, as_Register(base), disp);
    1.39             } else {
    1.40                __ move(AT, value);
    1.41 -              __ sync();
    1.42                __ sb(AT, as_Register(base), disp);
    1.43             }
    1.44          } else {
    1.45             if (value == 0) {
    1.46                __ move(T9, disp);   
    1.47                __ daddu(AT, as_Register(base), T9); 
    1.48 -              __ sync();
    1.49                __ sb(R0, AT, 0);
    1.50             } else {
    1.51                __ move(T9, disp);   
    1.52                __ daddu(AT, as_Register(base), T9); 
    1.53                __ move(T9, value);
    1.54 -              __ sync();
    1.55                __ sb(T9, AT, 0);
    1.56             }
    1.57          }    
    1.58       }
    1.59 +
    1.60 +     __ sync();
    1.61    %}
    1.62  
    1.63    // Load Short (16bit signed)

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