Thu, 18 Aug 2016 11:12:52 +0800
Add subL_Reg_RegI2L and subL_RegI2L_Reg in mips_64.ad
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Aug 18 10:16:47 2016 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Thu Aug 18 11:12:52 2016 +0800 1.3 @@ -8382,6 +8382,34 @@ 1.4 ins_pipe( ialu_regL_regL ); 1.5 %} 1.6 1.7 +instruct subL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{ 1.8 + match(Set dst (SubL src1 (ConvI2L src2))); 1.9 + ins_cost(200); 1.10 + format %{ "SubL $dst, $src1, $src2 @ subL_Reg_RegI2L" %} 1.11 + ins_encode %{ 1.12 + Register dst = as_Register($dst$$reg); 1.13 + Register src1 = as_Register($src1$$reg); 1.14 + Register src2 = as_Register($src2$$reg); 1.15 + 1.16 + __ subu(dst, src1, src2); 1.17 + %} 1.18 + ins_pipe( ialu_regL_regL ); 1.19 +%} 1.20 + 1.21 +instruct subL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{ 1.22 + match(Set dst (SubL (ConvI2L src1) src2)); 1.23 + ins_cost(200); 1.24 + format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_Reg" %} 1.25 + ins_encode %{ 1.26 + Register dst = as_Register($dst$$reg); 1.27 + Register src1 = as_Register($src1$$reg); 1.28 + Register src2 = as_Register($src2$$reg); 1.29 + 1.30 + __ subu(dst, src1, src2); 1.31 + %} 1.32 + ins_pipe( ialu_regL_regL ); 1.33 +%} 1.34 + 1.35 // Integer MOD with Register 1.36 instruct modI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ 1.37 match(Set dst (ModI src1 src2));