Wed, 17 Aug 2016 17:20:44 +0800
Performance of integer array operation is about 8% up.
public class Test {
public static void main(String[] args) {
int LEN = 40000000;
int[] data = new int[LEN];
long result = 0;
for(int j = 0; j < 100; j++)
for(int i = 0; i < LEN; i++){
result += data[i];
}
System.out.println("result = " + result);
}
}
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Wed Aug 17 15:26:28 2016 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Wed Aug 17 17:20:44 2016 +0800 1.3 @@ -2035,21 +2035,34 @@ 1.4 guarantee(scale == 0, "scale is not zero !"); 1.5 1.6 if( index != 0 ) { 1.7 - __ addu(AT, as_Register(base), as_Register(index)); 1.8 if( Assembler::is_simm16(disp) ) { 1.9 - __ lw(as_Register(dst), AT, disp); 1.10 + if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) { 1.11 + __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp); 1.12 + } else { 1.13 + __ addu(AT, as_Register(base), as_Register(index)); 1.14 + __ lw(as_Register(dst), AT, disp); 1.15 + } 1.16 } else { 1.17 + __ addu(AT, as_Register(base), as_Register(index)); 1.18 __ move(T9, disp); 1.19 - __ addu(AT, AT, T9); 1.20 - __ lw(as_Register(dst), AT, 0); 1.21 + if( UseLoongsonISA ) { 1.22 + __ gslwx(as_Register(dst), AT, T9, 0); 1.23 + } else { 1.24 + __ addu(AT, AT, T9); 1.25 + __ lw(as_Register(dst), AT, 0); 1.26 + } 1.27 } 1.28 } else { 1.29 if( Assembler::is_simm16(disp) ) { 1.30 __ lw(as_Register(dst), as_Register(base), disp); 1.31 } else { 1.32 __ move(T9, disp); 1.33 - __ addu(AT, as_Register(base), T9); 1.34 - __ lw(as_Register(dst), AT, 0); 1.35 + if( UseLoongsonISA ) { 1.36 + __ gslwx(as_Register(dst), as_Register(base), T9, 0); 1.37 + } else { 1.38 + __ addu(AT, as_Register(base), T9); 1.39 + __ lw(as_Register(dst), AT, 0); 1.40 + } 1.41 } 1.42 } 1.43 %} 1.44 @@ -4710,6 +4723,15 @@ 1.45 ins_pipe( ialu_loadI ); 1.46 %} 1.47 1.48 +instruct loadI_convI2L(mRegL dst, memory mem) %{ 1.49 + match(Set dst (ConvI2L (LoadI mem))); 1.50 + 1.51 + ins_cost(125); 1.52 + format %{ "lw $dst, $mem #@loadI_convI2L" %} 1.53 + ins_encode (load_I_enc(dst, mem)); 1.54 + ins_pipe( ialu_loadI ); 1.55 +%} 1.56 + 1.57 // Load Long. 1.58 instruct loadL(mRegL dst, memory mem) %{ 1.59 // predicate(!((LoadLNode*)n)->require_atomic_access());