Sync in generate_disjoint_int_oop_copy and refine it.

Mon, 26 Sep 2016 11:52:55 +0800

author
fujie
date
Mon, 26 Sep 2016 11:52:55 +0800
changeset 109
6220e2d98a3e
parent 108
278f5d19c0bd
child 110
3ea2bda83fb6

Sync in generate_disjoint_int_oop_copy and refine it.

src/cpu/mips/vm/stubGenerator_mips_64.cpp file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/stubGenerator_mips_64.cpp	Thu Sep 22 07:41:28 2016 -0400
     1.2 +++ b/src/cpu/mips/vm/stubGenerator_mips_64.cpp	Mon Sep 26 11:52:55 2016 +0800
     1.3 @@ -1185,83 +1185,55 @@
     1.4    //   used by generate_conjoint_int_oop_copy().
     1.5    //
     1.6    address generate_disjoint_int_oop_copy(bool aligned, bool is_oop, const char *name) {
     1.7 -		Label l_2, l_3, l_4, l_stchk;
     1.8 +		Label l_3, l_4;
     1.9  		StubCodeMark mark(this, "StubRoutines", name);
    1.10  		__ align(CodeEntryAlignment);
    1.11  		address start = __ pc();
    1.12 -		/*
    1.13 -			 __ pushl(esi);
    1.14 -			 __ movl(ecx, Address(esp, 4+12));      // count
    1.15 -			 __ pushl(edi);
    1.16 -			 __ movl(esi, Address(esp, 8+ 4));      // from
    1.17 -			 __ movl(edi, Address(esp, 8+ 8));      // to
    1.18 -		 */
    1.19 +
    1.20  		__ push(T3);	
    1.21  		__ push(T0);	
    1.22  		__ push(T1);	
    1.23  		__ push(T8);	
    1.24 +
    1.25  		__ move(T1, A2);  
    1.26  		__ move(T3, A0); 
    1.27  		__ move(T0, A1);
    1.28  
    1.29 -		// __ cmpl(ecx, 32);
    1.30 -		// __ jcc(Assembler::belowEqual, l_2);                   // <= 32 dwords
    1.31 -		// __ rep_movl();
    1.32 -		__ b(l_2); 	
    1.33 -		__ delayed()->nop();	
    1.34  		if (is_oop) {
    1.35 -		//  __ jmp(l_stchk);
    1.36 -			__ b(l_stchk); 
    1.37 -			__ delayed()->nop(); 
    1.38 +			__ sync();
    1.39  		}
    1.40 -		//    __ popl(edi);
    1.41 -		//   __ popl(esi);
    1.42 -		//  __ ret(0);
    1.43 -		__ pop(T8);	
    1.44 -		__ pop(T1);	
    1.45 -		__ pop(T0);	
    1.46 -		__ pop(T3);	
    1.47 -		__ jr(RA); 
    1.48 +
    1.49 +                // T3: source array address 
    1.50 +                // T0: destination array address
    1.51 +                // T1: element count
    1.52 +		__ beq(T1, R0, l_4);  
    1.53  		__ delayed()->nop(); 
    1.54  
    1.55 -		__ bind(l_2);
    1.56 -		//  __ subl(edi, esi);
    1.57 -		//  __ testl(ecx, ecx);
    1.58 -		// __ jcc(Assembler::zero, l_4);
    1.59 -		__ beq(T1, R0, l_4);  
    1.60 -		__ delayed()->nop(); 
    1.61  		__ align(16);
    1.62  		__ bind(l_3);
    1.63 -		//__ movl(edx, Address(esi));
    1.64  		__ lw(AT, T3, 0);   
    1.65 -		// __ movl(Address(edi, esi, Address::times_1), edx);
    1.66  		__ sw(AT, T0, 0); 
    1.67 -		// __ addl(esi, 4);
    1.68  		__ addi(T3, T3, 4);
    1.69  		__ addi(T0, T0, 4);
    1.70 -		//   __ decl(ecx);
    1.71  		__ addi(T1, T1, -1); 
    1.72 -		//    __ jcc(Assembler::notEqual, l_3);
    1.73  		__ bne(T1, R0, l_3); 
    1.74  		__ delayed()->nop(); 
    1.75 +
    1.76 +		__ bind(l_4);
    1.77  		if (is_oop) {
    1.78 -			__ bind(l_stchk);
    1.79 -			//      __ movl(edi, Address(esp, 8+ 8));
    1.80 -			//     __ movl(ecx, Address(esp, 8+ 12));
    1.81  			__ move(T0, A1); 
    1.82  			__ move(T1, A2); 
    1.83  			array_store_check();
    1.84 +                        __ sync();
    1.85  		}
    1.86 -		__ bind(l_4);
    1.87 -		//    __ popl(edi);
    1.88 -		//   __ popl(esi);
    1.89 -		//  __ ret(0);
    1.90 +                // exit
    1.91  		__ pop(T8);
    1.92  		__ pop(T1);
    1.93  		__ pop(T0);
    1.94  		__ pop(T3);
    1.95  		__ jr(RA); 
    1.96  		__ delayed()->nop(); 
    1.97 +
    1.98  		return start;
    1.99  	}
   1.100  

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