Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/nativeInst_mips.cpp	Wed Jun 13 11:47:13 2018 +0800
     1.2 +++ b/src/cpu/mips/vm/nativeInst_mips.cpp	Wed Jun 13 15:14:39 2018 +0800
     1.3 @@ -1133,13 +1133,12 @@
     1.4    tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
     1.5  }
     1.6  
     1.7 +bool NativeInstruction::is_sigill_zombie_not_entrant() {
     1.8 +  return uint_at(0) == NativeIllegalInstruction::instruction_code;
     1.9 +}
    1.10 +
    1.11  void NativeIllegalInstruction::insert(address code_pos) {
    1.12 -  CodeBuffer cb(code_pos, instruction_size);
    1.13 -  MacroAssembler masm(&cb);
    1.14 -#define __ masm.
    1.15 -  __ brk(11);
    1.16 -#undef __
    1.17 -
    1.18 +  *(juint*)code_pos = instruction_code;
    1.19    ICache::invalidate_range(code_pos, instruction_size);
    1.20  }
    1.21  
    1.22 @@ -1608,20 +1607,27 @@
    1.23    /* 2013/11/5 Jin: ensure 100% atomicity.
    1.24     * The destination is fixed and can be cached in JavaThread.
    1.25     */
    1.26 -  guarantee(!os::is_MP() || (((long)verified_entry % BytesPerWord) == 0), "destination must be aligned for SD");
    1.27 +  // Destination must be aligned for GSSQ.
    1.28 +  bool is_aligned = !os::is_MP() || (((long)verified_entry % (BytesPerWord * 2)) == 0);
    1.29  
    1.30 -  int code_buffer[4];
    1.31 +  if (UseLoongsonISA && is_aligned) {
    1.32 +    int code_buffer[4];
    1.33  
    1.34 -  CodeBuffer cb((address)code_buffer, instruction_size);
    1.35 -  MacroAssembler masm(&cb);
    1.36 +    CodeBuffer cb((address)code_buffer, instruction_size);
    1.37 +    MacroAssembler masm(&cb);
    1.38  #define __ masm.
    1.39 -  __ ld(T9, TREG, in_bytes(JavaThread::handle_wrong_method_stub_offset()));
    1.40 -  __ jr(T9);
    1.41 -  __ delayed()->nop();
    1.42 -  __ nop();
    1.43 +    __ ld(T9, TREG, in_bytes(JavaThread::handle_wrong_method_stub_offset()));
    1.44 +    __ jr(T9);
    1.45 +    __ delayed()->nop();
    1.46 +    __ nop();
    1.47  
    1.48 -  atomic_store128_ptr func = get_atomic_store128_func();
    1.49 -  (*func)((long *)verified_entry, 0, *(long *)&code_buffer[0], *(long *)&code_buffer[2]);
    1.50 +    atomic_store128_ptr func = get_atomic_store128_func();
    1.51 +    (*func)((long *)verified_entry, 0, *(long *)&code_buffer[0], *(long *)&code_buffer[2]);
    1.52 +  } else {
    1.53 +    // We use an illegal instruction for marking a method as
    1.54 +    // not_entrant or zombie
    1.55 +    NativeIllegalInstruction::insert(verified_entry);
    1.56 +  }
    1.57  
    1.58    ICache::invalidate_range(verified_entry, instruction_size);
    1.59  }

     2.1 --- a/src/cpu/mips/vm/nativeInst_mips.hpp	Wed Jun 13 11:47:13 2018 +0800
     2.2 +++ b/src/cpu/mips/vm/nativeInst_mips.hpp	Wed Jun 13 15:14:39 2018 +0800
     2.3 @@ -77,6 +77,8 @@
     2.4    bool is_int_branch();
     2.5    bool is_float_branch();
     2.6  
     2.7 +  //We use an illegal instruction for marking a method as not_entrant or zombie.
     2.8 +  bool is_sigill_zombie_not_entrant();
     2.9  
    2.10   protected:
    2.11    address addr_at(int offset) const    { return address(this) + offset; }
    2.12 @@ -88,6 +90,7 @@
    2.13    u_char ubyte_at(int offset) const    { return *(u_char*) addr_at(offset); }
    2.14  
    2.15    jint int_at(int offset) const         { return *(jint*) addr_at(offset); }
    2.16 +  juint uint_at(int offset) const       { return *(juint*) addr_at(offset); }
    2.17  
    2.18    intptr_t ptr_at(int offset) const    { return *(intptr_t*) addr_at(offset); }
    2.19  
    2.20 @@ -465,7 +468,8 @@
    2.21  
    2.22  class NativeIllegalInstruction: public NativeInstruction {
    2.23  public:
    2.24 -  enum Intel_specific_constants {
    2.25 +  enum mips_specific_constants {
    2.26 +    instruction_code          =    0x42000029,    // mips reserved instruction
    2.27      instruction_size          =    4,
    2.28      instruction_offset        =    0,
    2.29      next_instruction_offset   =    4

     3.1 --- a/src/os_cpu/linux_mips/vm/os_linux_mips.cpp	Wed Jun 13 11:47:13 2018 +0800
     3.2 +++ b/src/os_cpu/linux_mips/vm/os_linux_mips.cpp	Wed Jun 13 15:14:39 2018 +0800
     3.3 @@ -360,7 +360,13 @@
     3.4        tty->print("java thread running in java code\n");
     3.5  #endif
     3.6  
     3.7 -      if (sig == SIGSEGV && os::is_poll_address((address)info->si_addr)) {
     3.8 +      // Handle signal from NativeJump::patch_verified_entry().
     3.9 +      if (sig == SIGILL & nativeInstruction_at(pc)->is_sigill_zombie_not_entrant()) {
    3.10 +#ifdef PRINT_SIGNAL_HANDLE
    3.11 +        tty->print_cr("verified entry = %lx, sig=%d", nativeInstruction_at(pc), sig);
    3.12 +#endif
    3.13 +        stub = SharedRuntime::get_handle_wrong_method_stub();
    3.14 +      } else if (sig == SIGSEGV && os::is_poll_address((address)info->si_addr)) {
    3.15  #ifdef PRINT_SIGNAL_HANDLE
    3.16          tty->print_cr("polling address = %lx, sig=%d", os::get_polling_page(), sig);
    3.17  #endif