Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/sparc/vm/vm_version_sparc.cpp	Fri Mar 17 03:39:23 2017 -0700
     1.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp	Fri Mar 31 01:25:26 2017 -0700
     1.3 @@ -259,49 +259,6 @@
     1.4    // buf is started with ", " or is empty
     1.5    _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
     1.6  
     1.7 -  // There are three 64-bit SPARC families that do not overlap, e.g.,
     1.8 -  // both is_ultra3() and is_sparc64() cannot be true at the same time.
     1.9 -  // Within these families, there can be more than one chip, e.g.,
    1.10 -  // is_T4() and is_T7() machines are also is_niagara().
    1.11 -  if (is_ultra3()) {
    1.12 -    assert(_L1_data_cache_line_size == 0, "overlap with Ultra3 family");
    1.13 -    // Ref: UltraSPARC III Cu Processor
    1.14 -    _L1_data_cache_line_size = 64;
    1.15 -  }
    1.16 -  if (is_niagara()) {
    1.17 -    assert(_L1_data_cache_line_size == 0, "overlap with niagara family");
    1.18 -    // All Niagara's are sun4v's, but not all sun4v's are Niagaras, e.g.,
    1.19 -    // Fujitsu SPARC64 is sun4v, but we don't want it in this block.
    1.20 -    //
    1.21 -    // Ref: UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
    1.22 -    // Appendix F.1.3.1 Cacheable Accesses
    1.23 -    // -> 16-byte L1 cache line size
    1.24 -    //
    1.25 -    // Ref: UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC
    1.26 -    // Section III: SPARC Processor Core
    1.27 -    // -> 16-byte L1 cache line size
    1.28 -    //
    1.29 -    // Ref: Oracle's SPARC T4-1, SPARC T4-2, SPARC T4-4, and SPARC T4-1B Server Architecture
    1.30 -    // Section SPARC T4 Processor Cache Architecture
    1.31 -    // -> 32-byte L1 cache line size (no longer see that info on this ref)
    1.32 -    //
    1.33 -    // XXX - still need a T7 reference here
    1.34 -    //
    1.35 -    if (is_T7()) {  // T7 or newer
    1.36 -      _L1_data_cache_line_size = 64;
    1.37 -    } else if (is_T4()) {  // T4 or newer (until T7)
    1.38 -      _L1_data_cache_line_size = 32;
    1.39 -    } else {  // T1 or newer (until T4)
    1.40 -      _L1_data_cache_line_size = 16;
    1.41 -    }
    1.42 -  }
    1.43 -  if (is_sparc64()) {
    1.44 -    guarantee(_L1_data_cache_line_size == 0, "overlap with SPARC64 family");
    1.45 -    // Ref: Fujitsu SPARC64 VII Processor
    1.46 -    // Section 4 Cache System
    1.47 -    _L1_data_cache_line_size = 64;
    1.48 -  }
    1.49 -
    1.50    // UseVIS is set to the smallest of what hardware supports and what
    1.51    // the command line requires.  I.e., you cannot set UseVIS to 3 on
    1.52    // older UltraSparc which do not support it.