8080012: JVM times out with vdbench on SPARC M7-16

Mon, 06 Jul 2015 10:33:54 -0700

author
poonam
date
Mon, 06 Jul 2015 10:33:54 -0700
changeset 8045
4b6e79c930bf
parent 8044
c7b266ea9a54
child 8046
a7c52c776c30

8080012: JVM times out with vdbench on SPARC M7-16
Summary: check cacheline sine only for one core on sun4v SPARC systems.
Reviewed-by: kvn

src/os_cpu/solaris_sparc/vm/vm_version_solaris_sparc.cpp file | annotate | diff | comparison | revisions
     1.1 --- a/src/os_cpu/solaris_sparc/vm/vm_version_solaris_sparc.cpp	Mon Jul 06 06:48:11 2015 -0700
     1.2 +++ b/src/os_cpu/solaris_sparc/vm/vm_version_solaris_sparc.cpp	Mon Jul 06 10:33:54 2015 -0700
     1.3 @@ -189,7 +189,7 @@
     1.4      return CPUVisitor::visit(nodeh, state);
     1.5    }
     1.6  
     1.7 -  PICL(bool is_fujitsu) : _L1_data_cache_line_size(0), _L2_data_cache_line_size(0), _dl_handle(NULL) {
     1.8 +  PICL(bool is_fujitsu, bool is_sun4v) : _L1_data_cache_line_size(0), _L2_data_cache_line_size(0), _dl_handle(NULL) {
     1.9      if (!open_library()) {
    1.10        return;
    1.11      }
    1.12 @@ -201,7 +201,7 @@
    1.13          if (is_fujitsu) {
    1.14            cpu_class = "core";
    1.15          }
    1.16 -        CPUVisitor cpu_visitor(this, os::processor_count());
    1.17 +        CPUVisitor cpu_visitor(this, (is_sun4v && !is_fujitsu) ? 1 : os::processor_count());
    1.18          _picl_walk_tree_by_class(rooth, cpu_class, &cpu_visitor, PICL_visit_cpu_helper);
    1.19          if (cpu_visitor.l1_visitor()->is_assigned()) { // Is there a value?
    1.20            _L1_data_cache_line_size = cpu_visitor.l1_visitor()->value();
    1.21 @@ -494,7 +494,7 @@
    1.22    }
    1.23  
    1.24    // Figure out cache line sizes using PICL
    1.25 -  PICL picl((features & sparc64_family_m) != 0);
    1.26 +  PICL picl((features & sparc64_family_m) != 0, (features & sun4v_m) != 0);
    1.27    _L2_data_cache_line_size = picl.L2_data_cache_line_size();
    1.28  
    1.29    return features;

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