[C2] Add salI_Reg_imm_and_M65536 in mips_64.ad

Mon, 20 Feb 2017 22:24:57 +0800

author
fujie
date
Mon, 20 Feb 2017 22:24:57 +0800
changeset 324
475de74e90f3
parent 323
f057d4f1922f
child 325
6e68a953851f

[C2] Add salI_Reg_imm_and_M65536 in mips_64.ad

src/cpu/mips/vm/mips_64.ad file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Mon Feb 20 22:13:56 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Mon Feb 20 22:24:57 2017 +0800
     1.3 @@ -3791,6 +3791,15 @@
     1.4    interface(CONST_INTER);
     1.5  %}
     1.6  
     1.7 +operand immI_M65536() %{
     1.8 +  predicate( n->get_int() == -65536 );
     1.9 +  match(ConI);
    1.10 +
    1.11 +  op_cost(5);
    1.12 +  format %{ %}
    1.13 +  interface(CONST_INTER);
    1.14 +%}
    1.15 +
    1.16  // Pointer Immediate
    1.17  operand immP() %{
    1.18    match(ConP);
    1.19 @@ -10759,6 +10768,19 @@
    1.20    ins_pipe( ialu_regI_regI );
    1.21  %}
    1.22  
    1.23 +instruct salI_Reg_imm_and_M65536(mRegI dst, mRegI src, immI_16 shift, immI_M65536 mask) %{
    1.24 +  match(Set dst (AndI (LShiftI src shift) mask));
    1.25 +
    1.26 +  format %{ "SHL    $dst, $src, $shift #@salI_Reg_imm_and_M65536" %}
    1.27 +  ins_encode %{
    1.28 +    Register src = $src$$Register;
    1.29 +    Register dst = $dst$$Register;
    1.30 +
    1.31 +    __ sll(dst, src, 16);
    1.32 +  %}
    1.33 +  ins_pipe( ialu_regI_regI );
    1.34 +%}
    1.35 +
    1.36  instruct land7_2_s(mRegI dst, mRegL src, immL7 seven, immI_16 sixteen)
    1.37  %{
    1.38    match(Set dst (RShiftI (LShiftI (ConvL2I (AndL src seven)) sixteen) sixteen));

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